zs.c revision 1.4
1 /* $NetBSD: zs.c,v 1.4 2000/03/06 21:36:10 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 /* 47 * news68k/dev/zs.c - based on {newsmips,x68k,mvme68k}/dev/zs.c 48 */ 49 50 #include "opt_ddb.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/conf.h> 55 #include <sys/device.h> 56 #include <sys/tty.h> 57 58 #include <machine/cpu.h> 59 #include <machine/z8530var.h> 60 61 #include <dev/cons.h> 62 #include <dev/ic/z8530reg.h> 63 64 #include <news68k/dev/hbvar.h> 65 66 #include "zsc.h" /* NZSC */ 67 #define NZS NZSC 68 69 /* Make life easier for the initialized arrays here. */ 70 #if NZS < 2 71 #undef NZS 72 #define NZS 2 73 #endif 74 75 struct zschan *zs_get_chan_addr __P((int, int)); 76 77 int zs_getc __P((void *)); 78 void zs_putc __P((void *, int)); 79 80 extern void Debugger __P((void)); 81 82 /* 83 * Some warts needed by z8530tty.c - 84 * The default parity REALLY needs to be the same as the PROM uses, 85 * or you can not see messages done with printf during boot-up... 86 */ 87 int zs_def_cflag = (CREAD | CS8 | HUPCL); 88 int zs_major = 1; 89 90 /* 91 * The news68k machines use three different clocks for the ZS chips. 92 */ 93 #define NPCLK 3 94 #define PCLK0 (9600 * 416) /* news1700: 3.9936MHz */ 95 #define PCLK1 (9600 * 512) /* news1200: 4.9152MHz */ 96 #define PCLK2 (9600 * 384) /* external: 3.6864MHz */ 97 98 static const u_int pclk[NPCLK] = { 99 PCLK0, 100 PCLK1, 101 PCLK2, 102 }; 103 104 /* 105 * Define interrupt levels. 106 */ 107 #define ZSHARD_PRI 5 108 #define ZS_IVECT 64 109 110 #define ZS_DELAY() /* delay(2) */ 111 112 /* The layout of this is hardware-dependent (padding, order). */ 113 struct zschan { 114 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 115 volatile u_char zc_data; /* data */ 116 }; 117 struct zsdevice { 118 /* Yes, they are backwards. */ 119 struct zschan zs_chan_b; 120 struct zschan zs_chan_a; 121 }; 122 123 static struct zsdevice *zsaddr[NZS]; 124 static u_char zs_sir; 125 126 /* Flags from cninit() */ 127 static int zs_hwflags[NZS][2]; 128 129 /* Default speed for all channels */ 130 static int zs_defspeed = 9600; 131 132 static u_char zs_init_reg[16] = { 133 0, /* 0: CMD (reset, etc.) */ 134 0, /* 1: No interrupts yet. */ 135 ZS_IVECT, /* IVECT */ 136 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 137 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 138 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 139 0, /* 6: TXSYNC/SYNCLO */ 140 0, /* 7: RXSYNC/SYNCHI */ 141 0, /* 8: alias for data port */ 142 ZSWR9_MASTER_IE, 143 0, /*10: Misc. TX/RX control bits */ 144 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 145 ((PCLK0/32)/9600)-2, /*12: BAUDLO (default=9600) */ 146 0, /*13: BAUDHI (default=9600) */ 147 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 148 ZSWR15_BREAK_IE, 149 }; 150 151 struct zschan * 152 zs_get_chan_addr(zs_unit, channel) 153 int zs_unit, channel; 154 { 155 struct zsdevice *addr; 156 struct zschan *zc; 157 158 if (zs_unit >= NZS) 159 return NULL; 160 addr = zsaddr[zs_unit]; 161 if (addr == NULL) 162 return NULL; 163 if (channel == 0) { 164 zc = &addr->zs_chan_a; 165 } else { 166 zc = &addr->zs_chan_b; 167 } 168 return (zc); 169 } 170 171 172 /**************************************************************** 173 * Autoconfig 174 ****************************************************************/ 175 176 /* Definition of the driver for autoconfig. */ 177 static int zs_match __P((struct device *, struct cfdata *, void *)); 178 static void zs_attach __P((struct device *, struct device *, void *)); 179 static int zs_print __P((void *, const char *name)); 180 181 struct cfattach zsc_ca = { 182 sizeof(struct zsc_softc), zs_match, zs_attach 183 }; 184 185 extern struct cfdriver zsc_cd; 186 187 static int zshard __P((void *)); 188 int zssoft __P((void *)); 189 static int zs_get_speed __P((struct zs_chanstate *)); 190 191 /* 192 * Is the zs chip present? 193 */ 194 static int 195 zs_match(parent, cf, aux) 196 struct device *parent; 197 struct cfdata *cf; 198 void *aux; 199 { 200 struct hb_attach_args *ha = aux; 201 u_int addr; 202 203 if (strcmp(ha->ha_name, "zsc")) 204 return 0; 205 206 /* XXX no default address */ 207 if (ha->ha_address == -1) 208 return 0; 209 210 addr = IIOV(ha->ha_address); 211 /* This returns -1 on a fault (bus error). */ 212 if (badaddr((void *)addr, 1)) 213 return 0; 214 215 return 1; 216 } 217 218 /* 219 * Attach a found zs. 220 * 221 * Match slave number to zs unit number, so that misconfiguration will 222 * not set up the keyboard as ttya, etc. 223 */ 224 static void 225 zs_attach(parent, self, aux) 226 struct device *parent; 227 struct device *self; 228 void *aux; 229 { 230 struct zsc_softc *zsc = (void *) self; 231 struct cfdata *cf = self->dv_cfdata; 232 struct hb_attach_args *ha = aux; 233 struct zsc_attach_args zsc_args; 234 volatile struct zschan *zc; 235 struct zs_chanstate *cs; 236 int s, zs_unit, channel, clk; 237 238 zs_unit = zsc->zsc_dev.dv_unit; 239 zsaddr[zs_unit] = (void *)IIOV(ha->ha_address); 240 241 clk = cf->cf_flags; 242 if (clk < 0 || clk >= NPCLK) 243 clk = 0; 244 245 printf("\n"); 246 247 /* 248 * Initialize software state for each channel. 249 */ 250 for (channel = 0; channel < 2; channel++) { 251 zsc_args.channel = channel; 252 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 253 cs = &zsc->zsc_cs_store[channel]; 254 zsc->zsc_cs[channel] = cs; 255 256 cs->cs_channel = channel; 257 cs->cs_private = NULL; 258 cs->cs_ops = &zsops_null; 259 cs->cs_brg_clk = pclk[clk] / 16; 260 261 zc = zs_get_chan_addr(zs_unit, channel); 262 cs->cs_reg_csr = &zc->zc_csr; 263 cs->cs_reg_data = &zc->zc_data; 264 265 if (ha->ha_vect != -1) 266 zs_init_reg[2] = ha->ha_vect; 267 bcopy(zs_init_reg, cs->cs_creg, 16); 268 bcopy(zs_init_reg, cs->cs_preg, 16); 269 270 /* XXX: Get these from the EEPROM instead? */ 271 /* XXX: See the mvme167 code. Better. */ 272 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 273 cs->cs_defspeed = zs_get_speed(cs); 274 else 275 cs->cs_defspeed = zs_defspeed; 276 cs->cs_defcflag = zs_def_cflag; 277 278 /* Make these correspond to cs_defcflag (-crtscts) */ 279 cs->cs_rr0_dcd = ZSRR0_DCD; 280 cs->cs_rr0_cts = 0; 281 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 282 cs->cs_wr5_rts = 0; 283 284 /* 285 * Clear the master interrupt enable. 286 * The INTENA is common to both channels, 287 * so just do it on the A channel. 288 */ 289 if (channel == 0) { 290 s = splhigh(); 291 zs_write_reg(cs, 9, 0); 292 splx(s); 293 } 294 295 /* 296 * Look for a child driver for this channel. 297 * The child attach will setup the hardware. 298 */ 299 if (!config_found(self, (void *)&zsc_args, zs_print)) { 300 /* No sub-driver. Just reset it. */ 301 u_char reset = (channel == 0) ? 302 ZSWR9_A_RESET : ZSWR9_B_RESET; 303 s = splhigh(); 304 zs_write_reg(cs, 9, reset); 305 splx(s); 306 } 307 } 308 309 /* 310 * Now safe to install interrupt handlers. 311 */ 312 hb_intr_establish(zs_init_reg[2], zshard, ZSHARD_PRI, zsc); 313 314 /* 315 * Set the master interrupt enable and interrupt vector. 316 * (common to both channels, do it on A) 317 */ 318 cs = zsc->zsc_cs[0]; 319 s = splhigh(); 320 /* interrupt vector */ 321 zs_write_reg(cs, 2, zs_init_reg[2]); 322 /* master interrupt control (enable) */ 323 zs_write_reg(cs, 9, zs_init_reg[9]); 324 splx(s); 325 326 if (zs_sir == 0) 327 zs_sir = allocate_sir((void (*) __P((void *)))zssoft, zsc); 328 } 329 330 static int 331 zs_print(aux, name) 332 void *aux; 333 const char *name; 334 { 335 struct zsc_attach_args *args = aux; 336 337 if (name != NULL) 338 printf("%s: ", name); 339 340 if (args->channel != -1) 341 printf(" channel %d", args->channel); 342 343 return UNCONF; 344 } 345 346 /* 347 * For news68k-port, we don't use autovectored interrupt. 348 * We do not need to look at all of the zs chips. 349 */ 350 static int 351 zshard(arg) 352 void *arg; 353 { 354 struct zsc_softc *zsc = arg; 355 int rval; 356 357 rval = zsc_intr_hard(zsc); 358 359 /* We are at splzs here, so no need to lock. */ 360 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) { 361 setsoftint(zs_sir); 362 } 363 364 return (rval); 365 } 366 367 /* 368 * Shared among the all chips. We have to look at all of them. 369 */ 370 int 371 zssoft(arg) 372 void *arg; 373 { 374 struct zsc_softc *zsc; 375 int s, unit; 376 377 /* Make sure we call the tty layer at spltty. */ 378 s = spltty(); 379 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 380 zsc = zsc_cd.cd_devs[unit]; 381 if (zsc == NULL) 382 continue; 383 (void) zsc_intr_soft(zsc); 384 } 385 splx(s); 386 387 return 1; 388 } 389 390 /* 391 * Compute the current baud rate given a ZS channel. 392 */ 393 static int 394 zs_get_speed(cs) 395 struct zs_chanstate *cs; 396 { 397 int tconst; 398 399 tconst = zs_read_reg(cs, 12); 400 tconst |= zs_read_reg(cs, 13) << 8; 401 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 402 } 403 404 /* 405 * MD functions for setting the baud rate and control modes. 406 */ 407 int 408 zs_set_speed(cs, bps) 409 struct zs_chanstate *cs; 410 int bps; /* bits per second */ 411 { 412 int tconst, real_bps; 413 414 if (bps == 0) 415 return (0); 416 417 #ifdef DIAGNOSTIC 418 if (cs->cs_brg_clk == 0) 419 panic("zs_set_speed"); 420 #endif 421 422 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 423 if (tconst < 0) 424 return (EINVAL); 425 426 /* Convert back to make sure we can do it. */ 427 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 428 429 /* XXX - Allow some tolerance here? */ 430 if (real_bps != bps) 431 return (EINVAL); 432 433 cs->cs_preg[12] = tconst; 434 cs->cs_preg[13] = tconst >> 8; 435 436 /* Caller will stuff the pending registers. */ 437 return (0); 438 } 439 440 int 441 zs_set_modes(cs, cflag) 442 struct zs_chanstate *cs; 443 int cflag; /* bits per second */ 444 { 445 int s; 446 447 /* 448 * Output hardware flow control on the chip is horrendous: 449 * if carrier detect drops, the receiver is disabled, and if 450 * CTS drops, the transmitter is stoped IN MID CHARACTER! 451 * Therefore, NEVER set the HFC bit, and instead use the 452 * status interrupt to detect CTS changes. 453 */ 454 s = splzs(); 455 cs->cs_rr0_pps = 0; 456 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 457 cs->cs_rr0_dcd = 0; 458 if ((cflag & MDMBUF) == 0) 459 cs->cs_rr0_pps = ZSRR0_DCD; 460 } else 461 cs->cs_rr0_dcd = ZSRR0_DCD; 462 if ((cflag & CRTSCTS) != 0) { 463 cs->cs_wr5_dtr = ZSWR5_DTR; 464 cs->cs_wr5_rts = ZSWR5_RTS; 465 cs->cs_rr0_cts = ZSRR0_CTS; 466 } else if ((cflag & MDMBUF) != 0) { 467 cs->cs_wr5_dtr = 0; 468 cs->cs_wr5_rts = ZSWR5_DTR; 469 cs->cs_rr0_cts = ZSRR0_DCD; 470 } else { 471 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 472 cs->cs_wr5_rts = 0; 473 cs->cs_rr0_cts = 0; 474 } 475 splx(s); 476 477 /* Caller will stuff the pending registers. */ 478 return (0); 479 } 480 481 482 /* 483 * Read or write the chip with suitable delays. 484 */ 485 486 u_char 487 zs_read_reg(cs, reg) 488 struct zs_chanstate *cs; 489 u_char reg; 490 { 491 u_char val; 492 493 *cs->cs_reg_csr = reg; 494 ZS_DELAY(); 495 val = *cs->cs_reg_csr; 496 ZS_DELAY(); 497 return val; 498 } 499 500 void 501 zs_write_reg(cs, reg, val) 502 struct zs_chanstate *cs; 503 u_char reg, val; 504 { 505 *cs->cs_reg_csr = reg; 506 ZS_DELAY(); 507 *cs->cs_reg_csr = val; 508 ZS_DELAY(); 509 } 510 511 u_char 512 zs_read_csr(cs) 513 struct zs_chanstate *cs; 514 { 515 u_char val; 516 517 val = *cs->cs_reg_csr; 518 ZS_DELAY(); 519 return val; 520 } 521 522 void 523 zs_write_csr(cs, val) 524 struct zs_chanstate *cs; 525 u_char val; 526 { 527 *cs->cs_reg_csr = val; 528 ZS_DELAY(); 529 } 530 531 u_char 532 zs_read_data(cs) 533 struct zs_chanstate *cs; 534 { 535 u_char val; 536 537 val = *cs->cs_reg_data; 538 ZS_DELAY(); 539 return val; 540 } 541 542 void 543 zs_write_data(cs, val) 544 struct zs_chanstate *cs; 545 u_char val; 546 { 547 *cs->cs_reg_data = val; 548 ZS_DELAY(); 549 } 550 551 void 552 zs_abort(cs) 553 struct zs_chanstate *cs; 554 { 555 #ifdef DDB 556 Debugger(); 557 #endif 558 } 559 560 /* 561 * Polled input char. 562 */ 563 int 564 zs_getc(arg) 565 void *arg; 566 { 567 volatile struct zschan *zc = arg; 568 int s, c, rr0; 569 570 s = splhigh(); 571 /* Wait for a character to arrive. */ 572 do { 573 rr0 = zc->zc_csr; 574 ZS_DELAY(); 575 } while ((rr0 & ZSRR0_RX_READY) == 0); 576 577 c = zc->zc_data; 578 ZS_DELAY(); 579 splx(s); 580 581 return c; 582 } 583 584 /* 585 * Polled output char. 586 */ 587 void 588 zs_putc(arg, c) 589 void *arg; 590 int c; 591 { 592 volatile struct zschan *zc = arg; 593 int s, rr0; 594 595 s = splhigh(); 596 /* Wait for transmitter to become ready. */ 597 do { 598 rr0 = zc->zc_csr; 599 ZS_DELAY(); 600 } while ((rr0 & ZSRR0_TX_READY) == 0); 601 602 zc->zc_data = c; 603 ZS_DELAY(); 604 splx(s); 605 } 606 607 /*****************************************************************/ 608 609 static void zscnprobe __P((struct consdev *)); 610 static void zscninit __P((struct consdev *)); 611 static int zscngetc __P((dev_t)); 612 static void zscnputc __P((dev_t, int)); 613 614 static void *zs_conschan; 615 616 struct consdev consdev_zs = { 617 zscnprobe, 618 zscninit, 619 zscngetc, 620 zscnputc, 621 nullcnpollc, 622 NULL, 623 }; 624 625 static void 626 zscnprobe(cn) 627 struct consdev *cn; 628 { 629 } 630 631 static void 632 zscninit(cn) 633 struct consdev *cn; 634 { 635 extern volatile u_char *sccport0a; 636 637 cn->cn_dev = makedev(zs_major, 0); 638 cn->cn_pri = CN_REMOTE; 639 zs_hwflags[0][0] = ZS_HWFLAG_CONSOLE; 640 zs_conschan = (void *)sccport0a; /* XXX */ 641 } 642 643 static int 644 zscngetc(dev) 645 dev_t dev; 646 { 647 return zs_getc(zs_conschan); 648 } 649 650 static void 651 zscnputc(dev, c) 652 dev_t dev; 653 int c; 654 { 655 zs_putc(zs_conschan, c); 656 } 657
Indexes created Tue Sep 30 11:09:46 GMT 2025