zs.c revision 1.5
1 /* $NetBSD: zs.c,v 1.5 2000/10/14 16:45:49 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 /* 47 * news68k/dev/zs.c - based on {newsmips,x68k,mvme68k}/dev/zs.c 48 */ 49 50 #include "opt_ddb.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/conf.h> 55 #include <sys/device.h> 56 #include <sys/tty.h> 57 58 #include <machine/cpu.h> 59 #include <machine/z8530var.h> 60 61 #include <dev/cons.h> 62 #include <dev/ic/z8530reg.h> 63 64 #include <news68k/dev/hbvar.h> 65 66 int zs_getc __P((void *)); 67 void zs_putc __P((void *, int)); 68 69 extern void Debugger __P((void)); 70 71 /* 72 * Some warts needed by z8530tty.c - 73 * The default parity REALLY needs to be the same as the PROM uses, 74 * or you can not see messages done with printf during boot-up... 75 */ 76 int zs_def_cflag = (CREAD | CS8 | HUPCL); 77 int zs_major = 1; 78 79 /* 80 * The news68k machines use three different clocks for the ZS chips. 81 */ 82 #define NPCLK 3 83 #define PCLK0 (9600 * 416) /* news1700: 3.9936MHz */ 84 #define PCLK1 (9600 * 512) /* news1200: 4.9152MHz */ 85 #define PCLK2 (9600 * 384) /* external: 3.6864MHz */ 86 87 static const u_int pclk[NPCLK] = { 88 PCLK0, 89 PCLK1, 90 PCLK2, 91 }; 92 93 /* 94 * Define interrupt levels. 95 */ 96 #define ZSHARD_PRI 5 97 #define ZS_IVECT 64 98 99 #define ZS_DELAY() /* delay(2) */ 100 101 /* The layout of this is hardware-dependent (padding, order). */ 102 struct zschan { 103 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 104 volatile u_char zc_data; /* data */ 105 }; 106 struct zsdevice { 107 /* Yes, they are backwards. */ 108 struct zschan zs_chan_b; 109 struct zschan zs_chan_a; 110 }; 111 112 static u_char zs_sir; 113 114 /* Default speed for all channels */ 115 static int zs_defspeed = 9600; 116 117 /* console status from cninit */ 118 static struct zs_chanstate zs_conschan_store; 119 static struct zs_chanstate *zs_conschan; 120 static struct zschan *zc_cons; 121 122 static u_char zs_init_reg[16] = { 123 0, /* 0: CMD (reset, etc.) */ 124 0, /* 1: No interrupts yet. */ 125 ZS_IVECT, /* IVECT */ 126 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 127 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 128 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 129 0, /* 6: TXSYNC/SYNCLO */ 130 0, /* 7: RXSYNC/SYNCHI */ 131 0, /* 8: alias for data port */ 132 ZSWR9_MASTER_IE, 133 0, /*10: Misc. TX/RX control bits */ 134 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 135 BPS_TO_TCONST((PCLK0/16), 9600), /*12: BAUDLO (default=9600) */ 136 0, /*13: BAUDHI (default=9600) */ 137 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 138 ZSWR15_BREAK_IE, 139 }; 140 141 142 /**************************************************************** 143 * Autoconfig 144 ****************************************************************/ 145 146 /* Definition of the driver for autoconfig. */ 147 static int zs_match __P((struct device *, struct cfdata *, void *)); 148 static void zs_attach __P((struct device *, struct device *, void *)); 149 static int zs_print __P((void *, const char *name)); 150 151 struct cfattach zsc_ca = { 152 sizeof(struct zsc_softc), zs_match, zs_attach 153 }; 154 155 extern struct cfdriver zsc_cd; 156 157 static int zshard __P((void *)); 158 void zssoft __P((void *)); 159 #if 0 160 static int zs_get_speed __P((struct zs_chanstate *)); 161 #endif 162 163 /* 164 * Is the zs chip present? 165 */ 166 static int 167 zs_match(parent, cf, aux) 168 struct device *parent; 169 struct cfdata *cf; 170 void *aux; 171 { 172 struct hb_attach_args *ha = aux; 173 u_int addr; 174 175 if (strcmp(ha->ha_name, "zsc")) 176 return 0; 177 178 /* XXX no default address */ 179 if (ha->ha_address == -1) 180 return 0; 181 182 addr = IIOV(ha->ha_address); 183 /* This returns -1 on a fault (bus error). */ 184 if (badaddr((void *)addr, 1)) 185 return 0; 186 187 return 1; 188 } 189 190 /* 191 * Attach a found zs. 192 */ 193 static void 194 zs_attach(parent, self, aux) 195 struct device *parent; 196 struct device *self; 197 void *aux; 198 { 199 struct zsc_softc *zsc = (void *) self; 200 struct cfdata *cf = self->dv_cfdata; 201 struct hb_attach_args *ha = aux; 202 struct zsc_attach_args zsc_args; 203 struct zsdevice *zs; 204 struct zschan *zc; 205 struct zs_chanstate *cs; 206 int s, channel, clk; 207 208 zs = (void *)IIOV(ha->ha_address); 209 210 clk = cf->cf_flags; 211 if (clk < 0 || clk >= NPCLK) 212 clk = 0; 213 214 printf("\n"); 215 216 /* 217 * Initialize software state for each channel. 218 */ 219 for (channel = 0; channel < 2; channel++) { 220 zsc_args.channel = channel; 221 cs = &zsc->zsc_cs_store[channel]; 222 zsc->zsc_cs[channel] = cs; 223 zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b; 224 225 if (ha->ha_vect != -1) 226 zs_init_reg[2] = ha->ha_vect; 227 228 if (zc == zc_cons) { 229 bcopy(zs_conschan, cs, sizeof(struct zs_chanstate)); 230 zs_conschan = cs; 231 zsc_args.hwflags = ZS_HWFLAG_CONSOLE; 232 } else { 233 cs->cs_reg_csr = &zc->zc_csr; 234 cs->cs_reg_data = &zc->zc_data; 235 bcopy(zs_init_reg, cs->cs_creg, 16); 236 bcopy(zs_init_reg, cs->cs_preg, 16); 237 cs->cs_defspeed = zs_defspeed; 238 zsc_args.hwflags = 0; 239 } 240 241 cs->cs_defcflag = zs_def_cflag; 242 243 cs->cs_channel = channel; 244 cs->cs_private = NULL; 245 cs->cs_ops = &zsops_null; 246 cs->cs_brg_clk = pclk[clk] / 16; 247 248 /* Make these correspond to cs_defcflag (-crtscts) */ 249 cs->cs_rr0_dcd = ZSRR0_DCD; 250 cs->cs_rr0_cts = 0; 251 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 252 cs->cs_wr5_rts = 0; 253 254 /* 255 * Clear the master interrupt enable. 256 * The INTENA is common to both channels, 257 * so just do it on the A channel. 258 */ 259 if (channel == 0) { 260 s = splhigh(); 261 zs_write_reg(cs, 9, 0); 262 splx(s); 263 } 264 265 /* 266 * Look for a child driver for this channel. 267 * The child attach will setup the hardware. 268 */ 269 if (!config_found(self, (void *)&zsc_args, zs_print)) { 270 /* No sub-driver. Just reset it. */ 271 u_char reset = (channel == 0) ? 272 ZSWR9_A_RESET : ZSWR9_B_RESET; 273 s = splhigh(); 274 zs_write_reg(cs, 9, reset); 275 splx(s); 276 } 277 } 278 279 /* 280 * Now safe to install interrupt handlers. 281 */ 282 hb_intr_establish(zs_init_reg[2], zshard, ZSHARD_PRI, zsc); 283 284 /* 285 * Set the master interrupt enable and interrupt vector. 286 * (common to both channels, do it on A) 287 */ 288 cs = zsc->zsc_cs[0]; 289 s = splhigh(); 290 /* interrupt vector */ 291 zs_write_reg(cs, 2, zs_init_reg[2]); 292 /* master interrupt control (enable) */ 293 zs_write_reg(cs, 9, zs_init_reg[9]); 294 splx(s); 295 296 if (zs_sir == 0) 297 zs_sir = allocate_sir(zssoft, zsc); 298 } 299 300 static int 301 zs_print(aux, name) 302 void *aux; 303 const char *name; 304 { 305 struct zsc_attach_args *args = aux; 306 307 if (name != NULL) 308 printf("%s: ", name); 309 310 if (args->channel != -1) 311 printf(" channel %d", args->channel); 312 313 return UNCONF; 314 } 315 316 /* 317 * For news68k-port, we don't use autovectored interrupt. 318 * We do not need to look at all of the zs chips. 319 */ 320 static int 321 zshard(arg) 322 void *arg; 323 { 324 struct zsc_softc *zsc = arg; 325 int rval; 326 327 rval = zsc_intr_hard(zsc); 328 329 /* We are at splzs here, so no need to lock. */ 330 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) { 331 setsoftint(zs_sir); 332 } 333 334 return (rval); 335 } 336 337 /* 338 * Shared among the all chips. We have to look at all of them. 339 */ 340 void 341 zssoft(arg) 342 void *arg; 343 { 344 struct zsc_softc *zsc; 345 int s, unit; 346 347 /* Make sure we call the tty layer at spltty. */ 348 s = spltty(); 349 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 350 zsc = zsc_cd.cd_devs[unit]; 351 if (zsc == NULL) 352 continue; 353 (void) zsc_intr_soft(zsc); 354 } 355 splx(s); 356 } 357 358 /* 359 * Compute the current baud rate given a ZS channel. 360 */ 361 #if 0 362 static int 363 zs_get_speed(cs) 364 struct zs_chanstate *cs; 365 { 366 int tconst; 367 368 tconst = zs_read_reg(cs, 12); 369 tconst |= zs_read_reg(cs, 13) << 8; 370 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 371 } 372 #endif 373 374 /* 375 * MD functions for setting the baud rate and control modes. 376 */ 377 int 378 zs_set_speed(cs, bps) 379 struct zs_chanstate *cs; 380 int bps; /* bits per second */ 381 { 382 int tconst, real_bps; 383 384 if (bps == 0) 385 return (0); 386 387 #ifdef DIAGNOSTIC 388 if (cs->cs_brg_clk == 0) 389 panic("zs_set_speed"); 390 #endif 391 392 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 393 if (tconst < 0) 394 return (EINVAL); 395 396 /* Convert back to make sure we can do it. */ 397 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 398 399 /* XXX - Allow some tolerance here? */ 400 if (real_bps != bps) 401 return (EINVAL); 402 403 cs->cs_preg[12] = tconst; 404 cs->cs_preg[13] = tconst >> 8; 405 406 /* Caller will stuff the pending registers. */ 407 return (0); 408 } 409 410 int 411 zs_set_modes(cs, cflag) 412 struct zs_chanstate *cs; 413 int cflag; /* bits per second */ 414 { 415 int s; 416 417 /* 418 * Output hardware flow control on the chip is horrendous: 419 * if carrier detect drops, the receiver is disabled, and if 420 * CTS drops, the transmitter is stoped IN MID CHARACTER! 421 * Therefore, NEVER set the HFC bit, and instead use the 422 * status interrupt to detect CTS changes. 423 */ 424 s = splzs(); 425 cs->cs_rr0_pps = 0; 426 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 427 cs->cs_rr0_dcd = 0; 428 if ((cflag & MDMBUF) == 0) 429 cs->cs_rr0_pps = ZSRR0_DCD; 430 } else 431 cs->cs_rr0_dcd = ZSRR0_DCD; 432 if ((cflag & CRTSCTS) != 0) { 433 cs->cs_wr5_dtr = ZSWR5_DTR; 434 cs->cs_wr5_rts = ZSWR5_RTS; 435 cs->cs_rr0_cts = ZSRR0_CTS; 436 } else if ((cflag & MDMBUF) != 0) { 437 cs->cs_wr5_dtr = 0; 438 cs->cs_wr5_rts = ZSWR5_DTR; 439 cs->cs_rr0_cts = ZSRR0_DCD; 440 } else { 441 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 442 cs->cs_wr5_rts = 0; 443 cs->cs_rr0_cts = 0; 444 } 445 splx(s); 446 447 /* Caller will stuff the pending registers. */ 448 return (0); 449 } 450 451 452 /* 453 * Read or write the chip with suitable delays. 454 */ 455 456 u_char 457 zs_read_reg(cs, reg) 458 struct zs_chanstate *cs; 459 u_char reg; 460 { 461 u_char val; 462 463 *cs->cs_reg_csr = reg; 464 ZS_DELAY(); 465 val = *cs->cs_reg_csr; 466 ZS_DELAY(); 467 return val; 468 } 469 470 void 471 zs_write_reg(cs, reg, val) 472 struct zs_chanstate *cs; 473 u_char reg, val; 474 { 475 *cs->cs_reg_csr = reg; 476 ZS_DELAY(); 477 *cs->cs_reg_csr = val; 478 ZS_DELAY(); 479 } 480 481 u_char 482 zs_read_csr(cs) 483 struct zs_chanstate *cs; 484 { 485 u_char val; 486 487 val = *cs->cs_reg_csr; 488 ZS_DELAY(); 489 return val; 490 } 491 492 void 493 zs_write_csr(cs, val) 494 struct zs_chanstate *cs; 495 u_char val; 496 { 497 *cs->cs_reg_csr = val; 498 ZS_DELAY(); 499 } 500 501 u_char 502 zs_read_data(cs) 503 struct zs_chanstate *cs; 504 { 505 u_char val; 506 507 val = *cs->cs_reg_data; 508 ZS_DELAY(); 509 return val; 510 } 511 512 void 513 zs_write_data(cs, val) 514 struct zs_chanstate *cs; 515 u_char val; 516 { 517 *cs->cs_reg_data = val; 518 ZS_DELAY(); 519 } 520 521 void 522 zs_abort(cs) 523 struct zs_chanstate *cs; 524 { 525 #ifdef DDB 526 Debugger(); 527 #endif 528 } 529 530 /* 531 * Polled input char. 532 */ 533 int 534 zs_getc(arg) 535 void *arg; 536 { 537 struct zs_chanstate *cs = arg; 538 int s, c, rr0; 539 540 s = splhigh(); 541 /* Wait for a character to arrive. */ 542 do { 543 rr0 = *cs->cs_reg_csr; 544 ZS_DELAY(); 545 } while ((rr0 & ZSRR0_RX_READY) == 0); 546 547 c = *cs->cs_reg_data; 548 ZS_DELAY(); 549 splx(s); 550 551 return c; 552 } 553 554 /* 555 * Polled output char. 556 */ 557 void 558 zs_putc(arg, c) 559 void *arg; 560 int c; 561 { 562 struct zs_chanstate *cs = arg; 563 int s, rr0; 564 565 s = splhigh(); 566 /* Wait for transmitter to become ready. */ 567 do { 568 rr0 = *cs->cs_reg_csr; 569 ZS_DELAY(); 570 } while ((rr0 & ZSRR0_TX_READY) == 0); 571 572 *cs->cs_reg_data = c; 573 ZS_DELAY(); 574 splx(s); 575 } 576 577 /*****************************************************************/ 578 579 static void zscnprobe __P((struct consdev *)); 580 static void zscninit __P((struct consdev *)); 581 static int zscngetc __P((dev_t)); 582 static void zscnputc __P((dev_t, int)); 583 584 struct consdev consdev_zs = { 585 zscnprobe, 586 zscninit, 587 zscngetc, 588 zscnputc, 589 nullcnpollc, 590 NULL, 591 }; 592 593 static void 594 zscnprobe(cn) 595 struct consdev *cn; 596 { 597 extern int tty00_is_console; 598 599 cn->cn_dev = makedev(zs_major, 0); 600 if (tty00_is_console) 601 cn->cn_pri = CN_REMOTE; 602 else 603 cn->cn_pri = CN_NORMAL; 604 } 605 606 static void 607 zscninit(cn) 608 struct consdev *cn; 609 { 610 struct zs_chanstate *cs; 611 612 extern volatile u_char *sccport0a; 613 614 zc_cons = (struct zschan *)sccport0a; /* XXX */ 615 616 zs_conschan = cs = &zs_conschan_store; 617 618 /* Setup temporary chanstate. */ 619 cs->cs_reg_csr = &zc_cons->zc_csr; 620 cs->cs_reg_data = &zc_cons->zc_data; 621 622 /* Initialize the pending registers. */ 623 bcopy(zs_init_reg, cs->cs_preg, 16); 624 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 625 626 cs->cs_preg[12] = BPS_TO_TCONST(pclk[systype] / 16, 9600); /* XXX */ 627 cs->cs_preg[13] = 0; 628 cs->cs_defspeed = 9600; 629 630 /* Clear the master interrupt enable. */ 631 zs_write_reg(cs, 9, 0); 632 633 /* Reset the whole SCC chip. */ 634 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 635 636 /* Copy "pending" to "current" and H/W */ 637 zs_loadchannelregs(cs); 638 } 639 640 static int 641 zscngetc(dev) 642 dev_t dev; 643 { 644 return zs_getc((void *)zs_conschan); 645 } 646 647 static void 648 zscnputc(dev, c) 649 dev_t dev; 650 int c; 651 { 652 zs_putc((void *)zs_conschan, c); 653 } 654
Indexes created Sun Sep 28 16:09:52 GMT 2025