dmac3.c revision 1.5
1 /* $NetBSD: dmac3.c,v 1.5 2003/04/02 04:17:50 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/device.h> 31 #include <sys/kernel.h> 32 #include <sys/systm.h> 33 34 #include <uvm/uvm_extern.h> 35 36 #include <machine/locore.h> 37 38 #include <newsmips/apbus/apbusvar.h> 39 #include <newsmips/apbus/dmac3reg.h> 40 41 #include <mips/cache.h> 42 43 #define DMA_BURST 44 #define DMA_APAD_OFF 45 46 #ifdef DMA_APAD_OFF 47 # define APAD_MODE 0 48 #else 49 # define APAD_MODE DMAC3_CSR_APAD 50 #endif 51 52 #ifdef DMA_BURST 53 # define BURST_MODE (DMAC3_CSR_DBURST | DMAC3_CSR_MBURST) 54 #else 55 # define BURST_MODE 0 56 #endif 57 58 struct dmac3_softc { 59 struct device sc_dev; 60 struct dmac3reg *sc_reg; 61 vaddr_t sc_dmaaddr; 62 int *sc_dmamap; 63 int sc_conf; 64 int sc_ctlnum; 65 }; 66 67 int dmac3_match __P((struct device *, struct cfdata *, void *)); 68 void dmac3_attach __P((struct device *, struct device *, void *)); 69 70 paddr_t kvtophys __P((vaddr_t)); 71 72 CFATTACH_DECL(dmac, sizeof(struct dmac3_softc), 73 dmac3_match, dmac3_attach, NULL, NULL); 74 75 int 76 dmac3_match(parent, cf, aux) 77 struct device *parent; 78 struct cfdata *cf; 79 void *aux; 80 { 81 struct apbus_attach_args *apa = aux; 82 83 if (strcmp(apa->apa_name, "dmac3") == 0) 84 return 1; 85 86 return 0; 87 } 88 89 void 90 dmac3_attach(parent, self, aux) 91 struct device *parent, *self; 92 void *aux; 93 { 94 struct dmac3_softc *sc = (void *)self; 95 struct apbus_attach_args *apa = aux; 96 struct dmac3reg *reg; 97 98 static paddr_t dmamap = DMAC3_PAGEMAP; 99 static vaddr_t dmaaddr = 0; 100 101 reg = (void *)apa->apa_hwbase; 102 sc->sc_reg = reg; 103 sc->sc_ctlnum = apa->apa_ctlnum; 104 sc->sc_dmamap = (int *)dmamap; 105 sc->sc_dmaaddr = dmaaddr; 106 dmamap += 0x1000; 107 dmaaddr += 0x200000; 108 109 sc->sc_conf = DMAC3_CONF_PCEN | DMAC3_CONF_DCEN | DMAC3_CONF_FASTACCESS; 110 111 dmac3_reset(sc); 112 113 printf(" slot%d addr 0x%lx", apa->apa_slotno, apa->apa_hwbase); 114 printf(": ctlnum = %d, map = %p, va = %lx", 115 apa->apa_ctlnum, sc->sc_dmamap, sc->sc_dmaaddr); 116 printf("\n"); 117 } 118 119 void * 120 dmac3_link(ctlnum) 121 int ctlnum; 122 { 123 struct dmac3_softc *sc; 124 struct device *dv; 125 126 for (dv = alldevs.tqh_first; dv; dv = dv->dv_list.tqe_next) { 127 if (strncmp(dv->dv_xname, "dmac", 4) == 0) { 128 sc = (void *)dv; 129 if (sc->sc_ctlnum == ctlnum) 130 return sc; 131 } 132 } 133 return NULL; 134 } 135 136 void 137 dmac3_reset(sc) 138 struct dmac3_softc *sc; 139 { 140 struct dmac3reg *reg = sc->sc_reg; 141 142 reg->csr = DMAC3_CSR_RESET; 143 reg->csr = 0; 144 reg->intr = DMAC3_INTR_EOPIE | DMAC3_INTR_INTEN; 145 reg->conf = sc->sc_conf; 146 } 147 148 void 149 dmac3_start(sc, addr, len, direction) 150 struct dmac3_softc *sc; 151 vaddr_t addr; 152 int len, direction; 153 { 154 struct dmac3reg *reg = sc->sc_reg; 155 paddr_t pa; 156 vaddr_t start, end, v; 157 u_int *p; 158 159 if (reg->csr & DMAC3_CSR_ENABLE) 160 dmac3_reset(sc); 161 162 start = mips_trunc_page(addr); 163 end = mips_round_page(addr + len); 164 p = sc->sc_dmamap; 165 for (v = start; v < end; v += PAGE_SIZE) { 166 pa = kvtophys(v); 167 mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(pa), PAGE_SIZE); 168 *p++ = 0; 169 *p++ = (pa >> PGSHIFT) | 0xc0000000; 170 } 171 *p++ = 0; 172 *p++ = 0x003fffff; 173 174 addr &= PGOFSET; 175 addr += sc->sc_dmaaddr; 176 177 reg->len = len; 178 reg->addr = addr; 179 reg->intr = DMAC3_INTR_EOPIE | DMAC3_INTR_INTEN; 180 reg->csr = DMAC3_CSR_ENABLE | direction | BURST_MODE | APAD_MODE; 181 } 182 183 int 184 dmac3_intr(v) 185 void *v; 186 { 187 struct dmac3_softc *sc = v; 188 struct dmac3reg *reg = sc->sc_reg; 189 int intr, conf, rv = 1; 190 191 intr = reg->intr; 192 if ((intr & DMAC3_INTR_INT) == 0) 193 return 0; 194 195 /* clear interrupt */ 196 conf = reg->conf; 197 reg->conf = conf; 198 reg->intr = intr; 199 200 if (intr & DMAC3_INTR_PERR) { 201 printf("%s: intr = 0x%x\n", sc->sc_dev.dv_xname, intr); 202 rv = -1; 203 } 204 205 if (conf & (DMAC3_CONF_IPER | DMAC3_CONF_MPER | DMAC3_CONF_DERR)) { 206 printf("%s: conf = 0x%x\n", sc->sc_dev.dv_xname, conf); 207 if (conf & DMAC3_CONF_DERR) { 208 printf("DMA address = 0x%x\n", reg->addr); 209 printf("resetting DMA...\n"); 210 dmac3_reset(sc); 211 } 212 } 213 214 return rv; 215 } 216 217 void 218 dmac3_misc(sc, cmd) 219 struct dmac3_softc *sc; 220 int cmd; 221 { 222 struct dmac3reg *reg = sc->sc_reg; 223 int conf; 224 225 conf = DMAC3_CONF_PCEN | DMAC3_CONF_DCEN | cmd; 226 sc->sc_conf = conf; 227 reg->conf = conf; 228 } 229
Indexes created Mon Sep 29 21:09:56 GMT 2025