if_snvar.h revision 1.1
1 /* $NetBSD: if_snvar.h,v 1.1 1999/12/22 05:55:25 tsubai Exp $ */ 2 3 /* 4 * Copyright (c) 1991 Algorithmics Ltd (http://www.algor.co.uk) 5 * You may use, copy, and modify this program so long as you retain the 6 * copyright line. 7 */ 8 9 /* 10 * if_snvar.h -- National Semiconductor DP8393X (SONIC) NetBSD/newsmips vars 11 */ 12 13 /* 14 * Memory access macros. Since we handle SONIC in 16 bit mode (PB5X0) 15 * and 32 bit mode (everything else) using a single GENERIC kernel 16 * binary, all structures have to be accessed using macros which can 17 * adjust the offsets appropriately. 18 */ 19 #define SWO(m, a, o, x) (*(u_int32_t *)((u_int32_t *)(a) + (o)) = (x)) 20 #define SRO(m, a, o) (*(u_int32_t *)((u_int32_t *)(a) + (o)) & 0xffff) 21 22 /* 23 * Register access macros. We use bus_space_* to talk to the Sonic 24 * registers. A mapping table is used in case a particular configuration 25 * hooked the regs up at non-word offsets. 26 */ 27 #define NIC_GET(sc, reg) ((sc)->sc_regbase[(reg) * 4 + 3]) 28 #define NIC_PUT(sc, reg, val) ((sc)->sc_regbase[(reg) * 4 + 3] = val) 29 30 #define SONIC_GETDMA(p) ((u_int32_t)(p)) 31 32 #define SN_REGSIZE SN_NREGS*4 33 34 void mips3_wbflush __P((void)); 35 void apbus_wbflush __P((void)); 36 37 static __inline void 38 wbflush() 39 { 40 mips3_wbflush(); 41 apbus_wbflush(); 42 }; 43 44 /* 45 * buffer sizes in 32 bit mode 46 * 1 TXpkt is 4 hdr words + (3 * FRAGMAX) + 1 link word == 23 words == 92 bytes 47 * 48 * 1 RxPkt is 7 words == 28 bytes 49 * 1 Rda is 4 words == 16 bytes 50 * 51 * The CDA is 17 words == 68 bytes 52 * 53 * total space in page 0 = NTDA * 92 + NRRA * 16 + NRDA * 28 + 68 54 */ 55 56 #define NRBA 4 /* # receive buffers < NRRA */ 57 #define RBAMASK (NRBA-1) 58 #define NTDA 4 /* # transmit descriptors */ 59 #define NRRA 8 /* # receive resource descriptors */ 60 #define RRAMASK (NRRA-1) /* the reason why NRRA must be power of two */ 61 62 #define FCSSIZE 4 /* size of FCS appended to packets */ 63 64 /* 65 * maximum receive packet size plus 2 byte pad to make each 66 * one aligned. 4 byte slop (required for eobc) 67 */ 68 #define RBASIZE(sc) (sizeof(struct ether_header) + ETHERMTU + FCSSIZE + 6) 69 70 /* 71 * transmit buffer area 72 */ 73 #define TXBSIZE 1536 /* 6*2^8 -- the same size as the 8390 TXBUF */ 74 75 #define SN_NPAGES 2 + NRBA + (NTDA/2) 76 77 typedef struct mtd { 78 void *mtd_txp; 79 u_int32_t mtd_vtxp; 80 caddr_t mtd_buf; 81 u_int32_t mtd_vbuf; 82 struct mbuf *mtd_mbuf; 83 } mtd_t; 84 85 /* 86 * The sn_softc for NEWS5000 if_sn. 87 */ 88 struct sn_softc { 89 struct device sc_dev; 90 struct ethercom sc_ethercom; 91 #define sc_if sc_ethercom.ec_if /* network visible interface */ 92 93 caddr_t sc_hwbase; /* hardware base address */ 94 u_int16_t *sc_regbase; /* register base address */ 95 96 int bitmode; /* 32 bit mode == 1, 16 == 0 */ 97 98 u_int16_t snr_dcr; /* DCR for this instance */ 99 u_int16_t snr_dcr2; /* DCR2 for this instance */ 100 int slotno; /* Slot number */ 101 102 int sc_rramark; /* index into p_rra of wp */ 103 void *p_rra[NRRA]; /* RX resource descs */ 104 u_int32_t v_rra[NRRA]; /* DMA addresses of p_rra */ 105 u_int32_t v_rea; /* ptr to the end of the rra space */ 106 107 int sc_rxmark; /* current hw pos in rda ring */ 108 int sc_rdamark; /* current sw pos in rda ring */ 109 int sc_nrda; /* total number of RDAs */ 110 caddr_t p_rda; 111 u_int32_t v_rda; 112 113 caddr_t rbuf[NRBA]; 114 115 struct mtd mtda[NTDA]; 116 int mtd_hw; /* idx of first mtd given to hw */ 117 int mtd_prev; /* idx of last mtd given to hardware */ 118 int mtd_free; /* next free mtd to use */ 119 int mtd_tlinko; /* 120 * offset of tlink of last txp given 121 * to SONIC. Need to clear EOL on 122 * this word to add a desc. 123 */ 124 int mtd_pint; /* Counter to set TXP_PINT */ 125 126 void *p_cda; 127 u_int32_t v_cda; 128 129 unsigned char *space; 130 }; 131 132 /* 133 * Accessing SONIC data structures and registers as 32 bit values 134 * makes code endianess independent. The SONIC is however always in 135 * bigendian mode so it is necessary to ensure that data structures shared 136 * between the CPU and the SONIC are always in bigendian order. 137 */ 138 139 /* 140 * Receive Resource Descriptor 141 * This structure describes the buffers into which packets 142 * will be received. Note that more than one packet may be 143 * packed into a single buffer if constraints permit. 144 */ 145 #define RXRSRC_PTRLO 0 /* buffer address LO */ 146 #define RXRSRC_PTRHI 1 /* buffer address HI */ 147 #define RXRSRC_WCLO 2 /* buffer size (16bit words) LO */ 148 #define RXRSRC_WCHI 3 /* buffer size (16bit words) HI */ 149 150 #define RXRSRC_SIZE(sc) (4 * 4) 151 152 /* 153 * Receive Descriptor 154 * This structure holds information about packets received. 155 */ 156 #define RXPKT_STATUS 0 157 #define RXPKT_BYTEC 1 158 #define RXPKT_PTRLO 2 159 #define RXPKT_PTRHI 3 160 #define RXPKT_SEQNO 4 161 #define RXPKT_RLINK 5 162 #define RXPKT_INUSE 6 163 #define RXPKT_SIZE(sc) (7 * 4) 164 165 #define RBASEQ(x) (((x) >> 8) & 0xff) 166 #define PSNSEQ(x) ((x) & 0xff) 167 168 /* 169 * Transmit Descriptor 170 * This structure holds information about packets to be transmitted. 171 */ 172 #define FRAGMAX 8 /* maximum number of fragments in a packet */ 173 174 #define TXP_STATUS 0 /* + transmitted packet status */ 175 #define TXP_CONFIG 1 /* transmission configuration */ 176 #define TXP_PKTSIZE 2 /* entire packet size in bytes */ 177 #define TXP_FRAGCNT 3 /* # fragments in packet */ 178 179 #define TXP_FRAGOFF 4 /* offset to first fragment */ 180 #define TXP_FRAGSIZE 3 /* size of each fragment desc */ 181 #define TXP_FPTRLO 0 /* ptr to packet fragment LO */ 182 #define TXP_FPTRHI 1 /* ptr to packet fragment HI */ 183 #define TXP_FSIZE 2 /* fragment size */ 184 185 #define TXP_WORDS TXP_FRAGOFF + (FRAGMAX*TXP_FRAGSIZE) + 1 /* 1 for tlink */ 186 #define TXP_SIZE(sc) (TXP_WORDS*4) 187 188 #define EOL 0x0001 /* end of list marker for link fields */ 189 190 /* 191 * CDA, the CAM descriptor area. The SONIC has a 16 entry CAM to 192 * match incoming addresses against. It is programmed via DMA 193 * from a memory region. 194 */ 195 #define MAXCAM 16 /* number of user entries in CAM */ 196 #define CDA_CAMDESC 4 /* # words i na descriptor */ 197 #define CDA_CAMEP 0 /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */ 198 #define CDA_CAMAP0 1 /* CAM Address Port 1 xx-xx-YY-YY-xx-xx */ 199 #define CDA_CAMAP1 2 /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */ 200 #define CDA_CAMAP2 3 201 #define CDA_ENABLE 64 /* mask enabling CAM entries */ 202 #define CDA_SIZE(sc) ((4*16 + 1) * ((sc->bitmode) ? 4 : 2)) 203 204 int snsetup __P((struct sn_softc *sc, u_int8_t *)); 205 void snintr __P((void *)); 206 void sn_md_init __P((struct sn_softc *)); 207
Indexes created Wed Oct 01 19:09:53 GMT 2025