spifi.c revision 1.1
1 /* $NetBSD: spifi.c,v 1.1 2000/10/30 10:07:35 tsubai Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/buf.h> 31 #include <sys/device.h> 32 #include <sys/errno.h> 33 #include <sys/kernel.h> 34 #include <sys/queue.h> 35 #include <sys/systm.h> 36 37 #include <uvm/uvm_extern.h> 38 39 #include <dev/scsipi/scsi_all.h> 40 #include <dev/scsipi/scsi_message.h> 41 #include <dev/scsipi/scsipi_all.h> 42 #include <dev/scsipi/scsiconf.h> 43 44 #include <newsmips/apbus/apbusvar.h> 45 #include <newsmips/apbus/spifireg.h> 46 #include <newsmips/apbus/dmac3reg.h> 47 48 #include <machine/adrsmap.h> 49 50 /* #define SPIFI_DEBUG */ 51 52 #ifdef SPIFI_DEBUG 53 # define DPRINTF printf 54 #else 55 # define DPRINTF while (0) printf 56 #endif 57 58 struct spifi_scb { 59 TAILQ_ENTRY(spifi_scb) chain; 60 int flags; 61 struct scsipi_xfer *xs; 62 struct scsi_generic cmd; 63 int cmdlen; 64 int resid; 65 vaddr_t daddr; 66 u_char target; 67 u_char lun; 68 u_char lun_targ; 69 u_char status; 70 }; 71 /* scb flags */ 72 #define SPIFI_READ 0x80 73 #define SPIFI_DMA 0x01 74 75 struct spifi_softc { 76 struct device sc_dev; 77 struct scsipi_link sc_link; 78 79 struct spifi_reg *sc_reg; 80 struct spifi_scb *sc_nexus; 81 void *sc_dma; /* attached DMA softc */ 82 int sc_id; /* my SCSI ID */ 83 int sc_msgout; 84 u_char sc_omsg[16]; 85 struct spifi_scb sc_scb[16]; 86 TAILQ_HEAD(, spifi_scb) free_scb; 87 TAILQ_HEAD(, spifi_scb) ready_scb; 88 }; 89 90 #define SPIFI_SYNC_OFFSET_MAX 7 91 92 #define SEND_REJECT 1 93 #define SEND_IDENTIFY 2 94 #define SEND_SDTR 4 95 96 #define SPIFI_DATAOUT 0 97 #define SPIFI_DATAIN PRS_IO 98 #define SPIFI_COMMAND PRS_CD 99 #define SPIFI_STATUS (PRS_CD | PRS_IO) 100 #define SPIFI_MSGOUT (PRS_MSG | PRS_CD) 101 #define SPIFI_MSGIN (PRS_MSG | PRS_CD | PRS_IO) 102 103 int spifi_match(struct device *, struct cfdata *, void *); 104 void spifi_attach(struct device *, struct device *, void *); 105 106 int spifi_scsi_cmd(struct scsipi_xfer *); 107 struct spifi_scb *spifi_get_scb(struct spifi_softc *); 108 void spifi_free_scb(struct spifi_softc *, struct spifi_scb *); 109 int spifi_poll(struct spifi_softc *); 110 void spifi_minphys(struct buf *); 111 112 void spifi_sched(struct spifi_softc *); 113 int spifi_intr(void *); 114 void spifi_pmatch(struct spifi_softc *); 115 116 void spifi_select(struct spifi_softc *); 117 void spifi_sendmsg(struct spifi_softc *, int); 118 void spifi_command(struct spifi_softc *); 119 void spifi_data_io(struct spifi_softc *); 120 void spifi_status(struct spifi_softc *); 121 int spifi_done(struct spifi_softc *); 122 void spifi_fifo_drain(struct spifi_softc *); 123 void spifi_reset(struct spifi_softc *); 124 void spifi_bus_reset(struct spifi_softc *); 125 126 static int spifi_read_count(struct spifi_reg *); 127 static void spifi_write_count(struct spifi_reg *, int); 128 129 #define DMAC3_FASTACCESS(sc) dmac3_misc((sc)->sc_dma, DMAC3_CONF_FASTACCESS) 130 #define DMAC3_SLOWACCESS(sc) dmac3_misc((sc)->sc_dma, DMAC3_CONF_SLOWACCESS) 131 132 struct scsipi_device spifi_dev = { 133 NULL, /* Use default error handler */ 134 NULL, /* have a queue, served by this */ 135 NULL, /* have no async handler */ 136 NULL, /* Use default 'done' routine */ 137 }; 138 139 struct scsipi_adapter spifi_adapter = { 140 0, 141 spifi_scsi_cmd, 142 spifi_minphys, 143 NULL, 144 NULL, 145 }; 146 147 struct cfattach spifi_ca = { 148 sizeof(struct spifi_softc), spifi_match, spifi_attach 149 }; 150 151 int 152 spifi_match(parent, cf, aux) 153 struct device *parent; 154 struct cfdata *cf; 155 void *aux; 156 { 157 struct apbus_attach_args *apa = aux; 158 159 if (strcmp(apa->apa_name, "spifi") == 0) 160 return 1; 161 162 return 0; 163 } 164 165 void 166 spifi_attach(parent, self, aux) 167 struct device *parent, *self; 168 void *aux; 169 { 170 struct spifi_softc *sc = (void *)self; 171 struct apbus_attach_args *apa = aux; 172 struct device *dma; 173 int intr, i; 174 175 /* Initialize scbs. */ 176 TAILQ_INIT(&sc->free_scb); 177 TAILQ_INIT(&sc->ready_scb); 178 for (i = 0; i < sizeof(sc->sc_scb)/sizeof(sc->sc_scb[0]); i++) 179 TAILQ_INSERT_TAIL(&sc->free_scb, &sc->sc_scb[i], chain); 180 181 sc->sc_reg = (struct spifi_reg *)apa->apa_hwbase; 182 sc->sc_id = 7; /* XXX */ 183 184 /* Find my dmac3. */ 185 dma = dmac3_link(apa->apa_ctlnum); 186 if (dma == NULL) { 187 printf(": cannot find slave dmac\n"); 188 return; 189 } 190 sc->sc_dma = dma; 191 192 printf(" slot%d addr 0x%lx", apa->apa_slotno, apa->apa_hwbase); 193 printf(": SCSI ID = %d, using %s\n", sc->sc_id, dma->dv_xname); 194 195 dmac3_reset(sc->sc_dma); 196 197 DMAC3_SLOWACCESS(sc); 198 spifi_reset(sc); 199 DMAC3_FASTACCESS(sc); 200 201 sc->sc_link.scsipi_scsi.adapter_target = sc->sc_id; 202 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 203 sc->sc_link.scsipi_scsi.max_target = 7; 204 sc->sc_link.scsipi_scsi.max_lun = 7; 205 sc->sc_link.adapter_softc = sc; 206 sc->sc_link.adapter = &spifi_adapter; 207 sc->sc_link.device = &spifi_dev; 208 sc->sc_link.openings = 2; 209 sc->sc_link.type = BUS_SCSI; 210 211 if (apa->apa_slotno == 0) 212 intr = NEWS5000_INT0_DMAC; 213 else 214 intr = SLOTTOMASK(apa->apa_slotno); 215 apbus_intr_establish(0, intr, 0, spifi_intr, sc, apa->apa_name, 216 apa->apa_ctlnum); 217 218 config_found(&sc->sc_dev, &sc->sc_link, scsiprint); 219 } 220 221 int 222 spifi_scsi_cmd(xs) 223 struct scsipi_xfer *xs; 224 { 225 struct scsipi_link *sc_link = xs->sc_link; 226 struct spifi_softc *sc = sc_link->adapter_softc; 227 struct spifi_scb *scb; 228 u_int flags; 229 int s; 230 231 DPRINTF("spifi_scsi_cmd\n"); 232 233 flags = xs->xs_control; 234 235 scb = spifi_get_scb(sc); 236 if (scb == NULL) { 237 DPRINTF("no scb\n"); 238 return TRY_AGAIN_LATER; 239 } 240 241 scb->xs = xs; 242 scb->flags = 0; 243 scb->status = 0; 244 scb->daddr = (vaddr_t)xs->data; 245 scb->resid = xs->datalen; 246 bcopy(xs->cmd, &scb->cmd, xs->cmdlen); 247 scb->cmdlen = xs->cmdlen; 248 249 scb->target = sc_link->scsipi_scsi.target; 250 scb->lun = sc_link->scsipi_scsi.lun; 251 scb->lun_targ = scb->target | (scb->lun << 3); 252 253 if (flags & XS_CTL_DATA_IN) 254 scb->flags |= SPIFI_READ; 255 256 s = splbio(); 257 258 TAILQ_INSERT_TAIL(&sc->ready_scb, scb, chain); 259 260 if (sc->sc_nexus == NULL) /* IDLE */ 261 spifi_sched(sc); 262 263 splx(s); 264 265 if ((flags & XS_CTL_POLL) == 0) 266 return SUCCESSFULLY_QUEUED; 267 268 if (spifi_poll(sc)) { 269 printf("spifi: timeout\n"); 270 if (spifi_poll(sc)) 271 printf("spifi: timeout again\n"); 272 } 273 return COMPLETE; 274 } 275 276 struct spifi_scb * 277 spifi_get_scb(sc) 278 struct spifi_softc *sc; 279 { 280 struct spifi_scb *scb; 281 int s; 282 283 s = splbio(); 284 scb = sc->free_scb.tqh_first; 285 if (scb) 286 TAILQ_REMOVE(&sc->free_scb, scb, chain); 287 splx(s); 288 289 return scb; 290 } 291 292 void 293 spifi_free_scb(sc, scb) 294 struct spifi_softc *sc; 295 struct spifi_scb *scb; 296 { 297 int s; 298 299 s = splbio(); 300 TAILQ_INSERT_HEAD(&sc->free_scb, scb, chain); 301 splx(s); 302 } 303 304 int 305 spifi_poll(sc) 306 struct spifi_softc *sc; 307 { 308 struct spifi_scb *scb = sc->sc_nexus; 309 struct scsipi_xfer *xs; 310 int count; 311 312 printf("spifi_poll: not implemented yet\n"); 313 delay(10000); 314 return 0; 315 316 if (xs == NULL) 317 return 0; 318 319 xs = scb->xs; 320 count = xs->timeout; 321 322 while (count > 0) { 323 if (dmac3_intr(sc->sc_dma) != 0) 324 spifi_intr(sc); 325 326 if (xs->xs_status & XS_STS_DONE) 327 return 0; 328 DELAY(1000); 329 count--; 330 }; 331 return 1; 332 } 333 334 void 335 spifi_minphys(bp) 336 struct buf *bp; 337 { 338 if (bp->b_bcount > 64*1024) 339 bp->b_bcount = 64*1024; 340 341 minphys(bp); 342 } 343 344 void 345 spifi_sched(sc) 346 struct spifi_softc *sc; 347 { 348 struct spifi_scb *scb; 349 350 scb = sc->ready_scb.tqh_first; 351 start: 352 if (scb == NULL || sc->sc_nexus != NULL) 353 return; 354 /* 355 if (sc->sc_targets[scb->target] & (1 << scb->lun)) 356 goto next; 357 */ 358 TAILQ_REMOVE(&sc->ready_scb, scb, chain); 359 360 #ifdef SPIFI_DEBUG 361 { 362 int i; 363 364 printf("spifi_sched: ID:LUN = %d:%d, ", scb->target, scb->lun); 365 printf("cmd = 0x%x", scb->cmd.opcode); 366 for (i = 0; i < 5; i++) 367 printf(" 0x%x", scb->cmd.bytes[i]); 368 printf("\n"); 369 } 370 #endif 371 372 DMAC3_SLOWACCESS(sc); 373 sc->sc_nexus = scb; 374 spifi_select(sc); 375 DMAC3_FASTACCESS(sc); 376 377 scb = scb->chain.tqe_next; 378 goto start; 379 } 380 381 static inline int 382 spifi_read_count(reg) 383 struct spifi_reg *reg; 384 { 385 int count; 386 387 count = (reg->count_hi & 0xff) | 388 (reg->count_mid & 0xff) | 389 (reg->count_low & 0xff); 390 return count; 391 } 392 393 static inline void 394 spifi_write_count(reg, count) 395 struct spifi_reg *reg; 396 int count; 397 { 398 reg->count_hi = count >> 16; 399 reg->count_mid = count >> 8; 400 reg->count_low = count; 401 } 402 403 404 #ifdef SPIFI_DEBUG 405 static char scsi_phase_name[][8] = { 406 "DATAOUT", "DATAIN", "COMMAND", "STATUS", 407 "", "", "MSGOUT", "MSGIN" 408 }; 409 #endif 410 411 int 412 spifi_intr(v) 413 void *v; 414 { 415 struct spifi_softc *sc = v; 416 struct spifi_reg *reg = sc->sc_reg; 417 int intr, state, icond; 418 struct spifi_scb *scb; 419 struct scsipi_xfer *xs; 420 #ifdef SPIFI_DEBUG 421 char bitmask[64]; 422 #endif 423 424 switch (dmac3_intr(sc->sc_dma)) { 425 case 0: 426 DPRINTF("sprious dma intr\n"); 427 return 0; 428 case -1: 429 printf("DMAC parity error, data PAD\n"); 430 431 DMAC3_SLOWACCESS(sc); 432 reg->prcmd = PRC_TRPAD; 433 DMAC3_FASTACCESS(sc); 434 return 1; 435 436 default: 437 break; 438 } 439 DMAC3_SLOWACCESS(sc); 440 441 intr = reg->intr & 0xff; 442 if (intr == 0) { 443 DMAC3_FASTACCESS(sc); 444 DPRINTF("sprious intr (not me)\n"); 445 return 0; 446 } 447 448 scb = sc->sc_nexus; 449 xs = scb->xs; 450 state = reg->spstat; 451 icond = reg->icond; 452 453 /* clear interrupt */ 454 reg->intr = ~intr; 455 456 #ifdef SPIFI_DEBUG 457 bitmask_snprintf(intr, INTR_BITMASK, bitmask, sizeof bitmask); 458 printf("spifi_intr intr = 0x%s (%s), ", bitmask, 459 scsi_phase_name[(reg->prstat >> 3) & 7]); 460 printf("state = 0x%x, icond = 0x%x\n", state, icond); 461 #endif 462 463 if (intr & INTR_FCOMP) { 464 spifi_fifo_drain(sc); 465 scb->status = reg->cmbuf[scb->target].status; 466 scb->resid = spifi_read_count(reg); 467 468 DPRINTF("datalen = %d, resid = %d, status = 0x%x\n", 469 xs->datalen, scb->resid, scb->status); 470 DPRINTF("msg = 0x%x\n", reg->cmbuf[sc->sc_id].cdb[0]); 471 472 DMAC3_FASTACCESS(sc); 473 spifi_done(sc); 474 return 1; 475 } 476 if (intr & INTR_DISCON) 477 panic("disconnect"); 478 479 if (intr & INTR_TIMEO) { 480 xs->error = XS_SELTIMEOUT; 481 DMAC3_FASTACCESS(sc); 482 spifi_done(sc); 483 return 1; 484 } 485 if (intr & INTR_BSRQ) { 486 if (scb == NULL) 487 panic("reconnect?"); 488 489 if (intr & INTR_PERR) { 490 printf("%s: %d:%d parity error\n", sc->sc_dev.dv_xname, 491 scb->target, scb->lun); 492 493 /* XXX reset */ 494 xs->error = XS_DRIVER_STUFFUP; 495 spifi_done(sc); 496 return 1; 497 } 498 499 if (state >> 4 == SPS_MSGIN && icond == ICOND_NXTREQ) 500 panic("spifi_intr: NXTREQ"); 501 if (reg->fifoctrl & FIFOC_RQOVRN) 502 panic("spifi_intr RQOVRN"); 503 if (icond == ICOND_UXPHASEZ) 504 panic("ICOND_UXPHASEZ"); 505 506 if ((icond & 0x0f) == ICOND_ADATAOFF) { 507 spifi_data_io(sc); 508 goto done; 509 } 510 if ((icond & 0xf0) == ICOND_UBF) { 511 reg->exstat = reg->exstat & ~EXS_UBF; 512 spifi_pmatch(sc); 513 goto done; 514 } 515 516 /* 517 * XXX Work around the SPIFI bug that interrupts during 518 * XXX dataout phase. 519 */ 520 if (state == ((SPS_DATAOUT << 4) | SPS_INTR) && 521 (reg->prstat & PRS_PHASE) == SPIFI_DATAOUT) { 522 reg->prcmd = PRC_DATAOUT; 523 goto done; 524 } 525 if ((reg->prstat & PRS_Z) == 0) { 526 spifi_pmatch(sc); 527 goto done; 528 } 529 530 panic("spifi_intr: unknown intr state"); 531 } 532 533 done: 534 DMAC3_FASTACCESS(sc); 535 return 1; 536 } 537 538 void 539 spifi_pmatch(sc) 540 struct spifi_softc *sc; 541 { 542 struct spifi_reg *reg = sc->sc_reg; 543 int phase; 544 545 phase = (reg->prstat & PRS_PHASE); 546 547 #ifdef SPIFI_DEBUG 548 printf("spifi_pmatch (%s)\n", scsi_phase_name[phase >> 3]); 549 #endif 550 551 switch (phase) { 552 553 case SPIFI_COMMAND: 554 spifi_command(sc); 555 break; 556 case SPIFI_DATAIN: 557 case SPIFI_DATAOUT: 558 spifi_data_io(sc); 559 break; 560 case SPIFI_STATUS: 561 spifi_status(sc); 562 break; 563 564 case SPIFI_MSGIN: /* XXX */ 565 case SPIFI_MSGOUT: /* XXX */ 566 default: 567 printf("spifi: unknown phase %d\n", phase); 568 } 569 } 570 571 void 572 spifi_select(sc) 573 struct spifi_softc *sc; 574 { 575 struct spifi_reg *reg = sc->sc_reg; 576 struct spifi_scb *scb = sc->sc_nexus; 577 int sel; 578 579 #if 0 580 if (reg->loopdata || reg->intr) 581 return; 582 #endif 583 584 if (scb == NULL) { 585 printf("%s: spifi_select: NULL nexus\n", sc->sc_dev.dv_xname); 586 return; 587 } 588 589 reg->exctrl = EXC_IPLOCK; 590 591 dmac3_reset(sc->sc_dma); 592 sel = scb->target << 4 | SEL_ISTART | SEL_IRESELEN | SEL_WATN; 593 spifi_sendmsg(sc, SEND_IDENTIFY); 594 reg->select = sel; 595 } 596 597 void 598 spifi_sendmsg(sc, msg) 599 struct spifi_softc *sc; 600 int msg; 601 { 602 struct spifi_scb *scb = sc->sc_nexus; 603 /* struct mesh_tinfo *ti; */ 604 int lun, len, i; 605 606 int id = sc->sc_id; 607 struct spifi_reg *reg = sc->sc_reg; 608 609 DPRINTF("spifi_sendmsg: sending"); 610 sc->sc_msgout = msg; 611 len = 0; 612 613 if (msg & SEND_REJECT) { 614 DPRINTF(" REJECT"); 615 sc->sc_omsg[len++] = MSG_MESSAGE_REJECT; 616 } 617 if (msg & SEND_IDENTIFY) { 618 DPRINTF(" IDENTIFY"); 619 lun = scb->xs->sc_link->scsipi_scsi.lun; 620 sc->sc_omsg[len++] = MSG_IDENTIFY(lun, 0); 621 } 622 if (msg & SEND_SDTR) { 623 DPRINTF(" SDTR"); 624 #if 0 625 ti = &sc->sc_tinfo[scb->target]; 626 sc->sc_omsg[len++] = MSG_EXTENDED; 627 sc->sc_omsg[len++] = 3; 628 sc->sc_omsg[len++] = MSG_EXT_SDTR; 629 sc->sc_omsg[len++] = ti->period; 630 sc->sc_omsg[len++] = ti->offset; 631 #endif 632 } 633 DPRINTF("\n"); 634 635 reg->cmlen = CML_AMSG_EN | len; 636 for (i = 0; i < len; i++) 637 reg->cmbuf[id].cdb[i] = sc->sc_omsg[i]; 638 } 639 void 640 spifi_command(struct spifi_softc *sc) 641 { 642 struct spifi_scb *scb = sc->sc_nexus; 643 struct spifi_reg *reg = sc->sc_reg; 644 int len = scb->cmdlen; 645 u_char *cmdp = (char *)&scb->cmd; 646 int i; 647 648 DPRINTF("spifi_command\n"); 649 650 reg->cmdpage = scb->lun_targ; 651 652 if (reg->init_status & IST_ACK) { 653 /* Negate ACK. */ 654 reg->prcmd = PRC_NJMP | PRC_CLRACK | PRC_COMMAND; 655 reg->prcmd = PRC_NJMP | PRC_COMMAND; 656 } 657 658 reg->cmlen = CML_AMSG_EN | len; 659 660 for (i = 0; i < len; i++) 661 reg->cmbuf[sc->sc_id].cdb[i] = *cmdp++; 662 663 reg->prcmd = PRC_COMMAND; 664 } 665 666 void 667 spifi_data_io(struct spifi_softc *sc) 668 { 669 struct spifi_scb *scb = sc->sc_nexus; 670 struct spifi_reg *reg = sc->sc_reg; 671 int phase; 672 673 DPRINTF("spifi_data_io\n"); 674 675 phase = reg->prstat & PRS_PHASE; 676 dmac3_reset(sc->sc_dma); 677 678 spifi_write_count(reg, scb->resid); 679 reg->cmlen = CML_AMSG_EN | 1; 680 reg->data_xfer = 0; 681 682 scb->flags |= SPIFI_DMA; 683 if (phase == SPIFI_DATAIN) { 684 if (reg->fifoctrl & FIFOC_SSTKACT) { 685 /* 686 * Clear FIFO and load the contents of synchronous 687 * stack into the FIFO. 688 */ 689 reg->fifoctrl = FIFOC_CLREVEN; 690 reg->fifoctrl = FIFOC_LOAD; 691 } 692 reg->autodata = ADATA_IN | scb->lun_targ; 693 dmac3_start(sc->sc_dma, scb->daddr, scb->resid, DMAC3_CSR_RECV); 694 reg->prcmd = PRC_DATAIN; 695 } else { 696 reg->fifoctrl = FIFOC_CLREVEN; 697 reg->autodata = scb->lun_targ; 698 dmac3_start(sc->sc_dma, scb->daddr, scb->resid, DMAC3_CSR_SEND); 699 reg->prcmd = PRC_DATAOUT; 700 } 701 } 702 703 void 704 spifi_status(struct spifi_softc *sc) 705 { 706 struct spifi_reg *reg = sc->sc_reg; 707 708 DPRINTF("spifi_status\n"); 709 spifi_fifo_drain(sc); 710 reg->cmlen = CML_AMSG_EN | 1; 711 reg->prcmd = PRC_STATUS; 712 } 713 714 int 715 spifi_done(sc) 716 struct spifi_softc *sc; 717 { 718 struct spifi_scb *scb = sc->sc_nexus; 719 struct scsipi_xfer *xs = scb->xs; 720 721 DPRINTF("spifi_done\n"); 722 723 /* XXX sense */ 724 725 if (scb->status == SCSI_CHECK) 726 DPRINTF("spifi_done: CHECK CONDITION\n"); 727 728 xs->xs_status |= XS_STS_DONE; 729 xs->resid = scb->resid; 730 731 scsipi_done(xs); 732 spifi_free_scb(sc, scb); 733 734 sc->sc_nexus = NULL; 735 spifi_sched(sc); 736 737 return FALSE; 738 } 739 740 void 741 spifi_fifo_drain(sc) 742 struct spifi_softc *sc; 743 { 744 struct spifi_scb *scb = sc->sc_nexus; 745 struct spifi_reg *reg = sc->sc_reg; 746 int fifoctrl, fifo_count; 747 748 DPRINTF("spifi_fifo_drain\n"); 749 750 if ((scb->flags & SPIFI_READ) == 0) 751 return; 752 753 fifoctrl = reg->fifoctrl; 754 if (fifoctrl & FIFOC_SSTKACT) 755 return; 756 757 fifo_count = 8 - (fifoctrl & FIFOC_FSLOT); 758 if (fifo_count > 0 && (scb->flags & SPIFI_DMA)) { 759 /* Flush data still in FIFO. */ 760 reg->fifoctrl = FIFOC_FLUSH; 761 return; 762 } 763 764 reg->fifoctrl = FIFOC_CLREVEN; 765 } 766 767 void 768 spifi_reset(sc) 769 struct spifi_softc *sc; 770 { 771 struct spifi_reg *reg = sc->sc_reg; 772 int id = sc->sc_id; 773 774 DPRINTF("spifi_reset\n"); 775 776 reg->auxctrl = AUXCTRL_SRST; 777 reg->auxctrl = AUXCTRL_CRST; 778 779 dmac3_reset(sc->sc_dma); 780 781 reg->auxctrl = AUXCTRL_SRST; 782 reg->auxctrl = AUXCTRL_CRST; 783 reg->auxctrl = AUXCTRL_DMAEDGE; 784 785 /* Mask (only) target mode interrupts. */ 786 reg->imask = INTR_TGSEL | INTR_COMRECV; 787 788 reg->config = CONFIG_DMABURST | CONFIG_PCHKEN | CONFIG_PGENEN | id; 789 reg->fastwide = FAST_FASTEN; 790 reg->prctrl = 0; 791 reg->loopctrl = 0; 792 793 /* Enable automatic status input except the initiator. */ 794 reg->autostat = ~(1 << id); 795 796 reg->fifoctrl = FIFOC_CLREVEN; 797 spifi_write_count(reg, 0); 798 799 /* Flush write buffer. */ 800 (void)reg->spstat; 801 } 802 803 void 804 spifi_bus_reset(sc) 805 struct spifi_softc *sc; 806 { 807 struct spifi_reg *reg = sc->sc_reg; 808 809 printf("%s: bus reset\n", sc->sc_dev.dv_xname); 810 811 sc->sc_nexus = NULL; 812 813 reg->auxctrl = AUXCTRL_SETRST; 814 delay(100); 815 reg->auxctrl = 0; 816 } 817 818 #if 0 819 static u_char spifi_sync_period[] = { 820 /* 0 1 2 3 4 5 6 7 8 9 10 11 */ 821 137, 125, 112, 100, 87, 75, 62, 50, 43, 37, 31, 25 822 }; 823 824 void 825 spifi_setsync(sc, ti) 826 struct spifi_softc *sc; 827 struct spifi_tinfo *ti; 828 { 829 if ((ti->flags & T_SYNCMODE) == 0) 830 reg->data_xfer = 0; 831 else { 832 int period = ti->period; 833 int offset = ti->offset; 834 int v; 835 836 for (v = sizeof(spifi_sync_period) - 1; v >= 0; v--) 837 if (spifi_sync_period[v] >= period) 838 break; 839 if (v == -1) 840 reg->data_xfer = 0; /* XXX */ 841 else 842 reg->data_xfer = v << 4 | offset; 843 } 844 } 845 #endif 846
Indexes created Tue Sep 30 20:09:53 GMT 2025