spifi.c revision 1.12
1 /* $NetBSD: spifi.c,v 1.12 2004/12/07 22:23:45 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: spifi.c,v 1.12 2004/12/07 22:23:45 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/buf.h> 34 #include <sys/device.h> 35 #include <sys/errno.h> 36 #include <sys/kernel.h> 37 #include <sys/queue.h> 38 #include <sys/systm.h> 39 40 #include <uvm/uvm_extern.h> 41 42 #include <dev/scsipi/scsi_all.h> 43 #include <dev/scsipi/scsi_message.h> 44 #include <dev/scsipi/scsipi_all.h> 45 #include <dev/scsipi/scsiconf.h> 46 47 #include <newsmips/apbus/apbusvar.h> 48 #include <newsmips/apbus/spifireg.h> 49 #include <newsmips/apbus/dmac3reg.h> 50 51 #include <machine/adrsmap.h> 52 53 /* #define SPIFI_DEBUG */ 54 55 #ifdef SPIFI_DEBUG 56 # define DPRINTF printf 57 #else 58 # define DPRINTF while (0) printf 59 #endif 60 61 struct spifi_scb { 62 TAILQ_ENTRY(spifi_scb) chain; 63 int flags; 64 struct scsipi_xfer *xs; 65 struct scsipi_generic cmd; 66 int cmdlen; 67 int resid; 68 vaddr_t daddr; 69 u_char target; 70 u_char lun; 71 u_char lun_targ; 72 u_char status; 73 }; 74 /* scb flags */ 75 #define SPIFI_READ 0x80 76 #define SPIFI_DMA 0x01 77 78 struct spifi_softc { 79 struct device sc_dev; 80 struct scsipi_channel sc_channel; 81 struct scsipi_adapter sc_adapter; 82 83 struct spifi_reg *sc_reg; 84 struct spifi_scb *sc_nexus; 85 void *sc_dma; /* attached DMA softc */ 86 int sc_id; /* my SCSI ID */ 87 int sc_msgout; 88 u_char sc_omsg[16]; 89 struct spifi_scb sc_scb[16]; 90 TAILQ_HEAD(, spifi_scb) free_scb; 91 TAILQ_HEAD(, spifi_scb) ready_scb; 92 }; 93 94 #define SPIFI_SYNC_OFFSET_MAX 7 95 96 #define SEND_REJECT 1 97 #define SEND_IDENTIFY 2 98 #define SEND_SDTR 4 99 100 #define SPIFI_DATAOUT 0 101 #define SPIFI_DATAIN PRS_IO 102 #define SPIFI_COMMAND PRS_CD 103 #define SPIFI_STATUS (PRS_CD | PRS_IO) 104 #define SPIFI_MSGOUT (PRS_MSG | PRS_CD) 105 #define SPIFI_MSGIN (PRS_MSG | PRS_CD | PRS_IO) 106 107 int spifi_match(struct device *, struct cfdata *, void *); 108 void spifi_attach(struct device *, struct device *, void *); 109 110 void spifi_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, void *); 111 struct spifi_scb *spifi_get_scb(struct spifi_softc *); 112 void spifi_free_scb(struct spifi_softc *, struct spifi_scb *); 113 int spifi_poll(struct spifi_softc *); 114 void spifi_minphys(struct buf *); 115 116 void spifi_sched(struct spifi_softc *); 117 int spifi_intr(void *); 118 void spifi_pmatch(struct spifi_softc *); 119 120 void spifi_select(struct spifi_softc *); 121 void spifi_sendmsg(struct spifi_softc *, int); 122 void spifi_command(struct spifi_softc *); 123 void spifi_data_io(struct spifi_softc *); 124 void spifi_status(struct spifi_softc *); 125 int spifi_done(struct spifi_softc *); 126 void spifi_fifo_drain(struct spifi_softc *); 127 void spifi_reset(struct spifi_softc *); 128 void spifi_bus_reset(struct spifi_softc *); 129 130 static int spifi_read_count(struct spifi_reg *); 131 static void spifi_write_count(struct spifi_reg *, int); 132 133 #define DMAC3_FASTACCESS(sc) dmac3_misc((sc)->sc_dma, DMAC3_CONF_FASTACCESS) 134 #define DMAC3_SLOWACCESS(sc) dmac3_misc((sc)->sc_dma, DMAC3_CONF_SLOWACCESS) 135 136 CFATTACH_DECL(spifi, sizeof(struct spifi_softc), 137 spifi_match, spifi_attach, NULL, NULL); 138 139 int 140 spifi_match(parent, cf, aux) 141 struct device *parent; 142 struct cfdata *cf; 143 void *aux; 144 { 145 struct apbus_attach_args *apa = aux; 146 147 if (strcmp(apa->apa_name, "spifi") == 0) 148 return 1; 149 150 return 0; 151 } 152 153 void 154 spifi_attach(parent, self, aux) 155 struct device *parent, *self; 156 void *aux; 157 { 158 struct spifi_softc *sc = (void *)self; 159 struct apbus_attach_args *apa = aux; 160 struct device *dma; 161 int intr, i; 162 163 /* Initialize scbs. */ 164 TAILQ_INIT(&sc->free_scb); 165 TAILQ_INIT(&sc->ready_scb); 166 for (i = 0; i < sizeof(sc->sc_scb)/sizeof(sc->sc_scb[0]); i++) 167 TAILQ_INSERT_TAIL(&sc->free_scb, &sc->sc_scb[i], chain); 168 169 sc->sc_reg = (struct spifi_reg *)apa->apa_hwbase; 170 sc->sc_id = 7; /* XXX */ 171 172 /* Find my dmac3. */ 173 dma = dmac3_link(apa->apa_ctlnum); 174 if (dma == NULL) { 175 printf(": cannot find slave dmac\n"); 176 return; 177 } 178 sc->sc_dma = dma; 179 180 printf(" slot%d addr 0x%lx", apa->apa_slotno, apa->apa_hwbase); 181 printf(": SCSI ID = %d, using %s\n", sc->sc_id, dma->dv_xname); 182 183 dmac3_reset(sc->sc_dma); 184 185 DMAC3_SLOWACCESS(sc); 186 spifi_reset(sc); 187 DMAC3_FASTACCESS(sc); 188 189 sc->sc_adapter.adapt_dev = &sc->sc_dev; 190 sc->sc_adapter.adapt_nchannels = 1; 191 sc->sc_adapter.adapt_openings = 7; 192 sc->sc_adapter.adapt_max_periph = 1; 193 sc->sc_adapter.adapt_ioctl = NULL; 194 sc->sc_adapter.adapt_minphys = minphys; 195 sc->sc_adapter.adapt_request = spifi_scsipi_request; 196 197 memset(&sc->sc_channel, 0, sizeof(sc->sc_channel)); 198 sc->sc_channel.chan_adapter = &sc->sc_adapter; 199 sc->sc_channel.chan_bustype = &scsi_bustype; 200 sc->sc_channel.chan_channel = 0; 201 sc->sc_channel.chan_ntargets = 8; 202 sc->sc_channel.chan_nluns = 8; 203 sc->sc_channel.chan_id = sc->sc_id; 204 205 if (apa->apa_slotno == 0) 206 intr = NEWS5000_INT0_DMAC; 207 else 208 intr = SLOTTOMASK(apa->apa_slotno); 209 apbus_intr_establish(0, intr, 0, spifi_intr, sc, apa->apa_name, 210 apa->apa_ctlnum); 211 212 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 213 } 214 215 void 216 spifi_scsipi_request(chan, req, arg) 217 struct scsipi_channel *chan; 218 scsipi_adapter_req_t req; 219 void *arg; 220 { 221 struct scsipi_xfer *xs; 222 struct scsipi_periph *periph; 223 struct spifi_softc *sc = (void *)chan->chan_adapter->adapt_dev; 224 struct spifi_scb *scb; 225 u_int flags; 226 int s; 227 228 switch (req) { 229 case ADAPTER_REQ_RUN_XFER: 230 xs = arg; 231 periph = xs->xs_periph; 232 233 DPRINTF("spifi_scsi_cmd\n"); 234 235 flags = xs->xs_control; 236 237 scb = spifi_get_scb(sc); 238 if (scb == NULL) { 239 panic("spifi_scsipi_request: no scb"); 240 } 241 242 scb->xs = xs; 243 scb->flags = 0; 244 scb->status = 0; 245 scb->daddr = (vaddr_t)xs->data; 246 scb->resid = xs->datalen; 247 bcopy(xs->cmd, &scb->cmd, xs->cmdlen); 248 scb->cmdlen = xs->cmdlen; 249 250 scb->target = periph->periph_target; 251 scb->lun = periph->periph_lun; 252 scb->lun_targ = scb->target | (scb->lun << 3); 253 254 if (flags & XS_CTL_DATA_IN) 255 scb->flags |= SPIFI_READ; 256 257 s = splbio(); 258 259 TAILQ_INSERT_TAIL(&sc->ready_scb, scb, chain); 260 261 if (sc->sc_nexus == NULL) /* IDLE */ 262 spifi_sched(sc); 263 264 splx(s); 265 266 if (flags & XS_CTL_POLL) { 267 if (spifi_poll(sc)) { 268 printf("spifi: timeout\n"); 269 if (spifi_poll(sc)) 270 printf("spifi: timeout again\n"); 271 } 272 } 273 return; 274 case ADAPTER_REQ_GROW_RESOURCES: 275 /* XXX Not supported. */ 276 return; 277 case ADAPTER_REQ_SET_XFER_MODE: 278 /* XXX Not supported. */ 279 return; 280 } 281 } 282 283 struct spifi_scb * 284 spifi_get_scb(sc) 285 struct spifi_softc *sc; 286 { 287 struct spifi_scb *scb; 288 int s; 289 290 s = splbio(); 291 scb = sc->free_scb.tqh_first; 292 if (scb) 293 TAILQ_REMOVE(&sc->free_scb, scb, chain); 294 splx(s); 295 296 return scb; 297 } 298 299 void 300 spifi_free_scb(sc, scb) 301 struct spifi_softc *sc; 302 struct spifi_scb *scb; 303 { 304 int s; 305 306 s = splbio(); 307 TAILQ_INSERT_HEAD(&sc->free_scb, scb, chain); 308 splx(s); 309 } 310 311 int 312 spifi_poll(sc) 313 struct spifi_softc *sc; 314 { 315 struct spifi_scb *scb = sc->sc_nexus; 316 struct scsipi_xfer *xs; 317 int count; 318 319 printf("spifi_poll: not implemented yet\n"); 320 delay(10000); 321 scb->status = SCSI_OK; 322 scb->resid = 0; 323 spifi_done(sc); 324 return 0; 325 326 if (xs == NULL) 327 return 0; 328 329 xs = scb->xs; 330 count = xs->timeout; 331 332 while (count > 0) { 333 if (dmac3_intr(sc->sc_dma) != 0) 334 spifi_intr(sc); 335 336 if (xs->xs_status & XS_STS_DONE) 337 return 0; 338 DELAY(1000); 339 count--; 340 }; 341 return 1; 342 } 343 344 void 345 spifi_minphys(bp) 346 struct buf *bp; 347 { 348 if (bp->b_bcount > 64*1024) 349 bp->b_bcount = 64*1024; 350 351 minphys(bp); 352 } 353 354 void 355 spifi_sched(sc) 356 struct spifi_softc *sc; 357 { 358 struct spifi_scb *scb; 359 360 scb = sc->ready_scb.tqh_first; 361 start: 362 if (scb == NULL || sc->sc_nexus != NULL) 363 return; 364 /* 365 if (sc->sc_targets[scb->target] & (1 << scb->lun)) 366 goto next; 367 */ 368 TAILQ_REMOVE(&sc->ready_scb, scb, chain); 369 370 #ifdef SPIFI_DEBUG 371 { 372 int i; 373 374 printf("spifi_sched: ID:LUN = %d:%d, ", scb->target, scb->lun); 375 printf("cmd = 0x%x", scb->cmd.opcode); 376 for (i = 0; i < 5; i++) 377 printf(" 0x%x", scb->cmd.bytes[i]); 378 printf("\n"); 379 } 380 #endif 381 382 DMAC3_SLOWACCESS(sc); 383 sc->sc_nexus = scb; 384 spifi_select(sc); 385 DMAC3_FASTACCESS(sc); 386 387 scb = scb->chain.tqe_next; 388 goto start; 389 } 390 391 static inline int 392 spifi_read_count(reg) 393 struct spifi_reg *reg; 394 { 395 int count; 396 397 count = (reg->count_hi & 0xff) << 16 | 398 (reg->count_mid & 0xff) << 8 | 399 (reg->count_low & 0xff); 400 return count; 401 } 402 403 static inline void 404 spifi_write_count(reg, count) 405 struct spifi_reg *reg; 406 int count; 407 { 408 reg->count_hi = count >> 16; 409 reg->count_mid = count >> 8; 410 reg->count_low = count; 411 } 412 413 414 #ifdef SPIFI_DEBUG 415 static char scsi_phase_name[][8] = { 416 "DATAOUT", "DATAIN", "COMMAND", "STATUS", 417 "", "", "MSGOUT", "MSGIN" 418 }; 419 #endif 420 421 int 422 spifi_intr(v) 423 void *v; 424 { 425 struct spifi_softc *sc = v; 426 struct spifi_reg *reg = sc->sc_reg; 427 int intr, state, icond; 428 struct spifi_scb *scb; 429 struct scsipi_xfer *xs; 430 #ifdef SPIFI_DEBUG 431 char bitmask[64]; 432 #endif 433 434 switch (dmac3_intr(sc->sc_dma)) { 435 case 0: 436 DPRINTF("spurious DMA intr\n"); 437 return 0; 438 case -1: 439 printf("DMAC parity error, data PAD\n"); 440 441 DMAC3_SLOWACCESS(sc); 442 reg->prcmd = PRC_TRPAD; 443 DMAC3_FASTACCESS(sc); 444 return 1; 445 446 default: 447 break; 448 } 449 DMAC3_SLOWACCESS(sc); 450 451 intr = reg->intr & 0xff; 452 if (intr == 0) { 453 DMAC3_FASTACCESS(sc); 454 DPRINTF("spurious intr (not me)\n"); 455 return 0; 456 } 457 458 scb = sc->sc_nexus; 459 xs = scb->xs; 460 state = reg->spstat; 461 icond = reg->icond; 462 463 /* clear interrupt */ 464 reg->intr = ~intr; 465 466 #ifdef SPIFI_DEBUG 467 bitmask_snprintf(intr, INTR_BITMASK, bitmask, sizeof bitmask); 468 printf("spifi_intr intr = 0x%s (%s), ", bitmask, 469 scsi_phase_name[(reg->prstat >> 3) & 7]); 470 printf("state = 0x%x, icond = 0x%x\n", state, icond); 471 #endif 472 473 if (intr & INTR_FCOMP) { 474 spifi_fifo_drain(sc); 475 scb->status = reg->cmbuf[scb->target].status; 476 scb->resid = spifi_read_count(reg); 477 478 DPRINTF("datalen = %d, resid = %d, status = 0x%x\n", 479 xs->datalen, scb->resid, scb->status); 480 DPRINTF("msg = 0x%x\n", reg->cmbuf[sc->sc_id].cdb[0]); 481 482 DMAC3_FASTACCESS(sc); 483 spifi_done(sc); 484 return 1; 485 } 486 if (intr & INTR_DISCON) 487 panic("disconnect"); 488 489 if (intr & INTR_TIMEO) { 490 xs->error = XS_SELTIMEOUT; 491 DMAC3_FASTACCESS(sc); 492 spifi_done(sc); 493 return 1; 494 } 495 if (intr & INTR_BSRQ) { 496 if (scb == NULL) 497 panic("reconnect?"); 498 499 if (intr & INTR_PERR) { 500 printf("%s: %d:%d parity error\n", sc->sc_dev.dv_xname, 501 scb->target, scb->lun); 502 503 /* XXX reset */ 504 xs->error = XS_DRIVER_STUFFUP; 505 spifi_done(sc); 506 return 1; 507 } 508 509 if (state >> 4 == SPS_MSGIN && icond == ICOND_NXTREQ) 510 panic("spifi_intr: NXTREQ"); 511 if (reg->fifoctrl & FIFOC_RQOVRN) 512 panic("spifi_intr RQOVRN"); 513 if (icond == ICOND_UXPHASEZ) 514 panic("ICOND_UXPHASEZ"); 515 516 if ((icond & 0x0f) == ICOND_ADATAOFF) { 517 spifi_data_io(sc); 518 goto done; 519 } 520 if ((icond & 0xf0) == ICOND_UBF) { 521 reg->exstat = reg->exstat & ~EXS_UBF; 522 spifi_pmatch(sc); 523 goto done; 524 } 525 526 /* 527 * XXX Work around the SPIFI bug that interrupts during 528 * XXX dataout phase. 529 */ 530 if (state == ((SPS_DATAOUT << 4) | SPS_INTR) && 531 (reg->prstat & PRS_PHASE) == SPIFI_DATAOUT) { 532 reg->prcmd = PRC_DATAOUT; 533 goto done; 534 } 535 if ((reg->prstat & PRS_Z) == 0) { 536 spifi_pmatch(sc); 537 goto done; 538 } 539 540 panic("spifi_intr: unknown intr state"); 541 } 542 543 done: 544 DMAC3_FASTACCESS(sc); 545 return 1; 546 } 547 548 void 549 spifi_pmatch(sc) 550 struct spifi_softc *sc; 551 { 552 struct spifi_reg *reg = sc->sc_reg; 553 int phase; 554 555 phase = (reg->prstat & PRS_PHASE); 556 557 #ifdef SPIFI_DEBUG 558 printf("spifi_pmatch (%s)\n", scsi_phase_name[phase >> 3]); 559 #endif 560 561 switch (phase) { 562 563 case SPIFI_COMMAND: 564 spifi_command(sc); 565 break; 566 case SPIFI_DATAIN: 567 case SPIFI_DATAOUT: 568 spifi_data_io(sc); 569 break; 570 case SPIFI_STATUS: 571 spifi_status(sc); 572 break; 573 574 case SPIFI_MSGIN: /* XXX */ 575 case SPIFI_MSGOUT: /* XXX */ 576 default: 577 printf("spifi: unknown phase %d\n", phase); 578 } 579 } 580 581 void 582 spifi_select(sc) 583 struct spifi_softc *sc; 584 { 585 struct spifi_reg *reg = sc->sc_reg; 586 struct spifi_scb *scb = sc->sc_nexus; 587 int sel; 588 589 #if 0 590 if (reg->loopdata || reg->intr) 591 return; 592 #endif 593 594 if (scb == NULL) { 595 printf("%s: spifi_select: NULL nexus\n", sc->sc_dev.dv_xname); 596 return; 597 } 598 599 reg->exctrl = EXC_IPLOCK; 600 601 dmac3_reset(sc->sc_dma); 602 sel = scb->target << 4 | SEL_ISTART | SEL_IRESELEN | SEL_WATN; 603 spifi_sendmsg(sc, SEND_IDENTIFY); 604 reg->select = sel; 605 } 606 607 void 608 spifi_sendmsg(sc, msg) 609 struct spifi_softc *sc; 610 int msg; 611 { 612 struct spifi_scb *scb = sc->sc_nexus; 613 /* struct mesh_tinfo *ti; */ 614 int lun, len, i; 615 616 int id = sc->sc_id; 617 struct spifi_reg *reg = sc->sc_reg; 618 619 DPRINTF("spifi_sendmsg: sending"); 620 sc->sc_msgout = msg; 621 len = 0; 622 623 if (msg & SEND_REJECT) { 624 DPRINTF(" REJECT"); 625 sc->sc_omsg[len++] = MSG_MESSAGE_REJECT; 626 } 627 if (msg & SEND_IDENTIFY) { 628 DPRINTF(" IDENTIFY"); 629 lun = scb->xs->xs_periph->periph_lun; 630 sc->sc_omsg[len++] = MSG_IDENTIFY(lun, 0); 631 } 632 if (msg & SEND_SDTR) { 633 DPRINTF(" SDTR"); 634 #if 0 635 ti = &sc->sc_tinfo[scb->target]; 636 sc->sc_omsg[len++] = MSG_EXTENDED; 637 sc->sc_omsg[len++] = 3; 638 sc->sc_omsg[len++] = MSG_EXT_SDTR; 639 sc->sc_omsg[len++] = ti->period; 640 sc->sc_omsg[len++] = ti->offset; 641 #endif 642 } 643 DPRINTF("\n"); 644 645 reg->cmlen = CML_AMSG_EN | len; 646 for (i = 0; i < len; i++) 647 reg->cmbuf[id].cdb[i] = sc->sc_omsg[i]; 648 } 649 void 650 spifi_command(struct spifi_softc *sc) 651 { 652 struct spifi_scb *scb = sc->sc_nexus; 653 struct spifi_reg *reg = sc->sc_reg; 654 int len = scb->cmdlen; 655 u_char *cmdp = (char *)&scb->cmd; 656 int i; 657 658 DPRINTF("spifi_command\n"); 659 660 reg->cmdpage = scb->lun_targ; 661 662 if (reg->init_status & IST_ACK) { 663 /* Negate ACK. */ 664 reg->prcmd = PRC_NJMP | PRC_CLRACK | PRC_COMMAND; 665 reg->prcmd = PRC_NJMP | PRC_COMMAND; 666 } 667 668 reg->cmlen = CML_AMSG_EN | len; 669 670 for (i = 0; i < len; i++) 671 reg->cmbuf[sc->sc_id].cdb[i] = *cmdp++; 672 673 reg->prcmd = PRC_COMMAND; 674 } 675 676 void 677 spifi_data_io(struct spifi_softc *sc) 678 { 679 struct spifi_scb *scb = sc->sc_nexus; 680 struct spifi_reg *reg = sc->sc_reg; 681 int phase; 682 683 DPRINTF("spifi_data_io\n"); 684 685 phase = reg->prstat & PRS_PHASE; 686 dmac3_reset(sc->sc_dma); 687 688 spifi_write_count(reg, scb->resid); 689 reg->cmlen = CML_AMSG_EN | 1; 690 reg->data_xfer = 0; 691 692 scb->flags |= SPIFI_DMA; 693 if (phase == SPIFI_DATAIN) { 694 if (reg->fifoctrl & FIFOC_SSTKACT) { 695 /* 696 * Clear FIFO and load the contents of synchronous 697 * stack into the FIFO. 698 */ 699 reg->fifoctrl = FIFOC_CLREVEN; 700 reg->fifoctrl = FIFOC_LOAD; 701 } 702 reg->autodata = ADATA_IN | scb->lun_targ; 703 dmac3_start(sc->sc_dma, scb->daddr, scb->resid, DMAC3_CSR_RECV); 704 reg->prcmd = PRC_DATAIN; 705 } else { 706 reg->fifoctrl = FIFOC_CLREVEN; 707 reg->autodata = scb->lun_targ; 708 dmac3_start(sc->sc_dma, scb->daddr, scb->resid, DMAC3_CSR_SEND); 709 reg->prcmd = PRC_DATAOUT; 710 } 711 } 712 713 void 714 spifi_status(struct spifi_softc *sc) 715 { 716 struct spifi_reg *reg = sc->sc_reg; 717 718 DPRINTF("spifi_status\n"); 719 spifi_fifo_drain(sc); 720 reg->cmlen = CML_AMSG_EN | 1; 721 reg->prcmd = PRC_STATUS; 722 } 723 724 int 725 spifi_done(sc) 726 struct spifi_softc *sc; 727 { 728 struct spifi_scb *scb = sc->sc_nexus; 729 struct scsipi_xfer *xs = scb->xs; 730 731 DPRINTF("spifi_done\n"); 732 733 xs->status = scb->status; 734 if (xs->status == SCSI_CHECK) { 735 DPRINTF("spifi_done: CHECK CONDITION\n"); 736 if (xs->error == XS_NOERROR) 737 xs->error = XS_BUSY; 738 } 739 740 xs->resid = scb->resid; 741 742 scsipi_done(xs); 743 spifi_free_scb(sc, scb); 744 745 sc->sc_nexus = NULL; 746 spifi_sched(sc); 747 748 return FALSE; 749 } 750 751 void 752 spifi_fifo_drain(sc) 753 struct spifi_softc *sc; 754 { 755 struct spifi_scb *scb = sc->sc_nexus; 756 struct spifi_reg *reg = sc->sc_reg; 757 int fifoctrl, fifo_count; 758 759 DPRINTF("spifi_fifo_drain\n"); 760 761 if ((scb->flags & SPIFI_READ) == 0) 762 return; 763 764 fifoctrl = reg->fifoctrl; 765 if (fifoctrl & FIFOC_SSTKACT) 766 return; 767 768 fifo_count = 8 - (fifoctrl & FIFOC_FSLOT); 769 if (fifo_count > 0 && (scb->flags & SPIFI_DMA)) { 770 /* Flush data still in FIFO. */ 771 reg->fifoctrl = FIFOC_FLUSH; 772 return; 773 } 774 775 reg->fifoctrl = FIFOC_CLREVEN; 776 } 777 778 void 779 spifi_reset(sc) 780 struct spifi_softc *sc; 781 { 782 struct spifi_reg *reg = sc->sc_reg; 783 int id = sc->sc_id; 784 785 DPRINTF("spifi_reset\n"); 786 787 reg->auxctrl = AUXCTRL_SRST; 788 reg->auxctrl = AUXCTRL_CRST; 789 790 dmac3_reset(sc->sc_dma); 791 792 reg->auxctrl = AUXCTRL_SRST; 793 reg->auxctrl = AUXCTRL_CRST; 794 reg->auxctrl = AUXCTRL_DMAEDGE; 795 796 /* Mask (only) target mode interrupts. */ 797 reg->imask = INTR_TGSEL | INTR_COMRECV; 798 799 reg->config = CONFIG_DMABURST | CONFIG_PCHKEN | CONFIG_PGENEN | id; 800 reg->fastwide = FAST_FASTEN; 801 reg->prctrl = 0; 802 reg->loopctrl = 0; 803 804 /* Enable automatic status input except the initiator. */ 805 reg->autostat = ~(1 << id); 806 807 reg->fifoctrl = FIFOC_CLREVEN; 808 spifi_write_count(reg, 0); 809 810 /* Flush write buffer. */ 811 (void)reg->spstat; 812 } 813 814 void 815 spifi_bus_reset(sc) 816 struct spifi_softc *sc; 817 { 818 struct spifi_reg *reg = sc->sc_reg; 819 820 printf("%s: bus reset\n", sc->sc_dev.dv_xname); 821 822 sc->sc_nexus = NULL; 823 824 reg->auxctrl = AUXCTRL_SETRST; 825 delay(100); 826 reg->auxctrl = 0; 827 } 828 829 #if 0 830 static u_char spifi_sync_period[] = { 831 /* 0 1 2 3 4 5 6 7 8 9 10 11 */ 832 137, 125, 112, 100, 87, 75, 62, 50, 43, 37, 31, 25 833 }; 834 835 void 836 spifi_setsync(sc, ti) 837 struct spifi_softc *sc; 838 struct spifi_tinfo *ti; 839 { 840 if ((ti->flags & T_SYNCMODE) == 0) 841 reg->data_xfer = 0; 842 else { 843 int period = ti->period; 844 int offset = ti->offset; 845 int v; 846 847 for (v = sizeof(spifi_sync_period) - 1; v >= 0; v--) 848 if (spifi_sync_period[v] >= period) 849 break; 850 if (v == -1) 851 reg->data_xfer = 0; /* XXX */ 852 else 853 reg->data_xfer = v << 4 | offset; 854 } 855 } 856 #endif 857
Indexes created Wed Oct 01 15:09:59 GMT 2025