zs_ap.c revision 1.2
1 /* $NetBSD: zs_ap.c,v 1.2 1999/12/23 06:52:30 tsubai Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/device.h> 50 #include <sys/tty.h> 51 52 #include <machine/adrsmap.h> 53 #include <machine/cpu.h> 54 #include <machine/z8530var.h> 55 56 #include <dev/cons.h> 57 #include <dev/ic/z8530reg.h> 58 59 #include <newsmips/apbus/apbusvar.h> 60 61 #include "zsc.h" /* NZSC */ 62 #define NZS NZSC 63 64 /* Make life easier for the initialized arrays here. */ 65 #if NZS < 2 66 #undef NZS 67 #define NZS 2 68 #endif 69 70 #define PORTB_XPORT 0x00000000 71 #define PORTB_RPORT 0x00010000 72 #define PORTA_XPORT 0x00020000 73 #define PORTA_RPORT 0x00030000 74 #define DMA_MODE_REG 3 75 #define DMA_ENABLE 0x01 /* DMA enable */ 76 #define DMA_DIR_DM 0x00 /* device to memory */ 77 #define DMA_DIR_MD 0x02 /* memory to device */ 78 #define DMA_EXTRDY 0x08 /* DMA external ready */ 79 #define PORTB_OFFSET 0x00040000 80 #define PORTA_OFFSET 0x00050000 81 #define PORT_CTL 2 82 #define PORTCTL_RI 0x01 83 #define PORTCTL_DSR 0x02 84 #define PORTCTL_DTR 0x04 85 #define PORT_SEL 3 86 #define PORTSEL_LOCALTALK 0x01 87 #define PORTSEL_RS232C 0x02 88 #define ESCC_REG 0x00060000 89 #define ESCCREG_INTSTAT 0 90 #define INTSTAT_SCC 0x01 91 #define ESCCREG_INTMASK 1 92 #define INTMASK_SCC 0x01 93 94 extern int zs_def_cflag; 95 extern void (*zs_delay) __P((void)); 96 97 /* 98 * The news5000 provides a 9.8304 MHz clock to the ZS chips. 99 */ 100 #define PCLK (9600 * 1024) /* PCLK pin input clock rate */ 101 102 #define ZS_DELAY() DELAY(2) 103 104 /* The layout of this is hardware-dependent (padding, order). */ 105 struct zschan { 106 volatile u_char pad1[3]; 107 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 108 volatile u_char pad2[3]; 109 volatile u_char zc_data; /* data */ 110 }; 111 112 static caddr_t zsaddr[NZS]; 113 114 /* Flags from cninit() */ 115 static int zs_hwflags[NZS][2]; 116 117 /* Default speed for all channels */ 118 static int zs_defspeed = 9600; 119 120 static u_char zs_init_reg[16] = { 121 0, /* 0: CMD (reset, etc.) */ 122 0, /* 1: No interrupts yet. */ 123 0, /* IVECT */ 124 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 125 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 126 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 127 0, /* 6: TXSYNC/SYNCLO */ 128 0, /* 7: RXSYNC/SYNCHI */ 129 0, /* 8: alias for data port */ 130 ZSWR9_MASTER_IE, 131 0, /*10: Misc. TX/RX control bits */ 132 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 133 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 134 0, /*13: BAUDHI (default=9600) */ 135 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 136 ZSWR15_BREAK_IE, 137 }; 138 139 static struct zschan * zs_get_chan_addr __P((int, int)); 140 static void zs_ap_delay __P((void)); 141 static void zshard __P((void *)); 142 static void zssoft __P((void *)); 143 static int zs_getc __P((void *)); 144 static void zs_putc __P((void *, int)); 145 int zs_get_speed __P((struct zs_chanstate *)); 146 147 struct zschan * 148 zs_get_chan_addr(zs_unit, channel) 149 int zs_unit, channel; 150 { 151 caddr_t addr; 152 struct zschan *zc; 153 154 if (zs_unit >= NZS) 155 return NULL; 156 addr = zsaddr[zs_unit]; 157 if (addr == NULL) 158 return NULL; 159 if (channel == 0) { 160 zc = (void *)(addr + PORTA_OFFSET); 161 } else { 162 zc = (void *)(addr + PORTB_OFFSET); 163 } 164 return (zc); 165 } 166 167 void 168 zs_ap_delay() 169 { 170 ZS_DELAY(); 171 } 172 173 /**************************************************************** 174 * Autoconfig 175 ****************************************************************/ 176 177 /* Definition of the driver for autoconfig. */ 178 int zs_ap_match __P((struct device *, struct cfdata *, void *)); 179 void zs_ap_attach __P((struct device *, struct device *, void *)); 180 int zs_print __P((void *, const char *name)); 181 182 struct cfattach zsc_ap_ca = { 183 sizeof(struct zsc_softc), zs_ap_match, zs_ap_attach 184 }; 185 186 extern struct cfdriver zsc_cd; 187 188 /* 189 * Is the zs chip present? 190 */ 191 int 192 zs_ap_match(parent, cf, aux) 193 struct device *parent; 194 struct cfdata *cf; 195 void *aux; 196 { 197 struct apbus_attach_args *apa = aux; 198 199 if (strcmp("esccf", apa->apa_name) != 0) 200 return 0; 201 202 return 1; 203 } 204 205 /* 206 * Attach a found zs. 207 * 208 * Match slave number to zs unit number, so that misconfiguration will 209 * not set up the keyboard as ttya, etc. 210 */ 211 void 212 zs_ap_attach(parent, self, aux) 213 struct device *parent; 214 struct device *self; 215 void *aux; 216 { 217 struct zsc_softc *zsc = (void *)self; 218 struct apbus_attach_args *apa = aux; 219 struct zsc_attach_args zsc_args; 220 volatile struct zschan *zc; 221 struct zs_chanstate *cs; 222 int s, zs_unit, channel; 223 volatile u_int *txBfifo = (void *)(apa->apa_hwbase + PORTB_XPORT); 224 volatile u_int *rxBfifo = (void *)(apa->apa_hwbase + PORTB_RPORT); 225 volatile u_int *txAfifo = (void *)(apa->apa_hwbase + PORTA_XPORT); 226 volatile u_int *rxAfifo = (void *)(apa->apa_hwbase + PORTA_RPORT); 227 volatile u_int *portBctl = (void *)(apa->apa_hwbase + PORTB_OFFSET); 228 volatile u_int *portActl = (void *)(apa->apa_hwbase + PORTA_OFFSET); 229 volatile u_int *esccregs = (void *)(apa->apa_hwbase + ESCC_REG); 230 static int didintr; 231 232 zs_unit = zsc->zsc_dev.dv_unit; 233 zsaddr[zs_unit] = (caddr_t)apa->apa_hwbase; 234 235 printf(" slot%d addr 0x%lx\n", apa->apa_slotno, apa->apa_hwbase); 236 237 txAfifo[DMA_MODE_REG] = rxAfifo[DMA_MODE_REG] = DMA_EXTRDY; 238 txBfifo[DMA_MODE_REG] = rxBfifo[DMA_MODE_REG] = DMA_EXTRDY; 239 240 /* assert DTR */ /* XXX */ 241 portBctl[PORT_CTL] = portActl[PORT_CTL] = PORTCTL_DTR; 242 243 /* select RS-232C (ch1 only) */ 244 portActl[PORT_SEL] = PORTSEL_RS232C; 245 246 /* enable SCC interrupts */ 247 esccregs[ESCCREG_INTMASK] = INTMASK_SCC; 248 249 zs_delay = zs_ap_delay; 250 251 /* 252 * Initialize software state for each channel. 253 */ 254 for (channel = 0; channel < 2; channel++) { 255 zsc_args.channel = channel; 256 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 257 cs = &zsc->zsc_cs_store[channel]; 258 zsc->zsc_cs[channel] = cs; 259 260 cs->cs_channel = channel; 261 cs->cs_private = NULL; 262 cs->cs_ops = &zsops_null; 263 cs->cs_brg_clk = PCLK / 16; 264 265 zc = zs_get_chan_addr(zs_unit, channel); 266 cs->cs_reg_csr = &zc->zc_csr; 267 cs->cs_reg_data = &zc->zc_data; 268 269 bcopy(zs_init_reg, cs->cs_creg, 16); 270 bcopy(zs_init_reg, cs->cs_preg, 16); 271 272 /* XXX: Get these from the EEPROM instead? */ 273 /* XXX: See the mvme167 code. Better. */ 274 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 275 cs->cs_defspeed = zs_get_speed(cs); 276 else 277 cs->cs_defspeed = zs_defspeed; 278 cs->cs_defcflag = zs_def_cflag; 279 280 /* Make these correspond to cs_defcflag (-crtscts) */ 281 cs->cs_rr0_dcd = ZSRR0_DCD; 282 cs->cs_rr0_cts = 0; 283 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 284 cs->cs_wr5_rts = 0; 285 286 /* 287 * Clear the master interrupt enable. 288 * The INTENA is common to both channels, 289 * so just do it on the A channel. 290 */ 291 if (channel == 0) { 292 zs_write_reg(cs, 9, 0); 293 } 294 295 /* 296 * Look for a child driver for this channel. 297 * The child attach will setup the hardware. 298 */ 299 if (!config_found(self, (void *)&zsc_args, zs_print)) { 300 /* No sub-driver. Just reset it. */ 301 u_char reset = (channel == 0) ? 302 ZSWR9_A_RESET : ZSWR9_B_RESET; 303 s = splhigh(); 304 zs_write_reg(cs, 9, reset); 305 splx(s); 306 } 307 } 308 309 /* 310 * Now safe to install interrupt handlers. Note the arguments 311 * to the interrupt handlers aren't used. Note, we only do this 312 * once since both SCCs interrupt at the same level and vector. 313 */ 314 if (!didintr) { 315 didintr = 1; 316 317 apbus_intr_establish(1, /* interrupt level ( 0 or 1 ) */ 318 NEWS5000_INT1_SCC, 319 0, /* priority */ 320 zshard, zsc, 321 apa->apa_name, apa->apa_ctlnum); 322 } 323 /* XXX; evcnt_attach() ? */ 324 325 #if 0 326 { 327 u_int x; 328 329 /* determine SCC/ESCC type */ 330 x = zs_read_reg(cs, 15); 331 zs_write_reg(cs, 15, x | ZSWR15_ENABLE_ENHANCED); 332 333 if (zs_read_reg(cs, 15) & ZSWR15_ENABLE_ENHANCED) { /* ESCC Z85230 */ 334 zs_write_reg(cs, 7, ZSWR7P_EXTEND_READ | ZSWR7P_TX_FIFO); 335 } 336 } 337 #endif 338 339 /* 340 * Set the master interrupt enable and interrupt vector. 341 * (common to both channels, do it on A) 342 */ 343 cs = zsc->zsc_cs[0]; 344 s = splhigh(); 345 /* interrupt vector */ 346 zs_write_reg(cs, 2, zs_init_reg[2]); 347 /* master interrupt control (enable) */ 348 zs_write_reg(cs, 9, zs_init_reg[9]); 349 splx(s); 350 } 351 352 static volatile int zssoftpending; 353 354 /* 355 * Our ZS chips all share a common, autovectored interrupt, 356 * so we have to look at all of them on each interrupt. 357 */ 358 static void 359 zshard(arg) 360 void *arg; 361 { 362 register struct zsc_softc *zsc; 363 register int unit, rval, softreq; 364 365 rval = softreq = 0; 366 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 367 zsc = zsc_cd.cd_devs[unit]; 368 if (zsc == NULL) 369 continue; 370 rval |= zsc_intr_hard(zsc); 371 softreq |= zsc->zsc_cs[0]->cs_softreq; 372 softreq |= zsc->zsc_cs[1]->cs_softreq; 373 } 374 375 /* We are at splzs here, so no need to lock. */ 376 if (softreq && (zssoftpending == 0)) { 377 zssoftpending = 1; 378 zssoft(arg); /*isr_soft_request(ZSSOFT_PRI);*/ 379 } 380 } 381 382 /* 383 * Similar scheme as for zshard (look at all of them) 384 */ 385 static void 386 zssoft(arg) 387 void *arg; 388 { 389 register struct zsc_softc *zsc; 390 register int s, unit; 391 392 /* This is not the only ISR on this IPL. */ 393 if (zssoftpending == 0) 394 return; 395 396 /* 397 * The soft intr. bit will be set by zshard only if 398 * the variable zssoftpending is zero. The order of 399 * these next two statements prevents our clearing 400 * the soft intr bit just after zshard has set it. 401 */ 402 /*isr_soft_clear(ZSSOFT_PRI);*/ 403 /*zssoftpending = 0;*/ 404 405 /* Make sure we call the tty layer at spltty. */ 406 s = spltty(); 407 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 408 zsc = zsc_cd.cd_devs[unit]; 409 if (zsc == NULL) 410 continue; 411 (void) zsc_intr_soft(zsc); 412 } 413 splx(s); 414 zssoftpending = 0; 415 return; 416 } 417 418 /* 419 * Polled input char. 420 */ 421 int 422 zs_getc(arg) 423 void *arg; 424 { 425 register volatile struct zschan *zc = arg; 426 register int s, c, rr0; 427 428 s = splhigh(); 429 /* Wait for a character to arrive. */ 430 do { 431 rr0 = zc->zc_csr; 432 ZS_DELAY(); 433 } while ((rr0 & ZSRR0_RX_READY) == 0); 434 435 c = zc->zc_data; 436 ZS_DELAY(); 437 splx(s); 438 439 /* 440 * This is used by the kd driver to read scan codes, 441 * so don't translate '\r' ==> '\n' here... 442 */ 443 return (c); 444 } 445 446 /* 447 * Polled output char. 448 */ 449 void 450 zs_putc(arg, c) 451 void *arg; 452 int c; 453 { 454 register volatile struct zschan *zc = arg; 455 register int s, rr0; 456 457 s = splhigh(); 458 /* Wait for transmitter to become ready. */ 459 do { 460 rr0 = zc->zc_csr; 461 ZS_DELAY(); 462 } while ((rr0 & ZSRR0_TX_READY) == 0); 463 464 zc->zc_data = c; 465 ZS_DELAY(); 466 splx(s); 467 } 468 469 /*****************************************************************/ 470 471 static void zscnprobe __P((struct consdev *)); 472 static void zscninit __P((struct consdev *)); 473 static int zscngetc __P((dev_t)); 474 static void zscnputc __P((dev_t, int)); 475 static void zscnpollc __P((dev_t, int)); 476 477 struct consdev consdev_zs_ap = { 478 zscnprobe, 479 zscninit, 480 zscngetc, 481 zscnputc, 482 zscnpollc 483 }; 484 485 void 486 zscnprobe(cn) 487 struct consdev *cn; 488 { 489 } 490 491 void 492 zscninit(cn) 493 struct consdev *cn; 494 { 495 cn->cn_dev = makedev(zs_major, 0); 496 cn->cn_pri = CN_REMOTE; 497 zs_hwflags[0][0] = ZS_HWFLAG_CONSOLE; 498 } 499 500 int 501 zscngetc(dev) 502 dev_t dev; 503 { 504 return zs_getc((void *)NEWS5000_SCCPORT0A); 505 } 506 507 void 508 zscnputc(dev, c) 509 dev_t dev; 510 int c; 511 { 512 zs_putc((void *)NEWS5000_SCCPORT0A, c); 513 } 514 515 void 516 zscnpollc(dev, on) 517 dev_t dev; 518 int on; 519 { 520 } 521
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