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zs_ap.c revision 1.32 
      1 /*	$NetBSD: zs_ap.c,v 1.32 2021/08/07 16:19:01 thorpej Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1996 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Gordon W. Ross.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * Zilog Z8530 Dual UART driver (machine-dependent part)
     34  *
     35  * Runs two serial lines per chip using slave drivers.
     36  * Plain tty/async lines use the zs_async slave.
     37  * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves.
     38  */
     39 
     40 #include <sys/cdefs.h>
     41 __KERNEL_RCSID(0, "$NetBSD: zs_ap.c,v 1.32 2021/08/07 16:19:01 thorpej Exp $");
     42 
     43 #include <sys/param.h>
     44 #include <sys/systm.h>
     45 #include <sys/device.h>
     46 #include <sys/tty.h>
     47 #include <sys/conf.h>
     48 #include <sys/cpu.h>
     49 #include <sys/intr.h>
     50 #ifdef NEWS4000_ZS_AP_POLLING
     51 #include <sys/callout.h>
     52 #endif
     53 
     54 #include <machine/adrsmap.h>
     55 #include <machine/z8530var.h>
     56 
     57 #include <dev/cons.h>
     58 #include <dev/ic/z8530reg.h>
     59 
     60 #include <newsmips/apbus/apbusvar.h>
     61 
     62 #include "zsc.h"	/* NZSC */
     63 #define NZS NZSC
     64 
     65 /* Make life easier for the initialized arrays here. */
     66 #if NZS < 2
     67 #undef  NZS
     68 #define NZS 2
     69 #endif
     70 
     71 #define NEWS5000_PORTB_TXPORT	0x00000000
     72 #define NEWS5000_PORTB_RXPORT	0x00010000
     73 #define NEWS5000_PORTA_TXPORT	0x00020000
     74 #define NEWS5000_PORTA_RXPORT	0x00030000
     75 #define   NEWS5000_DMA_MODE_REG		3
     76 #define     NEWS5000_DMA_ENABLE		0x01	/* DMA enable */
     77 #define     NEWS5000_DMA_DIR_DM		0x00	/* device to memory */
     78 #define     NEWS5000_DMA_DIR_MD		0x02	/* memory to device */
     79 #define     NEWS5000_DMA_EXTRDY		0x08	/* DMA external ready */
     80 #define NEWS5000_PORTB_OFFSET	0x00040000
     81 #define NEWS5000_PORTA_OFFSET	0x00050000
     82 #define   NEWS5000_PORT_CTL		2
     83 #define     NEWS5000_PORTCTL_RI		0x01
     84 #define     NEWS5000_PORTCTL_DSR	0x02
     85 #define     NEWS5000_PORTCTL_DTR	0x04
     86 #define   NEWS5000_PORT_SEL		3
     87 #define     NEWS5000_PORTSEL_LOCALTALK	0x01
     88 #define     NEWS5000_PORTSEL_RS232C	0x02
     89 #define NEWS5000_ESCC_REG	0x00060000
     90 #define   NEWS5000_ESCCREG_INTSTAT	0
     91 #define     NEWS5000_INTSTAT_SCC	0x01
     92 #define   NEWS5000_ESCCREG_INTMASK	1
     93 #define     NEWS5000_INTMASK_SCC	0x01
     94 
     95 #define NEWS4000_PORTB_TXPORT	0x00000000	/* XXX: not confirmed */
     96 #define NEWS4000_PORTB_RXPORT	0x00010000	/* XXX: not confirmed */
     97 #define NEWS4000_PORTA_TXPORT	0x00040000	/* XXX: not confirmed */
     98 #define NEWS4000_PORTA_RXPORT	0x00050000	/* XXX: not confirmed */
     99 #define   NEWS4000_DMA_MODE_REG		3
    100 #define     NEWS4000_DMA_ENABLE		0x01	/* DMA enable */
    101 #define     NEWS4000_DMA_DIR_DM		0x00	/* device to memory */
    102 #define     NEWS4000_DMA_DIR_MD		0x02	/* memory to device */
    103 #define     NEWS4000_DMA_EXTRDY		0x08	/* DMA external ready */
    104 #define NEWS4000_PORTB_CTL	0x00020000	/* XXX: not confirmed */
    105 #define NEWS4000_PORTA_CTL	0x00060000	/* XXX: not confirmed */
    106 #define   NEWS4000_PORT_CTL		4
    107 #define     NEWS4000_PORTCTL_RI		0x01
    108 #define     NEWS4000_PORTCTL_DSR	0x02
    109 #define     NEWS4000_PORTCTL_DTR	0x04
    110 #define   NEWS4000_PORT_SEL		5
    111 #define     NEWS4000_PORTSEL_LOCALTALK	0x01
    112 #define     NEWS4000_PORTSEL_RS232C	0x02
    113 #define NEWS4000_ESCC_REG	0x00060000	/* XXX:  not confirmed */
    114 #define   NEWS4000_ESCCREG_INTSTAT	0
    115 #define     NEWS4000_INTSTAT_SCC	0x01
    116 #define   NEWS4000_ESCCREG_INTMASK	1
    117 #define     NEWS4000_INTMASK_SCC	0x01
    118 #define NEWS4000_PORTB_OFFSET	0x00080000
    119 #define NEWS4000_PORTA_OFFSET	0x00080008
    120 
    121 extern int zs_def_cflag;
    122 extern void (*zs_delay)(void);
    123 
    124 /*
    125  * The news5000 provides a 9.8304 MHz clock to the ZS chips.
    126  */
    127 #define PCLK	(9600 * 1024)	/* PCLK pin input clock rate */
    128 
    129 #define ZS_DELAY()	DELAY(2)
    130 
    131 /* The layout of this is hardware-dependent (padding, order). */
    132 struct zschan {
    133 	volatile uint8_t pad1[3];
    134 	volatile uint8_t zc_csr;	/* ctrl,status, and indirect access */
    135 	volatile uint8_t pad2[3];
    136 	volatile uint8_t zc_data;	/* data */
    137 };
    138 
    139 static void *zsaddr[NZS];
    140 
    141 /* Default speed for all channels */
    142 static int zs_defspeed = 9600;
    143 
    144 /* console status from cninit */
    145 static struct zs_chanstate zs_ap_conschan_store;
    146 static struct zs_chanstate *zs_ap_conschan;
    147 static struct zschan *zc_ap_cons;
    148 
    149 static uint8_t zs_init_reg[16] = {
    150 	0,	/* 0: CMD (reset, etc.) */
    151 	0,	/* 1: No interrupts yet. */
    152 	0,	/* IVECT */
    153 	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
    154 	ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
    155 	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
    156 	0,	/* 6: TXSYNC/SYNCLO */
    157 	0,	/* 7: RXSYNC/SYNCHI */
    158 	0,	/* 8: alias for data port */
    159 	ZSWR9_MASTER_IE,
    160 	0,	/*10: Misc. TX/RX control bits */
    161 	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
    162 	BPS_TO_TCONST(PCLK/16,9600),	/*12: BAUDLO (default=9600) */
    163 	0,			/*13: BAUDHI (default=9600) */
    164 	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
    165 	ZSWR15_BREAK_IE,
    166 };
    167 
    168 #ifdef NEWS4000_ZS_AP_POLLING
    169 static struct callout zscallout;
    170 #endif
    171 
    172 static struct zschan * zs_get_chan_addr(int, int);
    173 static void zs_ap_delay(void);
    174 static int zshard_ap(void *);
    175 static int zs_getc(void *);
    176 static void zs_putc(void *, int);
    177 
    178 struct zschan *
    179 zs_get_chan_addr(int zs_unit, int channel)
    180 {
    181 	void *addr;
    182 	struct zschan *zc = NULL;
    183 
    184 	if (zs_unit >= NZS)
    185 		return NULL;
    186 	addr = zsaddr[zs_unit];
    187 	if (addr == NULL)
    188 		return NULL;
    189 	if (systype == NEWS5000) {
    190 		if (channel == 0) {
    191 			zc = (void *)((uint8_t *)addr + NEWS5000_PORTA_OFFSET);
    192 		} else {
    193 			zc = (void *)((uint8_t *)addr + NEWS5000_PORTB_OFFSET);
    194 		}
    195 	}
    196 	if (systype == NEWS4000) {
    197 		if (channel == 0) {
    198 			zc = (void *)((uint8_t *)addr + NEWS4000_PORTA_OFFSET);
    199 		} else {
    200 			zc = (void *)((uint8_t *)addr + NEWS4000_PORTB_OFFSET);
    201 		}
    202 	}
    203 	return zc;
    204 }
    205 
    206 void
    207 zs_ap_delay(void)
    208 {
    209 
    210 	ZS_DELAY();
    211 }
    212 
    213 /****************************************************************
    214  * Autoconfig
    215  ****************************************************************/
    216 
    217 /* Definition of the driver for autoconfig. */
    218 int zs_ap_match(device_t, cfdata_t, void *);
    219 void zs_ap_attach(device_t, device_t, void *);
    220 
    221 CFATTACH_DECL_NEW(zsc_ap, sizeof(struct zsc_softc),
    222     zs_ap_match, zs_ap_attach, NULL, NULL);
    223 
    224 /*
    225  * Is the zs chip present?
    226  */
    227 int
    228 zs_ap_match(device_t parent, cfdata_t cf, void *aux)
    229 {
    230 	struct apbus_attach_args *apa = aux;
    231 
    232 	if (strcmp("esccf", apa->apa_name) == 0 ||
    233 	    strcmp("esccg", apa->apa_name) == 0)
    234 		return 1;
    235 
    236 	return 0;
    237 }
    238 
    239 /*
    240  * Attach a found zs.
    241  *
    242  * Match slave number to zs unit number, so that misconfiguration will
    243  * not set up the keyboard as ttya, etc.
    244  */
    245 void
    246 zs_ap_attach(device_t parent, device_t self, void *aux)
    247 {
    248 	struct zsc_softc *zsc = device_private(self);
    249 	struct apbus_attach_args *apa = aux;
    250 	struct zsc_attach_args zsc_args;
    251 	volatile struct zschan *zc;
    252 	struct zs_chanstate *cs;
    253 	int s, zs_unit, channel;
    254 	volatile uint32_t *txBfifo;
    255 	volatile uint32_t *rxBfifo;
    256 	volatile uint32_t *txAfifo;
    257 	volatile uint32_t *rxAfifo;
    258 	volatile uint32_t *portBctl;
    259 	volatile uint32_t *portActl;
    260 	volatile uint32_t *esccregs;
    261 
    262 	zsc->zsc_dev = self;
    263 	zs_unit = device_unit(self);
    264 	zsaddr[zs_unit] = (void *)apa->apa_hwbase;
    265 
    266 	aprint_normal(" slot%d addr 0x%lx\n", apa->apa_slotno, apa->apa_hwbase);
    267 
    268 	/* XXX: appease gcc -Wuninitialized */
    269 	txBfifo  = (void *)(apa->apa_hwbase);
    270 	rxBfifo  = (void *)(apa->apa_hwbase);
    271 	txAfifo  = (void *)(apa->apa_hwbase);
    272 	rxAfifo  = (void *)(apa->apa_hwbase);
    273 	portBctl = (void *)(apa->apa_hwbase);
    274 	portActl = (void *)(apa->apa_hwbase);
    275 	esccregs = (void *)(apa->apa_hwbase);
    276 
    277 	if (systype == NEWS5000) {
    278 		txBfifo  = (void *)(apa->apa_hwbase + NEWS5000_PORTB_TXPORT);
    279 		rxBfifo  = (void *)(apa->apa_hwbase + NEWS5000_PORTB_RXPORT);
    280 		txAfifo  = (void *)(apa->apa_hwbase + NEWS5000_PORTA_TXPORT);
    281 		rxAfifo  = (void *)(apa->apa_hwbase + NEWS5000_PORTA_RXPORT);
    282 		portBctl = (void *)(apa->apa_hwbase + NEWS5000_PORTB_OFFSET);
    283 		portActl = (void *)(apa->apa_hwbase + NEWS5000_PORTA_OFFSET);
    284 		esccregs = (void *)(apa->apa_hwbase + NEWS5000_ESCC_REG);
    285 	}
    286 	if (systype == NEWS4000) {
    287 		txBfifo  = (void *)(apa->apa_hwbase + NEWS4000_PORTB_TXPORT);
    288 		rxBfifo  = (void *)(apa->apa_hwbase + NEWS4000_PORTB_RXPORT);
    289 		txAfifo  = (void *)(apa->apa_hwbase + NEWS4000_PORTA_TXPORT);
    290 		rxAfifo  = (void *)(apa->apa_hwbase + NEWS4000_PORTA_RXPORT);
    291 		portBctl = (void *)(apa->apa_hwbase + NEWS4000_PORTB_CTL);
    292 		portActl = (void *)(apa->apa_hwbase + NEWS4000_PORTA_CTL);
    293 		esccregs = (void *)(apa->apa_hwbase + NEWS4000_ESCC_REG);
    294 	}
    295 
    296 	if (systype == NEWS5000) {
    297 		txAfifo[NEWS5000_DMA_MODE_REG] = NEWS5000_DMA_EXTRDY;
    298 		rxAfifo[NEWS5000_DMA_MODE_REG] = NEWS5000_DMA_EXTRDY;
    299 		txBfifo[NEWS5000_DMA_MODE_REG] = NEWS5000_DMA_EXTRDY;
    300 		rxBfifo[NEWS5000_DMA_MODE_REG] = NEWS5000_DMA_EXTRDY;
    301 
    302 		/* assert DTR */			/* XXX */
    303 		portBctl[NEWS5000_PORT_CTL] = NEWS5000_PORTCTL_DTR;
    304 		portActl[NEWS5000_PORT_CTL] = NEWS5000_PORTCTL_DTR;
    305 
    306 		/* select RS-232C (ch1 only) */
    307 		portActl[NEWS5000_PORT_SEL] = NEWS5000_PORTSEL_RS232C;
    308 
    309 		/* enable SCC interrupts */
    310 		esccregs[NEWS5000_ESCCREG_INTMASK] = NEWS5000_INTMASK_SCC;
    311 	}
    312 
    313 	if (systype == NEWS4000) {
    314 		txAfifo[NEWS4000_DMA_MODE_REG] = NEWS4000_DMA_EXTRDY;
    315 		rxAfifo[NEWS4000_DMA_MODE_REG] = NEWS4000_DMA_EXTRDY;
    316 		txBfifo[NEWS4000_DMA_MODE_REG] = NEWS4000_DMA_EXTRDY;
    317 		rxBfifo[NEWS4000_DMA_MODE_REG] = NEWS4000_DMA_EXTRDY;
    318 
    319 #if 1	/* XXX: zsc on news4000 seems mangled by these ops */
    320 		/* assert DTR */			/* XXX */
    321 		portBctl[NEWS4000_PORT_CTL] = NEWS4000_PORTCTL_DTR;
    322 		portActl[NEWS4000_PORT_CTL] = NEWS4000_PORTCTL_DTR;
    323 
    324 		/* select RS-232C (ch1 only) */
    325 		portActl[NEWS4000_PORT_SEL] = NEWS4000_PORTSEL_RS232C;
    326 #endif
    327 
    328 		/* enable SCC interrupts */
    329 		esccregs[NEWS4000_ESCCREG_INTMASK] = NEWS4000_INTMASK_SCC;
    330 	}
    331 
    332 	zs_delay = zs_ap_delay;
    333 
    334 	/*
    335 	 * Initialize software state for each channel.
    336 	 */
    337 	for (channel = 0; channel < 2; channel++) {
    338 		zsc_args.channel = channel;
    339 		cs = &zsc->zsc_cs_store[channel];
    340 		zsc->zsc_cs[channel] = cs;
    341 
    342 		zs_lock_init(cs);
    343 		cs->cs_channel = channel;
    344 		cs->cs_private = NULL;
    345 		cs->cs_ops = &zsops_null;
    346 		cs->cs_brg_clk = PCLK / 16;
    347 
    348 		zc = zs_get_chan_addr(zs_unit, channel);
    349 
    350 		if (zc == zc_ap_cons) {
    351 			memcpy(cs, zs_ap_conschan, sizeof(struct zs_chanstate));
    352 			zs_ap_conschan = cs;
    353 			zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
    354 		} else {
    355 			cs->cs_reg_csr  = &zc->zc_csr;
    356 			cs->cs_reg_data = &zc->zc_data;
    357 			memcpy(cs->cs_creg, zs_init_reg, 16);
    358 			memcpy(cs->cs_preg, zs_init_reg, 16);
    359 			cs->cs_defspeed = zs_defspeed;
    360 			zsc_args.hwflags = 0;
    361 		}
    362 		cs->cs_defcflag = zs_def_cflag;
    363 
    364 		/* Make these correspond to cs_defcflag (-crtscts) */
    365 		cs->cs_rr0_dcd = ZSRR0_DCD;
    366 		cs->cs_rr0_cts = 0;
    367 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
    368 		cs->cs_wr5_rts = 0;
    369 
    370 		/*
    371 		 * Clear the master interrupt enable.
    372 		 * The INTENA is common to both channels,
    373 		 * so just do it on the A channel.
    374 		 */
    375 		if (channel == 0) {
    376 			zs_write_reg(cs, 9, 0);
    377 		}
    378 
    379 		/*
    380 		 * Look for a child driver for this channel.
    381 		 * The child attach will setup the hardware.
    382 		 */
    383 		if (!config_found(self, (void *)&zsc_args, zs_print,
    384 		    CFARGS_NONE)) {
    385 			/* No sub-driver.  Just reset it. */
    386 			uint8_t reset = (channel == 0) ?
    387 			    ZSWR9_A_RESET : ZSWR9_B_RESET;
    388 			s = splhigh();
    389 			zs_write_reg(cs, 9, reset);
    390 			splx(s);
    391 		}
    392 	}
    393 
    394 	/*
    395 	 * Now safe to install interrupt handlers.
    396 	 */
    397 	zsc->zsc_si = softint_establish(SOFTINT_SERIAL,
    398 	    (void (*)(void *))zsc_intr_soft, zsc);
    399 	if (systype == NEWS5000) {
    400 		apbus_intr_establish(1, /* interrupt level ( 0 or 1 ) */
    401 				     NEWS5000_INT1_SCC,
    402 				     0, /* priority */
    403 				     zshard_ap, zsc,
    404 				     device_xname(self), apa->apa_ctlnum);
    405 	}
    406 	if (systype == NEWS4000) {
    407 		apbus_intr_establish(1, /* interrupt level ( 0 or 1 ) */
    408 				     0x0200,
    409 				     0, /* priority */
    410 				     zshard_ap, zsc,
    411 				     device_xname(self), apa->apa_ctlnum);
    412 #ifdef NEWS4000_ZS_AP_POLLING
    413 		/* XXX: no info how to enable zs ap interrupt for now */
    414 		callout_init(&zscallout, 0);
    415 		callout_reset(&zscallout, 1,
    416 		    (void (*)(void *))zshard_ap, (void *)zsc);
    417 #endif
    418 	}
    419 	/* XXX; evcnt_attach() ? */
    420 
    421 #if 0
    422 {
    423 	u_int x;
    424 
    425 	/* determine SCC/ESCC type */
    426 	x = zs_read_reg(cs, 15);
    427 	zs_write_reg(cs, 15, x | ZSWR15_ENABLE_ENHANCED);
    428 
    429 	if (zs_read_reg(cs, 15) & ZSWR15_ENABLE_ENHANCED) { /* ESCC Z85230 */
    430 		zs_write_reg(cs, 7, ZSWR7P_EXTEND_READ | ZSWR7P_TX_FIFO);
    431 	}
    432 }
    433 #endif
    434 
    435 	/*
    436 	 * Set the master interrupt enable and interrupt vector.
    437 	 * (common to both channels, do it on A)
    438 	 */
    439 	cs = zsc->zsc_cs[0];
    440 	s = splhigh();
    441 	/* interrupt vector */
    442 	zs_write_reg(cs, 2, zs_init_reg[2]);
    443 	/* master interrupt control (enable) */
    444 	zs_write_reg(cs, 9, zs_init_reg[9]);
    445 	splx(s);
    446 }
    447 
    448 static int
    449 zshard_ap(void *arg)
    450 {
    451 
    452 	zshard(arg);
    453 #ifdef NEWS4000_ZS_AP_POLLING
    454 	if (systype == NEWS4000) {
    455 		callout_schedule(&zscallout, 1);
    456 	}
    457 #endif
    458 	return 1;
    459 }
    460 
    461 /*
    462  * Polled input char.
    463  */
    464 int
    465 zs_getc(void *arg)
    466 {
    467 	volatile struct zschan *zc = arg;
    468 	int s, c;
    469 	uint8_t rr0;
    470 
    471 	s = splhigh();
    472 	/* Wait for a character to arrive. */
    473 	do {
    474 		rr0 = zc->zc_csr;
    475 		ZS_DELAY();
    476 	} while ((rr0 & ZSRR0_RX_READY) == 0);
    477 
    478 	c = zc->zc_data;
    479 	ZS_DELAY();
    480 	splx(s);
    481 
    482 	/*
    483 	 * This is used by the kd driver to read scan codes,
    484 	 * so don't translate '\r' ==> '\n' here...
    485 	 */
    486 	return c;
    487 }
    488 
    489 /*
    490  * Polled output char.
    491  */
    492 void
    493 zs_putc(void *arg, int c)
    494 {
    495 	volatile struct zschan *zc = arg;
    496 	int s;
    497 	uint8_t rr0;
    498 
    499 	s = splhigh();
    500 	/* Wait for transmitter to become ready. */
    501 	do {
    502 		rr0 = zc->zc_csr;
    503 		ZS_DELAY();
    504 	} while ((rr0 & ZSRR0_TX_READY) == 0);
    505 
    506 	zc->zc_data = c;
    507 	ZS_DELAY();
    508 	splx(s);
    509 }
    510 
    511 /*****************************************************************/
    512 
    513 static void zscnprobe(struct consdev *);
    514 static void zscninit(struct consdev *);
    515 static int  zscngetc(dev_t);
    516 static void zscnputc(dev_t, int);
    517 
    518 struct consdev consdev_zs_ap = {
    519 	zscnprobe,
    520 	zscninit,
    521 	zscngetc,
    522 	zscnputc,
    523 	nullcnpollc,
    524 	NULL,
    525 	NULL,
    526 	NULL,
    527 	NODEV,
    528 	CN_DEAD
    529 };
    530 
    531 static void
    532 zscnprobe(struct consdev *cn)
    533 {
    534 }
    535 
    536 static void
    537 zscninit(struct consdev *cn)
    538 {
    539 	extern const struct cdevsw zstty_cdevsw;
    540 	struct zs_chanstate *cs;
    541 	u_int tconst;
    542 
    543 	/* Wait a while for PROM console output to complete */
    544 	DELAY(20000);
    545 
    546 	cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0);
    547 	cn->cn_pri = CN_REMOTE;
    548 
    549 	zc_ap_cons = sccport0a;
    550 	zs_delay = zs_ap_delay;
    551 
    552 	zs_ap_conschan = cs = &zs_ap_conschan_store;
    553 
    554 	/* Setup temporary chanstate. */
    555 	cs->cs_reg_csr  = &zc_ap_cons->zc_csr;
    556 	cs->cs_reg_data = &zc_ap_cons->zc_data;
    557 
    558 	/* Initialize the pending registers. */
    559 	memcpy(cs->cs_preg, zs_init_reg, 16);
    560 	cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
    561 
    562 	cs->cs_brg_clk = PCLK / 16;
    563 	cs->cs_defspeed = 9600;	/* PROM use 9600 bps */
    564 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, cs->cs_defspeed);
    565 	cs->cs_preg[12] = tconst;
    566 	cs->cs_preg[13] = tconst >> 8;
    567 
    568 	/* Clear the master interrupt enable. */
    569 	zs_write_reg(cs, 9, 0);
    570 
    571 	/* Reset the whole SCC chip. */
    572 	zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
    573 
    574 	/* Copy "pending" to "current" and H/W */
    575 	zs_loadchannelregs(cs);
    576 }
    577 
    578 static int
    579 zscngetc(dev_t dev)
    580 {
    581 
    582 	return zs_getc(sccport0a);
    583 }
    584 
    585 static void
    586 zscnputc(dev_t dev, int c)
    587 {
    588 
    589 	zs_putc(sccport0a, c);
    590 }
    591