zs_ap.c revision 1.8
1 /* $NetBSD: zs_ap.c,v 1.8 2002/10/02 04:27:51 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/device.h> 50 #include <sys/tty.h> 51 #include <sys/conf.h> 52 53 #include <machine/adrsmap.h> 54 #include <machine/cpu.h> 55 #include <machine/z8530var.h> 56 57 #include <dev/cons.h> 58 #include <dev/ic/z8530reg.h> 59 60 #include <newsmips/apbus/apbusvar.h> 61 62 #include "zsc.h" /* NZSC */ 63 #define NZS NZSC 64 65 /* Make life easier for the initialized arrays here. */ 66 #if NZS < 2 67 #undef NZS 68 #define NZS 2 69 #endif 70 71 #define PORTB_XPORT 0x00000000 72 #define PORTB_RPORT 0x00010000 73 #define PORTA_XPORT 0x00020000 74 #define PORTA_RPORT 0x00030000 75 #define DMA_MODE_REG 3 76 #define DMA_ENABLE 0x01 /* DMA enable */ 77 #define DMA_DIR_DM 0x00 /* device to memory */ 78 #define DMA_DIR_MD 0x02 /* memory to device */ 79 #define DMA_EXTRDY 0x08 /* DMA external ready */ 80 #define PORTB_OFFSET 0x00040000 81 #define PORTA_OFFSET 0x00050000 82 #define PORT_CTL 2 83 #define PORTCTL_RI 0x01 84 #define PORTCTL_DSR 0x02 85 #define PORTCTL_DTR 0x04 86 #define PORT_SEL 3 87 #define PORTSEL_LOCALTALK 0x01 88 #define PORTSEL_RS232C 0x02 89 #define ESCC_REG 0x00060000 90 #define ESCCREG_INTSTAT 0 91 #define INTSTAT_SCC 0x01 92 #define ESCCREG_INTMASK 1 93 #define INTMASK_SCC 0x01 94 95 extern int zs_def_cflag; 96 extern void (*zs_delay) __P((void)); 97 98 /* 99 * The news5000 provides a 9.8304 MHz clock to the ZS chips. 100 */ 101 #define PCLK (9600 * 1024) /* PCLK pin input clock rate */ 102 103 #define ZS_DELAY() DELAY(2) 104 105 /* The layout of this is hardware-dependent (padding, order). */ 106 struct zschan { 107 volatile u_char pad1[3]; 108 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 109 volatile u_char pad2[3]; 110 volatile u_char zc_data; /* data */ 111 }; 112 113 static caddr_t zsaddr[NZS]; 114 115 /* Flags from cninit() */ 116 static int zs_hwflags[NZS][2]; 117 118 /* Default speed for all channels */ 119 static int zs_defspeed = 9600; 120 121 static u_char zs_init_reg[16] = { 122 0, /* 0: CMD (reset, etc.) */ 123 0, /* 1: No interrupts yet. */ 124 0, /* IVECT */ 125 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 126 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 127 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 128 0, /* 6: TXSYNC/SYNCLO */ 129 0, /* 7: RXSYNC/SYNCHI */ 130 0, /* 8: alias for data port */ 131 ZSWR9_MASTER_IE, 132 0, /*10: Misc. TX/RX control bits */ 133 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 134 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 135 0, /*13: BAUDHI (default=9600) */ 136 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 137 ZSWR15_BREAK_IE, 138 }; 139 140 static struct zschan * zs_get_chan_addr __P((int, int)); 141 static void zs_ap_delay __P((void)); 142 static int zshard_ap __P((void *)); 143 static int zs_getc __P((void *)); 144 static void zs_putc __P((void *, int)); 145 int zshard __P((void *)); 146 int zs_get_speed __P((struct zs_chanstate *)); 147 148 struct zschan * 149 zs_get_chan_addr(zs_unit, channel) 150 int zs_unit, channel; 151 { 152 caddr_t addr; 153 struct zschan *zc; 154 155 if (zs_unit >= NZS) 156 return NULL; 157 addr = zsaddr[zs_unit]; 158 if (addr == NULL) 159 return NULL; 160 if (channel == 0) { 161 zc = (void *)(addr + PORTA_OFFSET); 162 } else { 163 zc = (void *)(addr + PORTB_OFFSET); 164 } 165 return (zc); 166 } 167 168 void 169 zs_ap_delay() 170 { 171 ZS_DELAY(); 172 } 173 174 /**************************************************************** 175 * Autoconfig 176 ****************************************************************/ 177 178 /* Definition of the driver for autoconfig. */ 179 int zs_ap_match __P((struct device *, struct cfdata *, void *)); 180 void zs_ap_attach __P((struct device *, struct device *, void *)); 181 int zs_print __P((void *, const char *name)); 182 183 CFATTACH_DECL(zsc_ap, sizeof(struct zsc_softc), 184 zs_ap_match, zs_ap_attach, NULL, NULL); 185 186 /* 187 * Is the zs chip present? 188 */ 189 int 190 zs_ap_match(parent, cf, aux) 191 struct device *parent; 192 struct cfdata *cf; 193 void *aux; 194 { 195 struct apbus_attach_args *apa = aux; 196 197 if (strcmp("esccf", apa->apa_name) != 0) 198 return 0; 199 200 return 1; 201 } 202 203 /* 204 * Attach a found zs. 205 * 206 * Match slave number to zs unit number, so that misconfiguration will 207 * not set up the keyboard as ttya, etc. 208 */ 209 void 210 zs_ap_attach(parent, self, aux) 211 struct device *parent; 212 struct device *self; 213 void *aux; 214 { 215 struct zsc_softc *zsc = (void *)self; 216 struct apbus_attach_args *apa = aux; 217 struct zsc_attach_args zsc_args; 218 volatile struct zschan *zc; 219 struct zs_chanstate *cs; 220 int s, zs_unit, channel; 221 volatile u_int *txBfifo = (void *)(apa->apa_hwbase + PORTB_XPORT); 222 volatile u_int *rxBfifo = (void *)(apa->apa_hwbase + PORTB_RPORT); 223 volatile u_int *txAfifo = (void *)(apa->apa_hwbase + PORTA_XPORT); 224 volatile u_int *rxAfifo = (void *)(apa->apa_hwbase + PORTA_RPORT); 225 volatile u_int *portBctl = (void *)(apa->apa_hwbase + PORTB_OFFSET); 226 volatile u_int *portActl = (void *)(apa->apa_hwbase + PORTA_OFFSET); 227 volatile u_int *esccregs = (void *)(apa->apa_hwbase + ESCC_REG); 228 static int didintr; 229 230 zs_unit = zsc->zsc_dev.dv_unit; 231 zsaddr[zs_unit] = (caddr_t)apa->apa_hwbase; 232 233 printf(" slot%d addr 0x%lx\n", apa->apa_slotno, apa->apa_hwbase); 234 235 txAfifo[DMA_MODE_REG] = rxAfifo[DMA_MODE_REG] = DMA_EXTRDY; 236 txBfifo[DMA_MODE_REG] = rxBfifo[DMA_MODE_REG] = DMA_EXTRDY; 237 238 /* assert DTR */ /* XXX */ 239 portBctl[PORT_CTL] = portActl[PORT_CTL] = PORTCTL_DTR; 240 241 /* select RS-232C (ch1 only) */ 242 portActl[PORT_SEL] = PORTSEL_RS232C; 243 244 /* enable SCC interrupts */ 245 esccregs[ESCCREG_INTMASK] = INTMASK_SCC; 246 247 zs_delay = zs_ap_delay; 248 249 /* 250 * Initialize software state for each channel. 251 */ 252 for (channel = 0; channel < 2; channel++) { 253 zsc_args.channel = channel; 254 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 255 cs = &zsc->zsc_cs_store[channel]; 256 zsc->zsc_cs[channel] = cs; 257 258 cs->cs_channel = channel; 259 cs->cs_private = NULL; 260 cs->cs_ops = &zsops_null; 261 cs->cs_brg_clk = PCLK / 16; 262 263 zc = zs_get_chan_addr(zs_unit, channel); 264 cs->cs_reg_csr = &zc->zc_csr; 265 cs->cs_reg_data = &zc->zc_data; 266 267 bcopy(zs_init_reg, cs->cs_creg, 16); 268 bcopy(zs_init_reg, cs->cs_preg, 16); 269 270 /* XXX: Get these from the EEPROM instead? */ 271 /* XXX: See the mvme167 code. Better. */ 272 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 273 cs->cs_defspeed = zs_get_speed(cs); 274 else 275 cs->cs_defspeed = zs_defspeed; 276 cs->cs_defcflag = zs_def_cflag; 277 278 /* Make these correspond to cs_defcflag (-crtscts) */ 279 cs->cs_rr0_dcd = ZSRR0_DCD; 280 cs->cs_rr0_cts = 0; 281 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 282 cs->cs_wr5_rts = 0; 283 284 /* 285 * Clear the master interrupt enable. 286 * The INTENA is common to both channels, 287 * so just do it on the A channel. 288 */ 289 if (channel == 0) { 290 zs_write_reg(cs, 9, 0); 291 } 292 293 /* 294 * Look for a child driver for this channel. 295 * The child attach will setup the hardware. 296 */ 297 if (!config_found(self, (void *)&zsc_args, zs_print)) { 298 /* No sub-driver. Just reset it. */ 299 u_char reset = (channel == 0) ? 300 ZSWR9_A_RESET : ZSWR9_B_RESET; 301 s = splhigh(); 302 zs_write_reg(cs, 9, reset); 303 splx(s); 304 } 305 } 306 307 /* 308 * Now safe to install interrupt handlers. Note the arguments 309 * to the interrupt handlers aren't used. Note, we only do this 310 * once since both SCCs interrupt at the same level and vector. 311 */ 312 if (!didintr) { 313 didintr = 1; 314 315 apbus_intr_establish(1, /* interrupt level ( 0 or 1 ) */ 316 NEWS5000_INT1_SCC, 317 0, /* priority */ 318 zshard_ap, zsc, 319 apa->apa_name, apa->apa_ctlnum); 320 } 321 /* XXX; evcnt_attach() ? */ 322 323 #if 0 324 { 325 u_int x; 326 327 /* determine SCC/ESCC type */ 328 x = zs_read_reg(cs, 15); 329 zs_write_reg(cs, 15, x | ZSWR15_ENABLE_ENHANCED); 330 331 if (zs_read_reg(cs, 15) & ZSWR15_ENABLE_ENHANCED) { /* ESCC Z85230 */ 332 zs_write_reg(cs, 7, ZSWR7P_EXTEND_READ | ZSWR7P_TX_FIFO); 333 } 334 } 335 #endif 336 337 /* 338 * Set the master interrupt enable and interrupt vector. 339 * (common to both channels, do it on A) 340 */ 341 cs = zsc->zsc_cs[0]; 342 s = splhigh(); 343 /* interrupt vector */ 344 zs_write_reg(cs, 2, zs_init_reg[2]); 345 /* master interrupt control (enable) */ 346 zs_write_reg(cs, 9, zs_init_reg[9]); 347 splx(s); 348 } 349 350 /* 351 * Our ZS chips all share a common, autovectored interrupt, 352 * so we have to look at all of them on each interrupt. 353 */ 354 static int 355 zshard_ap(arg) 356 void *arg; 357 { 358 zshard(arg); 359 return 1; 360 } 361 362 /* 363 * Polled input char. 364 */ 365 int 366 zs_getc(arg) 367 void *arg; 368 { 369 register volatile struct zschan *zc = arg; 370 register int s, c, rr0; 371 372 s = splhigh(); 373 /* Wait for a character to arrive. */ 374 do { 375 rr0 = zc->zc_csr; 376 ZS_DELAY(); 377 } while ((rr0 & ZSRR0_RX_READY) == 0); 378 379 c = zc->zc_data; 380 ZS_DELAY(); 381 splx(s); 382 383 /* 384 * This is used by the kd driver to read scan codes, 385 * so don't translate '\r' ==> '\n' here... 386 */ 387 return (c); 388 } 389 390 /* 391 * Polled output char. 392 */ 393 void 394 zs_putc(arg, c) 395 void *arg; 396 int c; 397 { 398 register volatile struct zschan *zc = arg; 399 register int s, rr0; 400 401 s = splhigh(); 402 /* Wait for transmitter to become ready. */ 403 do { 404 rr0 = zc->zc_csr; 405 ZS_DELAY(); 406 } while ((rr0 & ZSRR0_TX_READY) == 0); 407 408 zc->zc_data = c; 409 ZS_DELAY(); 410 splx(s); 411 } 412 413 /*****************************************************************/ 414 415 static void zscnprobe __P((struct consdev *)); 416 static void zscninit __P((struct consdev *)); 417 static int zscngetc __P((dev_t)); 418 static void zscnputc __P((dev_t, int)); 419 static void zscnpollc __P((dev_t, int)); 420 421 struct consdev consdev_zs_ap = { 422 zscnprobe, 423 zscninit, 424 zscngetc, 425 zscnputc, 426 zscnpollc, 427 NULL, 428 }; 429 430 void 431 zscnprobe(cn) 432 struct consdev *cn; 433 { 434 } 435 436 void 437 zscninit(cn) 438 struct consdev *cn; 439 { 440 extern const struct cdevsw zstty_cdevsw; 441 442 cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0); 443 cn->cn_pri = CN_REMOTE; 444 zs_hwflags[0][0] = ZS_HWFLAG_CONSOLE; 445 } 446 447 int 448 zscngetc(dev) 449 dev_t dev; 450 { 451 return zs_getc((void *)NEWS5000_SCCPORT0A); 452 } 453 454 void 455 zscnputc(dev, c) 456 dev_t dev; 457 int c; 458 { 459 zs_putc((void *)NEWS5000_SCCPORT0A, c); 460 } 461 462 void 463 zscnpollc(dev, on) 464 dev_t dev; 465 int on; 466 { 467 } 468
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