screg_1185.h revision 1.1
1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: $Hdr: screg_1185.h,v 4.300 91/06/09 06:22:14 root Rel41 $ SONY 37 * 38 * @(#)screg_1185.h 8.1 (Berkeley) 6/11/93 39 */ 40 41 /* 42 * Copyright (c) 1989- by SONY Corporation. 43 */ 44 45 /* 46 * screg_1185.h ver 0.0 47 * for SCSI I/F Chip CXD1185Q 48 */ 49 50 /* 51 * SCSI I/F Chip CXD1185Q Register address assignment 52 */ 53 #ifdef mips 54 # define SCSI_BASE 0xbfe00100 55 #else 56 # define SCSI_BASE 0xe1900000 57 #endif 58 59 #ifndef U_CHAR 60 #ifdef mips 61 #define U_CHAR volatile u_char 62 #else 63 #define U_CHAR u_char 64 #endif 65 #endif 66 67 #define sc_statr *( (U_CHAR *)(SCSI_BASE + 0x0) ) 68 #define sc_comr *( (U_CHAR *)(SCSI_BASE + 0x0) ) 69 #define sc_datr *( (U_CHAR *)(SCSI_BASE + 0x1) ) 70 #define sc_intrq1 *( (U_CHAR *)(SCSI_BASE + 0x2) ) 71 #define sc_intrq2 *( (U_CHAR *)(SCSI_BASE + 0x3) ) 72 #define sc_envir *( (U_CHAR *)(SCSI_BASE + 0x3) ) 73 #define sc_cmonr *( (U_CHAR *)(SCSI_BASE + 0x4) ) 74 #define sc_timer *( (U_CHAR *)(SCSI_BASE + 0x4) ) 75 #define sc_ffstr *( (U_CHAR *)(SCSI_BASE + 0x5) ) 76 #define sc_idenr *( (U_CHAR *)(SCSI_BASE + 0x6) ) 77 #define sc_tclow *( (U_CHAR *)(SCSI_BASE + 0x7) ) 78 #define sc_tcmid *( (U_CHAR *)(SCSI_BASE + 0x8) ) 79 #define sc_tchi *( (U_CHAR *)(SCSI_BASE + 0x9) ) 80 #define sc_intok1 *( (U_CHAR *)(SCSI_BASE + 0xa) ) 81 #define sc_intok2 *( (U_CHAR *)(SCSI_BASE + 0xb) ) 82 #define sc_moder *( (U_CHAR *)(SCSI_BASE + 0xc) ) 83 #define sc_syncr *( (U_CHAR *)(SCSI_BASE + 0xd) ) 84 #define sc_busconr *( (U_CHAR *)(SCSI_BASE + 0xe) ) 85 #define sc_ioptr *( (U_CHAR *)(SCSI_BASE + 0xf) ) 86 87 /* 88 * CXD1185Q Register bit assignment 89 */ 90 91 /* sc_statr (status register) bit define 92 */ 93 #define R0_MRST 0x80 94 #define R0_MDBP 0x40 95 #define R0_INIT 0x10 96 #define R0_TARG 8 97 #define R0_TRBZ 4 98 #define R0_MIRQ 2 99 #define R0_CIP 1 100 101 /* sc_comr (command register) bit define 102 */ 103 #define R0_DMA 0x20 104 #define R0_TRBE 0x10 105 106 /* sc_intrq1 (interrupt request register 1) bit define 107 */ 108 #define R2_STO 0x10 109 #define R2_RSL 8 110 #define R2_SWA 4 111 #define R2_SWOA 2 112 #define R2_ARBF 1 113 114 /* sc_intrq2 (interrupt request register 2) bit define 115 */ 116 #define R3_FNC 0x80 117 #define R3_DCNT 0x40 118 #define R3_SRST 0x20 119 #define R3_PHC 0x10 120 #define R3_DATN 8 121 #define R3_DPE 4 122 #define R3_SPE 2 123 #define R3_RMSG 1 124 125 /* sc_envir (environment register) bit define 126 */ 127 #define R3_DIFE 0x80 128 #define R3_SDPM 0x40 129 #define R3_DPEN 0x20 130 #define R3_SIRM 0x10 131 #define R3_FS_MASK 3 132 133 /* sc_cmonr (scsi control monitor register) bit define 134 */ 135 #define R4_MBSY 0x80 136 #define R4_MSEL 0x40 137 #define R4_MMSG 0x20 138 #define R4_MCD 0x10 139 #define R4_MIO 8 140 #define R4_MREQ 4 141 #define R4_MACK 2 142 #define R4_MATN 1 143 144 /* sc_ffstr (FIFO status register) bit define 145 */ 146 #define R5_FIE 0x80 147 #define R5_FIF 0x10 148 #define R5_FIFOREM 0x1f 149 150 /* sc_idenr (scsi identify register) bit define 151 */ 152 #define R6_OID_MASK 0x07 153 #define R6_SID_MASK 0xe0 154 #define R6_TID_MASK 0xe0 155 156 /* sc_intok1 (interrupt enable register 1) bit define 157 */ 158 #define Ra_STO 0x10 159 #define Ra_RSL 8 160 #define Ra_SWA 4 161 #define Ra_SWOA 2 162 #define Ra_ARBF 1 163 164 /* sc_intok2 (interrupt enable register 2) bit define 165 */ 166 #define Rb_FNC 0x80 167 #define Rb_DCNT 0x40 168 #define Rb_SRST 0x20 169 #define Rb_PHC 0x10 170 #define Rb_DATN 8 171 #define Rb_DPE 4 172 #define Rb_SPE 2 173 #define Rb_RMSG 1 174 175 /* sc_moder (mode register) bit define 176 */ 177 #define Rc_HDPE 0x80 178 #define Rc_HSPE 0x40 179 #define Rc_HATN 0x20 180 #define Rc_TMSL 0x10 181 #define Rc_SPHI 8 182 #define Rc_BDMA 1 183 184 /* sc_syncr (synchronous transfer control register) bit define 185 */ 186 #define Rd_TPD_MASK 0xf0 187 #define Rd_TOF_MASK 0x0f 188 #define MIN_TP 62 /* minimum transfer period 4ns * 25 */ 189 #define MAX_OFFSET 15 190 191 /* sc_busconr (scsi bus control register) bit define 192 */ 193 #define Re_ABSY 0x80 194 #define Re_ASEL 0x40 195 #define Re_AMSG 0x20 196 #define Re_ACD 0x10 197 #define Re_AIO 8 198 #define Re_AREQ 4 199 #define Re_AACK 2 200 #define Re_AATN 1 201 202 /* sc_ioptr (I/O port) bit define 203 */ 204 #define Rf_PCN_MASK 0xf0 205 # define Rf_PCN3 0x80 206 # define Rf_PCN2 0x40 207 # define Rf_PCN1 0x20 208 # define Rf_PCN0 0x10 209 #define Rf_PRT_MASK 0x0f 210 # define Rf_PRT3 8 211 # define Rf_PRT2 4 212 # define Rf_PRT1 2 213 # define Rf_PRT0 1 214 215 216 /* 217 * CXD1185Q commands 218 */ 219 /* category 0 220 */ 221 #define SCMD_NOP 0x00 222 #define SCMD_CHIP_RST 0x01 223 #define SCMD_AST_RST 0x02 224 #define SCMD_FLSH_FIFO 0x03 225 #define SCMD_AST_CTRL 0x04 226 #define SCMD_NGT_CTRL 0x05 227 #define SCMD_AST_DATA 0x06 228 #define SCMD_NGT_DATA 0x07 229 230 /* category 1 231 */ 232 #define SCMD_RESEL 0x40 233 #define SCMD_SEL 0x41 234 #define SCMD_SEL_ATN 0x42 235 #define SCMD_ENB_SEL 0x43 236 #define SCMD_DIS_SEL 0x44 237 238 /* category 2 239 */ 240 #define SCMD_SEND_MES 0x80 241 #define SCMD_SEND_STAT 0x81 242 #define SCMD_SEND_DATA 0x82 243 #define SCMD_DISCONNECT 0x83 244 #define SCMD_RCV_MOUT 0x84 245 #define SCMD_RCV_CMD 0x85 246 #define SCMD_RCV_DATA 0x86 247 248 /* category 3 249 */ 250 #define SCMD_TR_INFO 0xc0 251 #define SCMD_TR_PAD 0xc1 252 #define SCMD_NGT_ACK 0xc2 253 #define SCMD_AST_ATN 0xc3 254 #define SCMD_NGT_ATN 0xc4 255 256 257 /* 258 * scsi parameter definition 259 */ 260 /* SCSI bus ID 261 */ 262 #define SC_OWNID 0x7 263 #define SC_TG_SHIFT 5 264 265 /* scsi bus phase 266 */ 267 #define SC_PMASK (R4_MMSG|R4_MCD|R4_MIO) 268 # define DAT_OUT 0 269 # define DAT_IN R4_MIO 270 # define COM_OUT R4_MCD 271 # define STAT_IN (R4_MCD|R4_MIO) 272 # define MES_OUT (R4_MMSG|R4_MCD) 273 # define MES_IN (R4_MMSG|R4_MCD|R4_MIO) 274 275 /* scsi command types define 276 */ 277 #define CMD_TYPEMASK 0xe0 278 # define CMD_T0 0 /* 6 byte commands */ 279 # define CMD_T1 0x20 /* 10 byte commands */ 280 # define CMD_T5 0xa0 /* 12 byte commands */ 281 # define CMD_T6 0xc0 282 # define CMD_T7 0xe0 283 284 #define MAXNSCSI 1 285
Indexes created Tue Sep 30 17:09:57 GMT 2025