screg_1185.h revision 1.3
1 /* $NetBSD: screg_1185.h,v 1.3 2002/05/31 21:45:01 thorpej Exp $ */ 2 /* 3 * Copyright (c) 1992, 1993 4 * The Regents of the University of California. All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: $Hdr: screg_1185.h,v 4.300 91/06/09 06:22:14 root Rel41 $ SONY 38 * 39 * @(#)screg_1185.h 8.1 (Berkeley) 6/11/93 40 */ 41 42 /* 43 * Copyright (c) 1989- by SONY Corporation. 44 */ 45 46 /* 47 * screg_1185.h ver 0.0 48 * for SCSI I/F Chip CXD1185Q 49 */ 50 51 /* 52 * SCSI I/F Chip CXD1185Q Register address assignment 53 */ 54 #ifdef __mips__ 55 # define SCSI_BASE 0xbfe00100 56 #else 57 # define SCSI_BASE 0xe1900000 58 #endif 59 60 #ifndef U_CHAR 61 #ifdef __mips__ 62 #define U_CHAR volatile u_char 63 #else 64 #define U_CHAR u_char 65 #endif 66 #endif 67 68 #define sc_statr *( (U_CHAR *)(SCSI_BASE + 0x0) ) 69 #define sc_comr *( (U_CHAR *)(SCSI_BASE + 0x0) ) 70 #define sc_datr *( (U_CHAR *)(SCSI_BASE + 0x1) ) 71 #define sc_intrq1 *( (U_CHAR *)(SCSI_BASE + 0x2) ) 72 #define sc_intrq2 *( (U_CHAR *)(SCSI_BASE + 0x3) ) 73 #define sc_envir *( (U_CHAR *)(SCSI_BASE + 0x3) ) 74 #define sc_cmonr *( (U_CHAR *)(SCSI_BASE + 0x4) ) 75 #define sc_timer *( (U_CHAR *)(SCSI_BASE + 0x4) ) 76 #define sc_ffstr *( (U_CHAR *)(SCSI_BASE + 0x5) ) 77 #define sc_idenr *( (U_CHAR *)(SCSI_BASE + 0x6) ) 78 #define sc_tclow *( (U_CHAR *)(SCSI_BASE + 0x7) ) 79 #define sc_tcmid *( (U_CHAR *)(SCSI_BASE + 0x8) ) 80 #define sc_tchi *( (U_CHAR *)(SCSI_BASE + 0x9) ) 81 #define sc_intok1 *( (U_CHAR *)(SCSI_BASE + 0xa) ) 82 #define sc_intok2 *( (U_CHAR *)(SCSI_BASE + 0xb) ) 83 #define sc_moder *( (U_CHAR *)(SCSI_BASE + 0xc) ) 84 #define sc_syncr *( (U_CHAR *)(SCSI_BASE + 0xd) ) 85 #define sc_busconr *( (U_CHAR *)(SCSI_BASE + 0xe) ) 86 #define sc_ioptr *( (U_CHAR *)(SCSI_BASE + 0xf) ) 87 88 /* 89 * CXD1185Q Register bit assignment 90 */ 91 92 /* sc_statr (status register) bit define 93 */ 94 #define R0_MRST 0x80 95 #define R0_MDBP 0x40 96 #define R0_INIT 0x10 97 #define R0_TARG 8 98 #define R0_TRBZ 4 99 #define R0_MIRQ 2 100 #define R0_CIP 1 101 102 /* sc_comr (command register) bit define 103 */ 104 #define R0_DMA 0x20 105 #define R0_TRBE 0x10 106 107 /* sc_intrq1 (interrupt request register 1) bit define 108 */ 109 #define R2_STO 0x10 110 #define R2_RSL 8 111 #define R2_SWA 4 112 #define R2_SWOA 2 113 #define R2_ARBF 1 114 115 /* sc_intrq2 (interrupt request register 2) bit define 116 */ 117 #define R3_FNC 0x80 118 #define R3_DCNT 0x40 119 #define R3_SRST 0x20 120 #define R3_PHC 0x10 121 #define R3_DATN 8 122 #define R3_DPE 4 123 #define R3_SPE 2 124 #define R3_RMSG 1 125 126 /* sc_envir (environment register) bit define 127 */ 128 #define R3_DIFE 0x80 129 #define R3_SDPM 0x40 130 #define R3_DPEN 0x20 131 #define R3_SIRM 0x10 132 #define R3_FS_MASK 3 133 134 /* sc_cmonr (scsi control monitor register) bit define 135 */ 136 #define R4_MBSY 0x80 137 #define R4_MSEL 0x40 138 #define R4_MMSG 0x20 139 #define R4_MCD 0x10 140 #define R4_MIO 8 141 #define R4_MREQ 4 142 #define R4_MACK 2 143 #define R4_MATN 1 144 145 /* sc_ffstr (FIFO status register) bit define 146 */ 147 #define R5_FIE 0x80 148 #define R5_FIF 0x10 149 #define R5_FIFOREM 0x1f 150 151 /* sc_idenr (scsi identify register) bit define 152 */ 153 #define R6_OID_MASK 0x07 154 #define R6_SID_MASK 0xe0 155 #define R6_TID_MASK 0xe0 156 157 /* sc_intok1 (interrupt enable register 1) bit define 158 */ 159 #define Ra_STO 0x10 160 #define Ra_RSL 8 161 #define Ra_SWA 4 162 #define Ra_SWOA 2 163 #define Ra_ARBF 1 164 165 /* sc_intok2 (interrupt enable register 2) bit define 166 */ 167 #define Rb_FNC 0x80 168 #define Rb_DCNT 0x40 169 #define Rb_SRST 0x20 170 #define Rb_PHC 0x10 171 #define Rb_DATN 8 172 #define Rb_DPE 4 173 #define Rb_SPE 2 174 #define Rb_RMSG 1 175 176 /* sc_moder (mode register) bit define 177 */ 178 #define Rc_HDPE 0x80 179 #define Rc_HSPE 0x40 180 #define Rc_HATN 0x20 181 #define Rc_TMSL 0x10 182 #define Rc_SPHI 8 183 #define Rc_BDMA 1 184 185 /* sc_syncr (synchronous transfer control register) bit define 186 */ 187 #define Rd_TPD_MASK 0xf0 188 #define Rd_TOF_MASK 0x0f 189 #define MIN_TP 62 /* minimum transfer period 4ns * 25 */ 190 #define MAX_OFFSET 15 191 192 /* sc_busconr (scsi bus control register) bit define 193 */ 194 #define Re_ABSY 0x80 195 #define Re_ASEL 0x40 196 #define Re_AMSG 0x20 197 #define Re_ACD 0x10 198 #define Re_AIO 8 199 #define Re_AREQ 4 200 #define Re_AACK 2 201 #define Re_AATN 1 202 203 /* sc_ioptr (I/O port) bit define 204 */ 205 #define Rf_PCN_MASK 0xf0 206 # define Rf_PCN3 0x80 207 # define Rf_PCN2 0x40 208 # define Rf_PCN1 0x20 209 # define Rf_PCN0 0x10 210 #define Rf_PRT_MASK 0x0f 211 # define Rf_PRT3 8 212 # define Rf_PRT2 4 213 # define Rf_PRT1 2 214 # define Rf_PRT0 1 215 216 217 /* 218 * CXD1185Q commands 219 */ 220 /* category 0 221 */ 222 #define SCMD_NOP 0x00 223 #define SCMD_CHIP_RST 0x01 224 #define SCMD_AST_RST 0x02 225 #define SCMD_FLSH_FIFO 0x03 226 #define SCMD_AST_CTRL 0x04 227 #define SCMD_NGT_CTRL 0x05 228 #define SCMD_AST_DATA 0x06 229 #define SCMD_NGT_DATA 0x07 230 231 /* category 1 232 */ 233 #define SCMD_RESEL 0x40 234 #define SCMD_SEL 0x41 235 #define SCMD_SEL_ATN 0x42 236 #define SCMD_ENB_SEL 0x43 237 #define SCMD_DIS_SEL 0x44 238 239 /* category 2 240 */ 241 #define SCMD_SEND_MES 0x80 242 #define SCMD_SEND_STAT 0x81 243 #define SCMD_SEND_DATA 0x82 244 #define SCMD_DISCONNECT 0x83 245 #define SCMD_RCV_MOUT 0x84 246 #define SCMD_RCV_CMD 0x85 247 #define SCMD_RCV_DATA 0x86 248 249 /* category 3 250 */ 251 #define SCMD_TR_INFO 0xc0 252 #define SCMD_TR_PAD 0xc1 253 #define SCMD_NGT_ACK 0xc2 254 #define SCMD_AST_ATN 0xc3 255 #define SCMD_NGT_ATN 0xc4 256 257 258 /* 259 * scsi parameter definition 260 */ 261 /* SCSI bus ID 262 */ 263 #define SC_OWNID 0x7 264 #define SC_TG_SHIFT 5 265 266 /* scsi bus phase 267 */ 268 #define SC_PMASK (R4_MMSG|R4_MCD|R4_MIO) 269 # define DAT_OUT 0 270 # define DAT_IN R4_MIO 271 # define COM_OUT R4_MCD 272 # define STAT_IN (R4_MCD|R4_MIO) 273 # define MES_OUT (R4_MMSG|R4_MCD) 274 # define MES_IN (R4_MMSG|R4_MCD|R4_MIO) 275 276 /* scsi command types define 277 */ 278 #define CMD_TYPEMASK 0xe0 279 # define CMD_T0 0 /* 6 byte commands */ 280 # define CMD_T1 0x20 /* 10 byte commands */ 281 # define CMD_T5 0xa0 /* 12 byte commands */ 282 # define CMD_T6 0xc0 283 # define CMD_T7 0xe0 284 285 #define MAXNSCSI 1 286
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