screg_1185.h revision 1.5
1 /* $NetBSD: screg_1185.h,v 1.5 2003/08/07 16:28:52 agc Exp $ */ 2 /* 3 * Copyright (c) 1992, 1993 4 * The Regents of the University of California. All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: $Hdr: screg_1185.h,v 4.300 91/06/09 06:22:14 root Rel41 $ SONY 34 * 35 * @(#)screg_1185.h 8.1 (Berkeley) 6/11/93 36 */ 37 38 /* 39 * Copyright (c) 1989- by SONY Corporation. 40 */ 41 42 /* 43 * screg_1185.h ver 0.0 44 * for SCSI I/F Chip CXD1185Q 45 */ 46 47 /* 48 * SCSI I/F Chip CXD1185Q Register address assignment 49 */ 50 #ifdef __mips__ 51 # define SCSI_BASE 0xbfe00100 52 #else 53 # define SCSI_BASE 0xe1900000 54 #endif 55 56 #ifndef U_CHAR 57 #ifdef __mips__ 58 #define U_CHAR volatile u_char 59 #else 60 #define U_CHAR u_char 61 #endif 62 #endif 63 64 #define sc_statr *( (U_CHAR *)(SCSI_BASE + 0x0) ) 65 #define sc_comr *( (U_CHAR *)(SCSI_BASE + 0x0) ) 66 #define sc_datr *( (U_CHAR *)(SCSI_BASE + 0x1) ) 67 #define sc_intrq1 *( (U_CHAR *)(SCSI_BASE + 0x2) ) 68 #define sc_intrq2 *( (U_CHAR *)(SCSI_BASE + 0x3) ) 69 #define sc_envir *( (U_CHAR *)(SCSI_BASE + 0x3) ) 70 #define sc_cmonr *( (U_CHAR *)(SCSI_BASE + 0x4) ) 71 #define sc_timer *( (U_CHAR *)(SCSI_BASE + 0x4) ) 72 #define sc_ffstr *( (U_CHAR *)(SCSI_BASE + 0x5) ) 73 #define sc_idenr *( (U_CHAR *)(SCSI_BASE + 0x6) ) 74 #define sc_tclow *( (U_CHAR *)(SCSI_BASE + 0x7) ) 75 #define sc_tcmid *( (U_CHAR *)(SCSI_BASE + 0x8) ) 76 #define sc_tchi *( (U_CHAR *)(SCSI_BASE + 0x9) ) 77 #define sc_intok1 *( (U_CHAR *)(SCSI_BASE + 0xa) ) 78 #define sc_intok2 *( (U_CHAR *)(SCSI_BASE + 0xb) ) 79 #define sc_moder *( (U_CHAR *)(SCSI_BASE + 0xc) ) 80 #define sc_syncr *( (U_CHAR *)(SCSI_BASE + 0xd) ) 81 #define sc_busconr *( (U_CHAR *)(SCSI_BASE + 0xe) ) 82 #define sc_ioptr *( (U_CHAR *)(SCSI_BASE + 0xf) ) 83 84 /* 85 * CXD1185Q Register bit assignment 86 */ 87 88 /* sc_statr (status register) bit define 89 */ 90 #define R0_MRST 0x80 91 #define R0_MDBP 0x40 92 #define R0_INIT 0x10 93 #define R0_TARG 8 94 #define R0_TRBZ 4 95 #define R0_MIRQ 2 96 #define R0_CIP 1 97 98 /* sc_comr (command register) bit define 99 */ 100 #define R0_DMA 0x20 101 #define R0_TRBE 0x10 102 103 /* sc_intrq1 (interrupt request register 1) bit define 104 */ 105 #define R2_STO 0x10 106 #define R2_RSL 8 107 #define R2_SWA 4 108 #define R2_SWOA 2 109 #define R2_ARBF 1 110 111 /* sc_intrq2 (interrupt request register 2) bit define 112 */ 113 #define R3_FNC 0x80 114 #define R3_DCNT 0x40 115 #define R3_SRST 0x20 116 #define R3_PHC 0x10 117 #define R3_DATN 8 118 #define R3_DPE 4 119 #define R3_SPE 2 120 #define R3_RMSG 1 121 122 /* sc_envir (environment register) bit define 123 */ 124 #define R3_DIFE 0x80 125 #define R3_SDPM 0x40 126 #define R3_DPEN 0x20 127 #define R3_SIRM 0x10 128 #define R3_FS_MASK 3 129 130 /* sc_cmonr (scsi control monitor register) bit define 131 */ 132 #define R4_MBSY 0x80 133 #define R4_MSEL 0x40 134 #define R4_MMSG 0x20 135 #define R4_MCD 0x10 136 #define R4_MIO 8 137 #define R4_MREQ 4 138 #define R4_MACK 2 139 #define R4_MATN 1 140 141 /* sc_ffstr (FIFO status register) bit define 142 */ 143 #define R5_FIE 0x80 144 #define R5_FIF 0x10 145 #define R5_FIFOREM 0x1f 146 147 /* sc_idenr (scsi identify register) bit define 148 */ 149 #define R6_OID_MASK 0x07 150 #define R6_SID_MASK 0xe0 151 #define R6_TID_MASK 0xe0 152 153 /* sc_intok1 (interrupt enable register 1) bit define 154 */ 155 #define Ra_STO 0x10 156 #define Ra_RSL 8 157 #define Ra_SWA 4 158 #define Ra_SWOA 2 159 #define Ra_ARBF 1 160 161 /* sc_intok2 (interrupt enable register 2) bit define 162 */ 163 #define Rb_FNC 0x80 164 #define Rb_DCNT 0x40 165 #define Rb_SRST 0x20 166 #define Rb_PHC 0x10 167 #define Rb_DATN 8 168 #define Rb_DPE 4 169 #define Rb_SPE 2 170 #define Rb_RMSG 1 171 172 /* sc_moder (mode register) bit define 173 */ 174 #define Rc_HDPE 0x80 175 #define Rc_HSPE 0x40 176 #define Rc_HATN 0x20 177 #define Rc_TMSL 0x10 178 #define Rc_SPHI 8 179 #define Rc_BDMA 1 180 181 /* sc_syncr (synchronous transfer control register) bit define 182 */ 183 #define Rd_TPD_MASK 0xf0 184 #define Rd_TOF_MASK 0x0f 185 #define MIN_TP 62 /* minimum transfer period 4ns * 25 */ 186 #define MAX_OFFSET 15 187 188 /* sc_busconr (scsi bus control register) bit define 189 */ 190 #define Re_ABSY 0x80 191 #define Re_ASEL 0x40 192 #define Re_AMSG 0x20 193 #define Re_ACD 0x10 194 #define Re_AIO 8 195 #define Re_AREQ 4 196 #define Re_AACK 2 197 #define Re_AATN 1 198 199 /* sc_ioptr (I/O port) bit define 200 */ 201 #define Rf_PCN_MASK 0xf0 202 # define Rf_PCN3 0x80 203 # define Rf_PCN2 0x40 204 # define Rf_PCN1 0x20 205 # define Rf_PCN0 0x10 206 #define Rf_PRT_MASK 0x0f 207 # define Rf_PRT3 8 208 # define Rf_PRT2 4 209 # define Rf_PRT1 2 210 # define Rf_PRT0 1 211 212 213 /* 214 * CXD1185Q commands 215 */ 216 /* category 0 217 */ 218 #define SCMD_NOP 0x00 219 #define SCMD_CHIP_RST 0x01 220 #define SCMD_AST_RST 0x02 221 #define SCMD_FLSH_FIFO 0x03 222 #define SCMD_AST_CTRL 0x04 223 #define SCMD_NGT_CTRL 0x05 224 #define SCMD_AST_DATA 0x06 225 #define SCMD_NGT_DATA 0x07 226 227 /* category 1 228 */ 229 #define SCMD_RESEL 0x40 230 #define SCMD_SEL 0x41 231 #define SCMD_SEL_ATN 0x42 232 #define SCMD_ENB_SEL 0x43 233 #define SCMD_DIS_SEL 0x44 234 235 /* category 2 236 */ 237 #define SCMD_SEND_MES 0x80 238 #define SCMD_SEND_STAT 0x81 239 #define SCMD_SEND_DATA 0x82 240 #define SCMD_DISCONNECT 0x83 241 #define SCMD_RCV_MOUT 0x84 242 #define SCMD_RCV_CMD 0x85 243 #define SCMD_RCV_DATA 0x86 244 245 /* category 3 246 */ 247 #define SCMD_TR_INFO 0xc0 248 #define SCMD_TR_PAD 0xc1 249 #define SCMD_NGT_ACK 0xc2 250 #define SCMD_AST_ATN 0xc3 251 #define SCMD_NGT_ATN 0xc4 252 253 254 /* 255 * scsi parameter definition 256 */ 257 /* SCSI bus ID 258 */ 259 #define SC_OWNID 0x7 260 #define SC_TG_SHIFT 5 261 262 /* scsi bus phase 263 */ 264 #define SC_PMASK (R4_MMSG|R4_MCD|R4_MIO) 265 # define DAT_OUT 0 266 # define DAT_IN R4_MIO 267 # define COM_OUT R4_MCD 268 # define STAT_IN (R4_MCD|R4_MIO) 269 # define MES_OUT (R4_MMSG|R4_MCD) 270 # define MES_IN (R4_MMSG|R4_MCD|R4_MIO) 271 272 /* scsi command types define 273 */ 274 #define CMD_TYPEMASK 0xe0 275 # define CMD_T0 0 /* 6 byte commands */ 276 # define CMD_T1 0x20 /* 10 byte commands */ 277 # define CMD_T5 0xa0 /* 12 byte commands */ 278 # define CMD_T6 0xc0 279 # define CMD_T7 0xe0 280 281 #define MAXNSCSI 1 282
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