scsi_1185.c revision 1.13
1 /* $NetBSD: scsi_1185.c,v 1.13 2003/08/07 16:28:52 agc Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: $Hdr: scsi_1185.c,v 4.300 91/06/09 06:22:20 root Rel41 $ SONY 35 * 36 * @(#)scsi_1185.c 8.1 (Berkeley) 6/11/93 37 */ 38 39 /* 40 * Copyright (c) 1989- by SONY Corporation. 41 * 42 * scsi_1185.c 43 * 44 * CXD1185Q 45 * SCSI bus low level common routines 46 * for one cpu machine 47 * 48 * MODIFY HISTORY: 49 * 50 * DMAC_WAIT --- DMAC_0266 wo tukau-baai, DMAC mata-wa SCSI-chip ni 51 * tuzukete access suru-baai, 52 * kanarazu wait wo ireru-beshi ! 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: scsi_1185.c,v 1.13 2003/08/07 16:28:52 agc Exp $"); 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/device.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <dev/scsipi/scsi_all.h> 65 #include <dev/scsipi/scsipi_all.h> 66 #include <dev/scsipi/scsiconf.h> 67 68 #include <machine/cpu.h> 69 #include <machine/intr.h> 70 #include <machine/machConst.h> 71 72 #include <mips/cache.h> 73 74 #include <newsmips/dev/screg_1185.h> 75 #include <newsmips/dev/scsireg.h> 76 77 #if defined(news3400) 78 # include <newsmips/dev/dmac_0448.h> 79 # ifndef NDMACMAP 80 # define NDMACMAP 144 81 # endif 82 #endif 83 84 #define VOLATILE volatile 85 #define ABORT_SYNCTR_MES_FROM_TARGET 86 #define SCSI_1185AQ 87 #define RESET_RECOVER 88 #define DMAC_MAP_INIT /* for nws-3700 parity error */ 89 #define APAD_ALWAYS_ON 90 91 #define CHECK_LOOP_CNT 60 92 #define RSL_LOOP_CNT 60 93 94 #ifndef DMAC_MAP_INIT 95 # define MAP_OVER_ACCESS /* for nws-3700 parity error */ 96 #endif 97 98 #undef CHECK_MRQ 99 100 #ifdef NOT_SUPPORT_SYNCTR 101 # define MAX_OFFSET_BYTES 0 102 #else 103 # define MAX_OFFSET_BYTES MAX_OFFSET 104 #endif 105 106 #define act_point spoint 107 #define act_trcnt stcnt 108 #define act_tag stag 109 #define act_offset soffset 110 111 #define splscsi splsc 112 113 #if defined(__mips__) && defined(CPU_SINGLE) 114 #define nops(x) { int i; for (i = 0; i < (x); i++) ; } 115 #define DMAC_WAIT0 ; 116 #else 117 #define DMAC_WAIT0 DMAC_WAIT 118 #endif 119 120 #ifdef DMAC_MAP_INIT 121 static int dmac_map_init = 0; 122 #endif 123 124 /* 125 * command flag status 126 */ 127 #define CF_SET 1 128 #define CF_SEND 2 129 #define CF_ENOUGH 3 130 #define CF_EXEC 4 131 132 #define SEL_TIMEOUT_VALUE 0x7a 133 134 extern struct cfdriver sc_cd; 135 136 void sc_send __P((struct sc_scb *, int, int)); 137 int scintr __P((void)); 138 void scsi_hardreset __P((void)); 139 void scsi_chipreset __P((struct sc_softc *)); 140 void scsi_softreset __P((struct sc_softc *)); 141 int sc_busy __P((struct sc_softc *, int)); 142 143 static int WAIT_STATR_BITCLR __P((int)); 144 static int WAIT_STATR_BITSET __P((int)); 145 static void SET_CMD __P((struct sc_softc *, int)); 146 static void SET_CNT __P((int)); 147 static int GET_CNT __P((void)); 148 static void GET_INTR __P((VOLATILE int *, VOLATILE int *)); 149 static void sc_start __P((struct sc_softc *)); 150 static void sc_resel __P((struct sc_softc *)); 151 static void sc_discon __P((struct sc_softc *)); 152 static void sc_pmatch __P((struct sc_softc *)); 153 static void flush_fifo __P((struct sc_softc *)); 154 static void sc_cout __P((struct sc_softc *, struct sc_chan_stat *)); 155 static void sc_min __P((struct sc_softc *, struct sc_chan_stat *)); 156 static void sc_mout __P((struct sc_softc *, struct sc_chan_stat *)); 157 static void sc_sin __P((struct sc_softc *, VOLATILE struct sc_chan_stat *)); 158 static void sc_dio __P((struct sc_softc *, VOLATILE struct sc_chan_stat *)); 159 static void sc_dio_pad __P((struct sc_softc *, VOLATILE struct sc_chan_stat *)); 160 static void print_scsi_stat __P((struct sc_softc *)); 161 static void append_wb __P((struct sc_softc *, struct sc_chan_stat *)); 162 static struct sc_chan_stat *get_wb_chan __P((struct sc_softc *)); 163 static int release_wb __P((struct sc_softc *)); 164 static void adjust_transfer __P((struct sc_softc *, struct sc_chan_stat *)); 165 static void clean_k2dcache __P((struct sc_scb *)); 166 167 extern void sc_done __P((struct sc_scb *)); 168 extern paddr_t kvtophys __P((vaddr_t)); 169 170 #if defined(__mips__) && defined(CPU_SINGLE) 171 #define dma_reset(x) { \ 172 int s = splscsi(); \ 173 dmac_gsel = (x); dmac_cctl = DM_RST; dmac_cctl = 0; \ 174 splx(s); \ 175 } 176 #endif 177 178 int 179 WAIT_STATR_BITCLR(bitmask) 180 register int bitmask; 181 { 182 register int iloop; 183 register VOLATILE int dummy; 184 185 iloop = 0; 186 do { 187 dummy = sc_statr; 188 DMAC_WAIT0; 189 if (iloop++ > CHECK_LOOP_CNT) 190 return (-1); 191 } while (dummy & bitmask); 192 return (0); 193 } 194 195 int 196 WAIT_STATR_BITSET(bitmask) 197 register int bitmask; 198 { 199 register int iloop; 200 register VOLATILE int dummy; 201 202 iloop = 0; 203 do { 204 dummy = sc_statr; 205 DMAC_WAIT0; 206 if (iloop++ > CHECK_LOOP_CNT) 207 return (-1); 208 } while ((dummy & bitmask) == 0); 209 return (0); 210 } 211 212 void 213 SET_CMD(sc, CMD) 214 struct sc_softc *sc; 215 register int CMD; 216 { 217 (void) WAIT_STATR_BITCLR(R0_CIP); 218 sc->lastcmd = (CMD); 219 sc_comr = (CMD); 220 DMAC_WAIT0; 221 } 222 223 void 224 SET_CNT(COUNT) 225 register int COUNT; 226 { 227 sc_tclow = (COUNT) & 0xff; 228 DMAC_WAIT0; 229 sc_tcmid = ((COUNT) >> 8) & 0xff; 230 DMAC_WAIT0; 231 sc_tchi = ((COUNT) >> 16) & 0xff; 232 DMAC_WAIT0; 233 } 234 235 int 236 GET_CNT() 237 { 238 register VOLATILE int COUNT; 239 240 COUNT = sc_tclow; 241 DMAC_WAIT0; 242 COUNT += (sc_tcmid << 8) & 0xff00; 243 DMAC_WAIT0; 244 COUNT += (sc_tchi << 16) & 0xff0000; 245 DMAC_WAIT0; 246 return (COUNT); 247 } 248 249 void 250 GET_INTR(DATA1, DATA2) 251 register VOLATILE int *DATA1; 252 register VOLATILE int *DATA2; 253 { 254 (void) WAIT_STATR_BITCLR(R0_CIP); 255 while (sc_statr & R0_MIRQ) { 256 DMAC_WAIT0; 257 *DATA1 |= sc_intrq1; 258 DMAC_WAIT0; 259 *DATA2 |= sc_intrq2; 260 DMAC_WAIT0; 261 } 262 } 263 264 265 void 266 sc_send(scb, chan, ie) 267 struct sc_scb *scb; 268 int chan, ie; 269 { 270 struct sc_softc *sc = scb->scb_softc; 271 struct sc_chan_stat *cs; 272 struct scsipi_xfer *xs; 273 int i; 274 u_char *p; 275 276 cs = &sc->chan_stat[chan]; 277 xs = scb->xs; 278 279 p = (u_char *)xs->cmd; 280 if (cs->scb != NULL) { 281 printf("SCSI%d: sc_send() NOT NULL cs->sc\n", chan); 282 printf("ie=0x%x scb=0x%p cs->sc=0x%p\n", ie, scb, cs->scb); 283 printf("cdb="); 284 for (i = 0; i < 6; i++) 285 printf(" 0x%x", *p++); 286 printf("\n"); 287 panic("SCSI soft error"); 288 /*NOTREACHED*/ 289 } 290 291 if (p[0] == SCOP_RESET && p[1] == SCOP_RESET) { 292 /* 293 * SCSI bus reset command procedure 294 * (vender unique by Sony Corp.) 295 */ 296 #ifdef SCSI_1185AQ 297 if (sc_idenr & 0x08) 298 sc->scsi_1185AQ = 1; 299 else 300 sc->scsi_1185AQ = 0; 301 #endif 302 cs->scb = scb; 303 scsi_hardreset(); 304 scb->istatus = INST_EP; 305 cs->scb = NULL; 306 sc_done(scb); 307 return; 308 } 309 310 if (scb->sc_map && (scb->sc_map->mp_pages > 0)) { 311 /* 312 * use map table 313 */ 314 scb->sc_coffset = scb->sc_map->mp_offset & PGOFSET; 315 if (scb->sc_map->mp_pages > NSCMAP) { 316 printf("SCSI%d: map table overflow\n", chan); 317 scb->istatus = INST_EP|INST_LB|INST_PRE; 318 return; 319 } 320 } else { 321 /* 322 * no use map table 323 */ 324 scb->sc_coffset = (u_int)scb->sc_cpoint & PGOFSET; 325 } 326 scb->sc_ctag = 0; 327 328 cs->scb = scb; 329 cs->comflg = OFF; 330 331 cs->intr_flg = ie; 332 cs->chan_num = chan; 333 sc->perr_flag[chan] = 0; 334 sc->mout_flag[chan] = 0; 335 sc->min_cnt[chan] = 0; 336 337 sc->sel_stat[chan] = SEL_WAIT; 338 append_wb(sc, cs); 339 sc_start(sc); 340 } 341 342 /* 343 * SCSI start up routine 344 */ 345 void 346 sc_start(sc) 347 struct sc_softc *sc; 348 { 349 struct sc_chan_stat *cs; 350 int chan, dummy; 351 int s; 352 353 s = splscsi(); 354 cs = get_wb_chan(sc); 355 if ((cs == NULL) || (sc->ipc >= 0)) 356 goto sc_start_exit; 357 chan = cs->chan_num; 358 if (sc->sel_stat[chan] != SEL_WAIT) { 359 /* 360 * already started 361 */ 362 goto sc_start_exit; 363 } 364 sc->sel_stat[chan] = SEL_START; 365 366 dummy = sc_cmonr; 367 DMAC_WAIT0; 368 if (dummy & (R4_MBSY|R4_MSEL)) { 369 sc->sel_stat[chan] = SEL_WAIT; 370 goto sc_start_exit; 371 } 372 373 /* 374 * send SELECT with ATN command 375 */ 376 sc->dma_stat = OFF; 377 sc->pad_start = 0; 378 dummy = sc_statr; 379 DMAC_WAIT0; 380 if (dummy & R0_CIP) { 381 sc->sel_stat[chan] = SEL_WAIT; 382 goto sc_start_exit; 383 } 384 sc_idenr = (chan << SC_TG_SHIFT) | SC_OWNID; 385 DMAC_WAIT0; 386 #ifdef SCSI_1185AQ 387 if (sc->scsi_1185AQ) 388 sc_intok1 = Ra_STO|Ra_ARBF; 389 else 390 sc_intok1 = Ra_STO|Ra_RSL|Ra_ARBF; 391 #else 392 sc_intok1 = Ra_STO|Ra_RSL|Ra_ARBF; 393 #endif 394 DMAC_WAIT0; 395 /* 396 * BUGFIX for signal reflection on BSY 397 * !Rb_DCNT 398 */ 399 sc_intok2 = Rb_FNC|Rb_SRST|Rb_PHC|Rb_SPE; 400 DMAC_WAIT0; 401 402 dummy = sc_cmonr; 403 DMAC_WAIT0; 404 if (dummy & (R4_MBSY|R4_MSEL)) { 405 sc->sel_stat[chan] = SEL_WAIT; 406 goto sc_start_exit; 407 } 408 SET_CMD(sc, SCMD_SEL_ATN); 409 410 sc_start_exit: 411 splx(s); 412 } 413 414 /* 415 * SCSI interrupt service routine 416 */ 417 int 418 scintr() 419 { 420 register int iloop; 421 register VOLATILE int chan; 422 register VOLATILE int dummy; 423 struct sc_softc *sc; 424 struct sc_chan_stat *cs; 425 int s_int1, s_int2; 426 427 sc = sc_cd.cd_devs[0]; /* XXX */ 428 429 scintr_loop: 430 431 #if defined(CHECK_MRQ) && defined(news3400) 432 while (dmac_gstat & CH_MRQ(CH_SCSI)) 433 DMAC_WAIT; 434 #endif 435 436 for (iloop = 0; iloop < 100; iloop++) { 437 dummy = sc_statr; 438 DMAC_WAIT; 439 if ((dummy & R0_CIP) == 0) 440 break; 441 } 442 443 /* 444 * get SCSI interrupt request 445 */ 446 while (sc_statr & R0_MIRQ) { 447 DMAC_WAIT0; 448 s_int1 = sc_intrq1; 449 DMAC_WAIT0; 450 s_int2 = sc_intrq2; 451 DMAC_WAIT0; 452 sc->int_stat1 |= s_int1; 453 sc->int_stat2 |= s_int2; 454 } 455 456 if (sc->int_stat2 & R3_SRST) { 457 /* 458 * RST signal is drived 459 */ 460 sc->int_stat2 &= ~R3_SRST; 461 scsi_softreset(sc); 462 goto scintr_exit; 463 } 464 465 if ((sc->ipc < 0) && (sc->wrc <= 0) && (sc->wbc <= 0)) { 466 sc->int_stat1 = 0; 467 sc->int_stat2 = 0; 468 goto scintr_exit; 469 } 470 471 cs = get_wb_chan(sc); 472 if (cs) chan = cs->chan_num; 473 474 if (cs && (sc->sel_stat[chan] == SEL_START) && 475 (sc->lastcmd == SCMD_SEL_ATN)) { 476 /* 477 * Check the result of SELECTION command 478 */ 479 if (sc->int_stat1 & R2_RSL) { 480 /* 481 * RESELECTION occur 482 */ 483 if (sc->wrc > 0) { 484 sc->sel_stat[chan] = SEL_RSLD; 485 } else { 486 /* 487 * Ghost RESELECTION ??? 488 */ 489 sc->int_stat1 &= ~R2_RSL; 490 } 491 } 492 if (sc->int_stat1 & R2_ARBF) { 493 /* 494 * ARBITRATION fault 495 */ 496 sc->int_stat1 &= ~R2_ARBF; 497 sc->sel_stat[chan] = SEL_ARBF; 498 } 499 if (sc->int_stat1 & R2_STO) { 500 /* 501 * SELECTION timeout 502 */ 503 sc->int_stat1 &= ~R2_STO; 504 if ((sc->int_stat2&(R3_PHC|R3_RMSG)) != (R3_PHC|R3_RMSG)) { 505 sc->ipc = chan; 506 sc->ip = &sc->chan_stat[chan]; 507 sc->sel_stat[chan] = SEL_TIMEOUT; 508 sc->chan_stat[chan].scb->istatus 509 = INST_EP|INST_TO; 510 release_wb(sc); 511 } 512 } 513 514 /* 515 * SELECTION command done 516 */ 517 switch (sc->sel_stat[chan]) { 518 519 case SEL_START: 520 if ((sc->int_stat2 & R3_FNC) == 0) 521 break; 522 /* 523 * SELECTION success 524 */ 525 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE; 526 sc->ipc = chan; 527 sc->ip = &sc->chan_stat[chan]; 528 sc->ip->scb->istatus |= INST_IP; 529 sc->dma_stat = OFF; 530 sc->pad_start = 0; 531 sc->sel_stat[chan] = SEL_SUCCESS; 532 release_wb(sc); 533 #ifndef NOT_SUPPORT_SYNCTR 534 sc_syncr = sc->sync_tr[chan]; 535 DMAC_WAIT0; 536 #endif 537 DMAC_WAIT0; 538 break; 539 540 case SEL_TIMEOUT: 541 /* 542 * SELECTION time out 543 */ 544 sc_discon(sc); 545 goto scintr_exit; 546 547 /* case SEL_RSLD: */ 548 /* case SEL_ARBF: */ 549 default: 550 /* 551 * SELECTION failed 552 */ 553 sc->sel_stat[chan] = SEL_WAIT; 554 break; 555 } 556 if ((sc->int_stat1 & R2_RSL) == 0) 557 sc->int_stat2 &= ~R3_FNC; 558 } 559 560 if (sc->ip != NULL) { 561 /* 562 * check In Process channel's request 563 */ 564 if (sc->dma_stat != OFF) { 565 /* 566 * adjust pointer & counter 567 */ 568 adjust_transfer(sc, sc->ip); 569 } 570 if (sc->int_stat2 & R3_SPE) { 571 register int VOLATILE statr; 572 register int VOLATILE cmonr; 573 574 statr = sc_statr; 575 DMAC_WAIT0; 576 cmonr = sc_cmonr; 577 sc->int_stat2 &= ~R3_SPE; 578 sc->perr_flag[sc->ip->chan_num] = 1; 579 } 580 } 581 582 if (sc->int_stat2 & R3_DCNT) { 583 /* 584 * Bus Free 585 */ 586 sc_discon(sc); 587 sc->int_stat2 &= ~R3_DCNT; 588 } 589 590 if ((sc->ipc >= 0) && (sc->sel_stat[sc->ipc] == SEL_RSL_WAIT)) { 591 sc->sel_stat[sc->ipc] = SEL_RSLD; 592 sc->ipc = -1; 593 sc->int_stat1 |= R2_RSL; 594 } 595 if (sc->int_stat1 & R2_RSL) { 596 /* 597 * Reselection 598 */ 599 sc_resel(sc); 600 sc->int_stat1 &= ~R2_RSL; 601 if (sc->sel_stat[sc->ipc] == SEL_RSL_WAIT) 602 goto scintr_exit; 603 } 604 605 606 if ((sc->ipc >= 0) && (sc->ipc != SC_OWNID) && 607 (sc->sel_stat[sc->ipc] == SEL_SUCCESS)) { 608 if (sc->int_stat2 & R3_PHC) { 609 /* 610 * Phase change 611 */ 612 sc->int_stat2 &= ~(R3_PHC|R3_RMSG); 613 sc_pmatch(sc); 614 } else if (sc->int_stat2 & R3_RMSG) { 615 /* 616 * message Phase 617 */ 618 if (sc->min_flag > 0) { 619 sc->int_stat2 &= ~(R3_PHC|R3_RMSG); 620 sc_pmatch(sc); 621 } 622 } 623 else if (sc->dma_stat != OFF) { 624 dummy = sc_cmonr; 625 DMAC_WAIT0; 626 if ((dummy & (R4_MMSG|R4_MCD|R4_MREQ)) == R4_MREQ) { 627 /* 628 * still DATA transfer phase 629 */ 630 sc_dio_pad(sc, sc->ip); 631 } 632 } 633 else if (sc->ip->comflg == CF_SEND) { 634 dummy = sc_cmonr; 635 DMAC_WAIT0; 636 if ((dummy & SC_PMASK) == COM_OUT) { 637 /* 638 * command out phase 639 */ 640 sc_cout(sc, sc->ip); 641 } 642 } 643 } else { 644 if (sc->int_stat2 & (R3_PHC|R3_RMSG)) 645 goto scintr_exit; 646 } 647 648 if ((sc->int_stat1 & (R2_STO|R2_RSL|R2_ARBF)) 649 || (sc->int_stat2 & (R3_DCNT|R3_SRST|R3_PHC|R3_SPE))) { 650 /* 651 * still remain intrq 652 */ 653 goto scintr_loop; 654 } 655 656 scintr_exit: 657 return (1); 658 } 659 660 /* 661 * SCSI bus reset routine 662 * scsi_hardreset() is occered a reset interrupt. 663 * And call scsi_softreset(). 664 */ 665 void 666 scsi_hardreset() 667 { 668 register int s; 669 #ifdef DMAC_MAP_INIT 670 register int i; 671 #endif 672 struct sc_softc *sc; 673 674 sc = sc_cd.cd_devs[0]; /* XXX */ 675 s = splscsi(); 676 677 scsi_chipreset(sc); 678 DMAC_WAIT0; 679 sc->int_stat1 = 0; 680 sc->int_stat2 = 0; 681 SET_CMD(sc, SCMD_AST_RST); /* assert RST signal */ 682 683 #ifdef DMAC_MAP_INIT 684 if (dmac_map_init == 0) { 685 dmac_map_init++; 686 for (i = 0; i < NDMACMAP; i++) { 687 # if defined(__mips__) && defined(CPU_SINGLE) 688 dmac_gsel = CH_SCSI; 689 dmac_ctag = (u_char)i; 690 dmac_cmap = (u_short)0; 691 # endif 692 } 693 } 694 #endif 695 /*cxd1185_init();*/ 696 splx(s); 697 } 698 699 /* 700 * I/O port (sc_ioptr) bit assign 701 * 702 * Rf_PRT3 - <reserved> 703 * Rf_PRT2 - <reserved> 704 * Rf_PRT1 out Floppy Disk Density control 705 * Rf_PRT0 out Floppy Disk Eject control 706 */ 707 708 void 709 scsi_chipreset(sc) 710 struct sc_softc *sc; 711 { 712 register int s; 713 register VOLATILE int save_ioptr; 714 715 s = splscsi(); 716 717 #if defined(__mips__) && defined(CPU_SINGLE) 718 dmac_gsel = CH_SCSI; 719 dmac_cwid = 4; /* initialize DMAC SCSI chan */ 720 *(unsigned VOLATILE char *)PINTEN |= DMA_INTEN; 721 dma_reset(CH_SCSI); 722 #endif 723 sc_envir = 0; /* 1/4 clock */ 724 DMAC_WAIT0; 725 save_ioptr = sc_ioptr; 726 DMAC_WAIT0; 727 sc->lastcmd = SCMD_CHIP_RST; 728 sc_comr = SCMD_CHIP_RST; /* reset chip */ 729 DMAC_WAIT; 730 (void) WAIT_STATR_BITCLR(R0_CIP); 731 /* 732 * SCMD_CHIP_RST command reset all register 733 * except sc_statr<7:6> & sc_cmonr. 734 * So, bit R0_MIRQ & R3_FNC will be not set. 735 */ 736 sc_idenr = SC_OWNID; 737 DMAC_WAIT0; 738 739 sc_intok1 = Ra_STO|Ra_RSL|Ra_ARBF; 740 DMAC_WAIT0; 741 sc_intok2 = Rb_FNC|Rb_SRST|Rb_PHC|Rb_SPE|Rb_RMSG; 742 DMAC_WAIT0; 743 744 sc_ioptr = save_ioptr; 745 DMAC_WAIT; 746 747 sc_moder = Rc_TMSL; /* RST drive time = 25.5 us */ 748 DMAC_WAIT0; 749 sc_timer = 0x2; 750 DMAC_WAIT0; 751 752 sc_moder = Rc_SPHI; /* selection timeout = 252 ms */ 753 DMAC_WAIT0; 754 sc_timer = SEL_TIMEOUT_VALUE; 755 DMAC_WAIT0; 756 757 #ifdef SCSI_1185AQ 758 if (sc->scsi_1185AQ) 759 SET_CMD(sc, SCMD_ENB_SEL); /* enable reselection */ 760 #endif 761 762 sc->int_stat1 &= ~R2_RSL; /* ignore RSL inter request */ 763 764 splx(s); 765 } 766 767 void 768 scsi_softreset(sc) 769 struct sc_softc *sc; 770 { 771 register VOLATILE struct sc_chan_stat *cs; 772 int i; 773 /* register int (*handler)(); */ 774 775 sc->wbq_actf = NULL; 776 sc->wbq_actl = NULL; 777 sc->wbc = 0; 778 sc->wrc = 0; 779 sc->ip = NULL; 780 sc->ipc = -1; 781 sc->dma_stat = OFF; 782 sc->pad_start = 0; 783 784 for (i = 0; i < NTARGET; ++i) { 785 if (i == SC_OWNID) 786 continue; 787 cs = &sc->chan_stat[i]; 788 cs->wb_next = NULL; 789 #ifndef NOT_SUPPORT_SYNCTR 790 sc->sync_tr[i] = 0; /* asynchronous mode */ 791 #endif 792 sc->sel_stat[i] = SEL_WAIT; 793 if (cs->scb != NULL) { 794 struct sc_scb *scb = cs->scb; 795 796 if ((cs->scb->istatus & INST_EP) == 0) 797 cs->scb->istatus = (INST_EP|INST_HE); 798 cs->scb = NULL; 799 #ifdef __mips__ 800 clean_k2dcache(scb); 801 #endif 802 if (cs->intr_flg == SCSI_INTEN) { 803 intrcnt[SCSI_INTR]++; 804 #if 0 805 handler = scintsw[i].sci_inthandler; 806 if (handler) 807 (*handler)(scintsw[i].sci_ctlr); 808 #endif 809 } 810 sc_done(scb); 811 } 812 } 813 } 814 815 /* 816 * RESELECTION interrupt service routine 817 * ( RESELECTION phase ) 818 */ 819 void 820 sc_resel(sc) 821 struct sc_softc *sc; 822 { 823 register struct sc_chan_stat *cs; 824 register VOLATILE int chan; 825 register VOLATILE int statr; 826 register int iloop; 827 828 sc->min_flag = 0; 829 chan = (sc_idenr & R6_SID_MASK) >> SC_TG_SHIFT; 830 831 if (chan == SC_OWNID) 832 return; 833 834 statr = sc_statr; 835 DMAC_WAIT0; 836 if (statr & R0_CIP) { 837 if (sc->lastcmd == SCMD_SEL_ATN) { 838 /* 839 * SELECTION command dead lock ? 840 * save interrupt request 841 */ 842 while (sc_statr & R0_MIRQ) { 843 DMAC_WAIT0; 844 sc->int_stat1 |= sc_intrq1; 845 DMAC_WAIT0; 846 sc->int_stat2 |= sc_intrq2; 847 DMAC_WAIT0; 848 } 849 scsi_chipreset(sc); 850 } 851 } 852 853 cs = &sc->chan_stat[chan]; 854 if (cs->scb == NULL) { 855 scsi_hardreset(); 856 return; 857 } 858 if ((cs->scb->istatus & INST_WR) == 0) { 859 scsi_hardreset(); 860 return; 861 } 862 863 if (sc->ipc >= 0) { 864 scsi_hardreset(); 865 return; 866 } 867 868 sc->ip = cs; 869 sc->ipc = chan; 870 871 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE; 872 DMAC_WAIT0; 873 874 iloop = 0; 875 while ((sc->int_stat2 & R3_FNC) == 0) { 876 /* 877 * Max 6 usec wait 878 */ 879 if (iloop++ > RSL_LOOP_CNT) { 880 sc->sel_stat[chan] = SEL_RSL_WAIT; 881 return; 882 } 883 GET_INTR(&sc->int_stat1, &sc->int_stat2); 884 } 885 sc->int_stat2 &= ~R3_FNC; 886 887 sc->sel_stat[chan] = SEL_SUCCESS; 888 889 sc->wrc--; 890 sc->dma_stat = OFF; 891 sc->pad_start = 0; 892 cs->scb->istatus |= INST_IP; 893 cs->scb->istatus &= ~INST_WR; 894 895 #ifndef NOT_SUPPORT_SYNCTR 896 sc_syncr = sc->sync_tr[chan]; 897 DMAC_WAIT0; 898 #endif 899 } 900 901 /* 902 * DISCONNECT interrupt service routine 903 * ( Target disconnect / job done ) 904 */ 905 void 906 sc_discon(sc) 907 struct sc_softc *sc; 908 { 909 register VOLATILE struct sc_chan_stat *cs; 910 /* register int (*handler)(); */ 911 register VOLATILE int dummy; 912 913 /* 914 * Signal reflection on BSY has occurred. 915 * Not Bus Free Phase, ignore. 916 * 917 * But, CXD1185Q reset INIT bit of sc_statr. 918 * So, can't issue Transfer Information command. 919 * 920 * What shall we do ? Bus reset ? 921 */ 922 if ((sc->int_stat2 & R3_DCNT) && ((sc_intok2 & Rb_DCNT) == 0)) 923 return; 924 925 sc_intok2 = Rb_FNC|Rb_SRST|Rb_PHC|Rb_SPE; 926 DMAC_WAIT0; 927 928 sc->min_flag = 0; 929 dummy = sc_cmonr; 930 DMAC_WAIT0; 931 if (dummy & R4_MATN) { 932 SET_CMD(sc, SCMD_NGT_ATN); 933 (void) WAIT_STATR_BITSET(R0_MIRQ); 934 GET_INTR(&sc->int_stat1, &sc->int_stat2); /* clear interrupt */ 935 } 936 937 if ((sc->int_stat1 & R2_RSL) == 0) 938 sc->int_stat2 &= ~R3_FNC; 939 940 cs = sc->ip; 941 if ((cs == NULL) || (sc->ipc < 0)) 942 goto sc_discon_exit; 943 944 if ((sc->sel_stat[cs->chan_num] != SEL_SUCCESS) 945 && (sc->sel_stat[cs->chan_num] != SEL_TIMEOUT)) 946 printf("sc_discon: eh!\n"); 947 948 /* 949 * indicate abnormal terminate 950 */ 951 if ((cs->scb->istatus & (INST_EP|INST_WR)) == 0) 952 cs->scb->istatus |= (INST_EP|INST_PRE|INST_LB); 953 954 cs->scb->istatus &= ~INST_IP; 955 sc->dma_stat = OFF; 956 sc->pad_start = 0; 957 sc->ip = NULL; 958 sc->ipc = -1; 959 960 if ((cs->scb->istatus & INST_WR) == 0) { 961 struct sc_scb *scb = cs->scb; 962 963 if (sc->perr_flag[cs->chan_num] > 0) 964 cs->scb->istatus |= INST_EP|INST_PRE; 965 cs->scb = NULL; 966 #ifdef __mips__ 967 clean_k2dcache(scb); 968 #endif 969 if (cs->intr_flg == SCSI_INTEN) { 970 intrcnt[SCSI_INTR]++; 971 #if 0 972 handler = scintsw[cs->chan_num].sci_inthandler; 973 if (handler) 974 (*handler)(scintsw[cs->chan_num].sci_ctlr); 975 #endif 976 } 977 sc_done(scb); 978 } 979 980 sc_discon_exit: 981 sc_start(sc); 982 } 983 984 /* 985 * SCSI phase match interrupt service routine 986 */ 987 void 988 sc_pmatch(sc) 989 struct sc_softc *sc; 990 { 991 struct sc_chan_stat *cs; 992 register VOLATILE int phase; 993 register VOLATILE int phase2; 994 register VOLATILE int cmonr; 995 996 sc->int_stat2 &= ~R3_FNC; /* XXXXXXXX */ 997 998 cs = sc->ip; 999 if (cs == NULL) 1000 return; 1001 1002 #if defined(__mips__) && defined(CPU_SINGLE) 1003 dma_reset(CH_SCSI); 1004 #endif 1005 phase = sc_cmonr & SC_PMASK; 1006 DMAC_WAIT0; 1007 for (;;) { 1008 phase2 = phase; 1009 cmonr = sc_cmonr; 1010 DMAC_WAIT0; 1011 phase = cmonr & SC_PMASK; 1012 if (phase == phase2) { 1013 if ((phase == DAT_IN) || (phase == DAT_OUT)) 1014 break; 1015 else if (cmonr & R4_MREQ) 1016 break; 1017 } 1018 } 1019 1020 1021 sc->dma_stat = OFF; 1022 sc->pad_start = 0; 1023 1024 if (phase == COM_OUT) { 1025 sc->min_flag = 0; 1026 if (cs->comflg != CF_SEND) 1027 cs->comflg = CF_SET; 1028 sc_cout(sc, cs); 1029 } else { 1030 cs->comflg = CF_ENOUGH; 1031 sc_intok2 &= ~Rb_FNC; 1032 if (phase == MES_IN) { 1033 sc->min_flag++; 1034 sc_min(sc, cs); 1035 } else { 1036 sc->min_flag = 0; 1037 1038 switch (phase) { 1039 1040 case MES_OUT: 1041 sc_mout(sc, cs); 1042 break; 1043 1044 case DAT_IN: 1045 case DAT_OUT: 1046 sc_dio(sc, cs); 1047 break; 1048 1049 case STAT_IN: 1050 sc_sin(sc, cs); 1051 break; 1052 1053 default: 1054 printf("SCSI%d: unknown phase\n", cs->chan_num); 1055 break; 1056 } 1057 } 1058 } 1059 } 1060 1061 1062 void 1063 flush_fifo(sc) 1064 struct sc_softc *sc; 1065 { 1066 register VOLATILE int dummy; 1067 VOLATILE int tmp; 1068 VOLATILE int tmp0; 1069 1070 dummy = sc_ffstr; 1071 DMAC_WAIT0; 1072 if (dummy & R5_FIFOREM) { 1073 /* 1074 * flush FIFO 1075 */ 1076 SET_CMD(sc, SCMD_FLSH_FIFO); 1077 tmp = 0; 1078 do { 1079 do { 1080 dummy = sc_statr; 1081 DMAC_WAIT0; 1082 } while (dummy & R0_CIP); 1083 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1084 } while ((tmp & R3_FNC) == 0); 1085 } 1086 } 1087 1088 /* 1089 * SCSI command send routine 1090 */ 1091 void 1092 sc_cout(sc, cs) 1093 struct sc_softc *sc; 1094 register struct sc_chan_stat *cs; 1095 { 1096 register int iloop; 1097 register int cdb_bytes; 1098 register VOLATILE int dummy; 1099 register VOLATILE int statr; 1100 struct scsipi_xfer *xs; 1101 1102 if (cs->comflg == CF_SET) { 1103 struct sc_scb *scb = cs->scb; 1104 1105 cs->comflg = CF_SEND; 1106 1107 flush_fifo(sc); 1108 1109 xs = scb->xs; 1110 cdb_bytes = xs->cmdlen; 1111 1112 switch (xs->cmd->opcode & CMD_TYPEMASK) { 1113 case CMD_T0: 1114 case CMD_T1: 1115 case CMD_T5: 1116 break; 1117 1118 default: 1119 cdb_bytes = 6; 1120 sc_intok2 |= Rb_FNC; 1121 break; 1122 } 1123 1124 /* 1125 * set Active pointers 1126 */ 1127 sc->act_cmd_pointer = (char *)xs->cmd; 1128 cs->act_trcnt = scb->sc_ctrnscnt; 1129 cs->act_point = scb->sc_cpoint; 1130 cs->act_tag = scb->sc_ctag; 1131 cs->act_offset = scb->sc_coffset; 1132 1133 } else { 1134 cdb_bytes = 1; 1135 iloop = 0; 1136 do { 1137 dummy = sc_cmonr; 1138 DMAC_WAIT0; 1139 if ((dummy & SC_PMASK) != COM_OUT) 1140 return; 1141 statr = sc_statr; 1142 DMAC_WAIT0; 1143 if (statr & R0_MIRQ) 1144 return; 1145 } while ((dummy & R4_MREQ) == 0); 1146 statr = sc_statr; 1147 DMAC_WAIT0; 1148 if (statr & R0_MIRQ) 1149 return; 1150 } 1151 1152 1153 SET_CNT(cdb_bytes); 1154 SET_CMD(sc, SCMD_TR_INFO|R0_TRBE); 1155 1156 for (iloop = 0; iloop < cdb_bytes; iloop++) { 1157 do { 1158 dummy = sc_cmonr; 1159 DMAC_WAIT0; 1160 if ((dummy & SC_PMASK) != COM_OUT) 1161 return; 1162 } while ((dummy & R4_MREQ) == 0); 1163 statr = sc_statr; 1164 DMAC_WAIT0; 1165 if (statr & R0_MIRQ) 1166 return; 1167 sc_datr = *sc->act_cmd_pointer++; 1168 do { 1169 dummy = sc_cmonr; 1170 DMAC_WAIT0; 1171 } while ((dummy & R4_MACK) != 0); 1172 } 1173 } 1174 1175 #define GET_MIN_COUNT 127 1176 1177 /* 1178 * SCSI message accept routine 1179 */ 1180 void 1181 sc_min(sc, cs) 1182 struct sc_softc *sc; 1183 register struct sc_chan_stat *cs; 1184 { 1185 struct sc_scb *scb = cs->scb; 1186 struct scsipi_xfer *xs = scb->xs; 1187 register VOLATILE int dummy; 1188 1189 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE|Rb_RMSG; 1190 DMAC_WAIT0; 1191 1192 if (sc->min_flag == 1) 1193 flush_fifo(sc); 1194 1195 dummy = sc_cmonr; 1196 DMAC_WAIT0; 1197 if ((dummy & R4_MREQ) == 0) { 1198 printf("sc_min: !REQ cmonr=%x\n", dummy); 1199 print_scsi_stat(sc); 1200 scsi_hardreset(); 1201 return; 1202 } 1203 1204 /* retry_cmd_issue: */ 1205 sc->int_stat2 &= ~R3_FNC; 1206 SET_CMD(sc, SCMD_TR_INFO); 1207 do { 1208 do { 1209 dummy = sc_statr; 1210 DMAC_WAIT0; 1211 } while (dummy & R0_CIP); 1212 GET_INTR(&sc->int_stat1, &sc->int_stat2); /* clear interrupt */ 1213 } while ((sc->int_stat2 & R3_FNC) == 0); 1214 sc->int_stat2 &= ~R3_FNC; 1215 1216 dummy = sc_ffstr; 1217 if (dummy & R5_FIE) { 1218 DMAC_WAIT; 1219 dummy = sc_ffstr; 1220 DMAC_WAIT0; 1221 if (dummy & R5_FIE) { 1222 dummy = sc_statr; 1223 DMAC_WAIT0; 1224 if ((dummy & R0_INIT) == 0) { 1225 /* 1226 * CXD1185 detect BSY false 1227 */ 1228 scsi_hardreset(); 1229 return; 1230 } 1231 } 1232 } 1233 dummy = sc_datr; /* get message byte */ 1234 DMAC_WAIT0; 1235 1236 if (sc->min_cnt[cs->chan_num] == 0) { 1237 scb->message = scb->identify; 1238 if (dummy == MSG_EXTND) { 1239 /* Extended Message */ 1240 sc->min_cnt[cs->chan_num] = GET_MIN_COUNT; 1241 sc->min_point[cs->chan_num] = scb->msgbuf; 1242 bzero(scb->msgbuf, 8); 1243 *sc->min_point[cs->chan_num]++ = dummy; 1244 } else { 1245 switch ((dummy & MSG_IDENT)? MSG_IDENT : dummy) { 1246 1247 case MSG_CCOMP: 1248 scb->istatus |= INST_EP; 1249 break; 1250 1251 case MSG_MREJ: 1252 #ifndef NOT_SUPPORT_SYNCTR 1253 if (sc->mout_flag[cs->chan_num] == MOUT_SYNC_TR) 1254 sc->sync_tr[cs->chan_num] = 0; 1255 #endif 1256 break; 1257 1258 case MSG_IDENT: 1259 case MSG_RDP: 1260 1261 sc->dma_stat = OFF; 1262 sc->pad_start = 0; 1263 cs->comflg = OFF; 1264 /* 1265 * restore the saved value to Active pointers 1266 */ 1267 sc->act_cmd_pointer = (char *)xs->cmd; 1268 cs->act_trcnt = scb->sc_ctrnscnt; 1269 cs->act_point = scb->sc_cpoint; 1270 cs->act_tag = scb->sc_ctag; 1271 cs->act_offset = scb->sc_coffset; 1272 break; 1273 1274 case MSG_SDP: 1275 /* 1276 * save Active pointers 1277 */ 1278 scb->sc_ctrnscnt = cs->act_trcnt; 1279 scb->sc_ctag = cs->act_tag; 1280 scb->sc_coffset = cs->act_offset; 1281 scb->sc_cpoint = cs->act_point; 1282 break; 1283 1284 case MSG_DCNT: 1285 scb->istatus |= INST_WR; 1286 sc->wrc++; 1287 break; 1288 1289 default: 1290 scb->message = MSG_MREJ; 1291 SET_CMD(sc, SCMD_AST_ATN); 1292 printf("SCSI%d:sc_min() Unknown mes=0x%x, \n", 1293 cs->chan_num, dummy); 1294 } 1295 } 1296 } else { 1297 *sc->min_point[cs->chan_num]++ = dummy; 1298 if (sc->min_cnt[cs->chan_num] == GET_MIN_COUNT) 1299 sc->min_cnt[cs->chan_num] = dummy; 1300 else 1301 sc->min_cnt[cs->chan_num]--; 1302 if (sc->min_cnt[cs->chan_num] <= 0) { 1303 #ifdef ABORT_SYNCTR_MES_FROM_TARGET 1304 if ((scb->msgbuf[2] == 0x01) && 1305 (sc->mout_flag[cs->chan_num] == MOUT_SYNC_TR)) { 1306 #else 1307 if (scb->msgbuf[2] == 0x01) { 1308 #endif 1309 register int i; 1310 /* 1311 * receive Synchronous transfer message reply 1312 * calculate transfer period val 1313 * tpm * 4/1000 us = 4/16 * (tpv + 1) 1314 */ 1315 #define TPM2TPV(tpm) (((tpm)*16 + 999) / 1000 - 1) 1316 #ifndef NOT_SUPPORT_SYNCTR 1317 i = scb->msgbuf[3]; /* get tpm */ 1318 i = TPM2TPV(i) << 4; 1319 if (scb->msgbuf[4] == 0) 1320 sc->sync_tr[cs->chan_num] = 0; 1321 else 1322 sc->sync_tr[cs->chan_num] = 1323 i | scb->msgbuf[4]; 1324 #endif /* !NOT_SUPPORT_SYNCTR */ 1325 } else { 1326 scb->message = MSG_MREJ; 1327 SET_CMD(sc, SCMD_AST_ATN); /* assert ATN */ 1328 } 1329 } 1330 } 1331 SET_CMD(sc, SCMD_NGT_ACK); 1332 } 1333 1334 /* 1335 * SCSI message send routine 1336 */ 1337 void 1338 sc_mout(sc, cs) 1339 struct sc_softc *sc; 1340 register struct sc_chan_stat *cs; 1341 { 1342 register struct sc_scb *scb = cs->scb; 1343 register u_char *mp; 1344 register int cnt; 1345 register int iloop; 1346 register VOLATILE int dummy; 1347 VOLATILE int tmp; 1348 VOLATILE int tmp0; 1349 1350 flush_fifo(sc); 1351 1352 if (sc->mout_flag[cs->chan_num] == 0) { 1353 sc->mout_flag[cs->chan_num] = MOUT_IDENTIFY; 1354 if (scb->message != 0) { 1355 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE|Rb_RMSG; 1356 DMAC_WAIT0; 1357 if ((scb->message == MSG_EXTND) 1358 && (scb->msgbuf[2] == 0x01)) { 1359 cnt = 5; 1360 mp = scb->msgbuf; 1361 scb->msgbuf[3] = MIN_TP; 1362 if (scb->msgbuf[4] > MAX_OFFSET_BYTES) 1363 scb->msgbuf[4] = MAX_OFFSET_BYTES; 1364 sc->mout_flag[cs->chan_num] = MOUT_SYNC_TR; 1365 } else { 1366 cnt = 1; 1367 mp = &scb->message; 1368 } 1369 1370 SET_CNT(cnt); 1371 SET_CMD(sc, SCMD_TR_INFO|R0_TRBE); 1372 sc_datr = scb->identify; 1373 DMAC_WAIT0; 1374 for (iloop = 1; iloop < cnt; iloop++) { 1375 sc_datr = *mp++; 1376 DMAC_WAIT; 1377 } 1378 do { 1379 dummy = sc_cmonr; 1380 DMAC_WAIT0; 1381 if ((dummy & R4_MBSY) == 0) 1382 return; 1383 dummy = sc_statr; 1384 DMAC_WAIT0; 1385 } while (dummy & R0_CIP); 1386 1387 tmp = 0; 1388 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1389 if ((tmp & R3_FNC) == 0) { 1390 (void) WAIT_STATR_BITSET(R0_MIRQ); 1391 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1392 } 1393 1394 do { 1395 dummy = sc_cmonr; 1396 DMAC_WAIT0; 1397 if ((dummy & R4_MBSY) == 0) 1398 return; 1399 } while ((dummy & R4_MREQ) == 0); 1400 SET_CMD(sc, SCMD_NGT_ATN); 1401 (void) WAIT_STATR_BITCLR(R0_CIP); 1402 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1403 1404 dummy = sc_cmonr; 1405 DMAC_WAIT0; 1406 if ((dummy & R4_MREQ) == 0) { 1407 printf("sc_mout: !REQ cmonr=%x\n", dummy); 1408 print_scsi_stat(sc); 1409 scsi_hardreset(); 1410 return; 1411 } 1412 1413 SET_CMD(sc, SCMD_TR_INFO); 1414 sc_datr = *mp++; 1415 DMAC_WAIT0; 1416 } else { 1417 dummy = sc_cmonr; 1418 DMAC_WAIT0; 1419 if (dummy & R4_MATN) { 1420 SET_CMD(sc, SCMD_NGT_ATN); 1421 (void) WAIT_STATR_BITCLR(R0_CIP); 1422 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1423 } 1424 1425 iloop = 0; 1426 do { 1427 dummy = sc_cmonr; 1428 DMAC_WAIT0; 1429 if (iloop++ > CHECK_LOOP_CNT) 1430 break; 1431 } while ((dummy & R4_MREQ) == 0); 1432 SET_CMD(sc, SCMD_TR_INFO); 1433 sc_datr = scb->identify; 1434 DMAC_WAIT0; 1435 } 1436 } else { 1437 dummy = sc_cmonr; 1438 DMAC_WAIT0; 1439 if (dummy & R4_MATN) { 1440 SET_CMD(sc, SCMD_NGT_ATN); 1441 (void) WAIT_STATR_BITCLR(R0_CIP); 1442 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1443 } 1444 1445 dummy = sc_cmonr; 1446 DMAC_WAIT0; 1447 if ((dummy & R4_MREQ) == 0) { 1448 printf("sc_mout: !REQ cmonr=%x\n", dummy); 1449 print_scsi_stat(sc); 1450 scsi_hardreset(); 1451 return; 1452 } 1453 1454 SET_CMD(sc, SCMD_TR_INFO); 1455 sc_datr = scb->message; 1456 DMAC_WAIT0; 1457 } 1458 } 1459 1460 /* 1461 * SCSI status accept routine 1462 */ 1463 void 1464 sc_sin(sc, cs) 1465 struct sc_softc *sc; 1466 register VOLATILE struct sc_chan_stat *cs; 1467 { 1468 register VOLATILE int dummy; 1469 register int iloop; 1470 1471 flush_fifo(sc); 1472 1473 dummy = sc_cmonr; 1474 DMAC_WAIT0; 1475 if ((dummy & R4_MREQ) == 0) { 1476 printf("sc_sin: !REQ cmonr=%x\n", dummy); 1477 print_scsi_stat(sc); 1478 scsi_hardreset(); 1479 return; 1480 } 1481 1482 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE|Rb_RMSG; 1483 DMAC_WAIT0; 1484 1485 SET_CMD(sc, SCMD_TR_INFO); 1486 1487 (void) WAIT_STATR_BITCLR(R0_CIP); 1488 1489 sc->int_stat2 &= ~R3_FNC; 1490 iloop = 0; 1491 do { 1492 if (iloop++ > CHECK_LOOP_CNT) 1493 break; 1494 GET_INTR(&sc->int_stat1, &sc->int_stat2); /* clear interrupt */ 1495 } while ((sc->int_stat2 & R3_FNC) == 0); 1496 sc->int_stat2 &= ~R3_FNC; 1497 1498 cs->scb->tstatus = sc_datr; /* get status byte */ 1499 DMAC_WAIT0; 1500 } 1501 1502 /* 1503 * SCSI data in/out routine 1504 */ 1505 void 1506 sc_dio(sc, cs) 1507 struct sc_softc *sc; 1508 register VOLATILE struct sc_chan_stat *cs; 1509 { 1510 register VOLATILE struct sc_scb *scb; 1511 register int i; 1512 register int pages; 1513 register u_int tag; 1514 register u_int pfn; 1515 VOLATILE int phase; 1516 struct scsipi_xfer *xs; 1517 1518 scb = cs->scb; 1519 xs = scb->xs; 1520 1521 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE; 1522 DMAC_WAIT0; 1523 1524 if (cs->act_trcnt <= 0) { 1525 sc_dio_pad(sc, cs); 1526 return; 1527 } 1528 1529 switch (xs->cmd->opcode) { 1530 1531 case SCOP_READ: 1532 case SCOP_WRITE: 1533 case SCOP_EREAD: 1534 case SCOP_EWRITE: 1535 i = (cs->act_trcnt + DEV_BSIZE -1) / DEV_BSIZE; 1536 i *= DEV_BSIZE; 1537 break; 1538 1539 default: 1540 i = cs->act_trcnt; 1541 break; 1542 } 1543 1544 SET_CNT(i); 1545 sc->pad_cnt[cs->chan_num] = i - cs->act_trcnt; 1546 1547 phase = sc_cmonr & SC_PMASK; 1548 DMAC_WAIT0; 1549 if (phase == DAT_IN) { 1550 if (sc_syncr == OFF) { 1551 DMAC_WAIT0; 1552 flush_fifo(sc); 1553 } 1554 } 1555 1556 #if defined(__mips__) && defined(CPU_SINGLE) 1557 SET_CMD(sc, SCMD_TR_INFO|R0_DMA|R0_TRBE); 1558 #endif 1559 1560 #if defined(__mips__) && defined(CPU_SINGLE) 1561 dmac_gsel = CH_SCSI; 1562 dmac_ctrcl = (u_char)(cs->act_trcnt & 0xff); 1563 dmac_ctrcm = (u_char)((cs->act_trcnt >> 8) & 0xff); 1564 dmac_ctrch = (u_char)((cs->act_trcnt >> 16) & 0x0f); 1565 dmac_cofsh = (u_char)((cs->act_offset >> 8) & 0xf); 1566 dmac_cofsl = (u_char)(cs->act_offset & 0xff); 1567 #endif 1568 tag = 0; 1569 1570 if (scb->sc_map && (scb->sc_map->mp_pages > 0)) { 1571 /* 1572 * Set DMAC map entry from map table 1573 */ 1574 pages = scb->sc_map->mp_pages; 1575 for (i = cs->act_tag; i < pages; i++) { 1576 if ((pfn = scb->sc_map->mp_addr[i]) == 0) 1577 panic("SCSI:sc_dma() zero entry"); 1578 #if defined(__mips__) && defined(CPU_SINGLE) 1579 dmac_gsel = CH_SCSI; 1580 dmac_ctag = (u_char)tag++; 1581 dmac_cmap = (u_short)pfn; 1582 #endif 1583 } 1584 #ifdef MAP_OVER_ACCESS 1585 # if defined(__mips__) && defined(CPU_SINGLE) 1586 dmac_gsel = CH_SCSI; 1587 dmac_ctag = (u_char)tag++; 1588 dmac_cmap = (u_short)pfn; 1589 # endif 1590 #endif 1591 } else { 1592 /* 1593 * Set DMAC map entry from logical address 1594 */ 1595 pfn = kvtophys((vaddr_t)cs->act_point) >> PGSHIFT; 1596 pages = (cs->act_trcnt >> PGSHIFT) + 2; 1597 for (i = 0; i < pages; i++) { 1598 #if defined(__mips__) && defined(CPU_SINGLE) 1599 dmac_gsel = CH_SCSI; 1600 dmac_ctag = (u_char)tag++; 1601 dmac_cmap = (u_short)pfn + i; 1602 #endif 1603 } 1604 } 1605 1606 #if defined(__mips__) && defined(CPU_SINGLE) 1607 dmac_gsel = CH_SCSI; 1608 dmac_ctag = 0; 1609 #endif 1610 1611 if (phase == DAT_IN) { 1612 sc->dma_stat = SC_DMAC_RD; 1613 #if defined(__mips__) && defined(CPU_SINGLE) 1614 /* 1615 * auto pad flag is always on 1616 */ 1617 dmac_gsel = CH_SCSI; 1618 dmac_cctl = DM_MODE|DM_APAD; 1619 DMAC_WAIT; 1620 dmac_cctl = DM_MODE|DM_APAD|DM_ENABLE; 1621 DMAC_WAIT0; 1622 #endif 1623 } 1624 else if (phase == DAT_OUT) { 1625 sc->dma_stat = SC_DMAC_WR; 1626 #if defined(__mips__) && defined(CPU_SINGLE) 1627 dmac_gsel = CH_SCSI; 1628 dmac_cctl = DM_APAD; 1629 DMAC_WAIT; 1630 dmac_cctl = DM_APAD|DM_ENABLE; 1631 DMAC_WAIT0; 1632 #endif 1633 /* DMAC start on mem->I/O */ 1634 } 1635 } 1636 1637 #define MAX_TR_CNT24 ((1 << 24) -1) 1638 void 1639 sc_dio_pad(sc, cs) 1640 struct sc_softc *sc; 1641 register VOLATILE struct sc_chan_stat *cs; 1642 { 1643 register int dummy; 1644 1645 if (cs->act_trcnt >= 0) 1646 return; 1647 sc->pad_start = 1; 1648 1649 SET_CNT(MAX_TR_CNT24); 1650 SET_CMD(sc, SCMD_TR_PAD|R0_TRBE); 1651 dummy = sc_cmonr & SC_PMASK; 1652 DMAC_WAIT0; 1653 if (dummy == DAT_IN) 1654 dummy = sc_datr; /* get data */ 1655 else 1656 sc_datr = 0; /* send data */ 1657 } 1658 1659 void 1660 print_scsi_stat(sc) 1661 struct sc_softc *sc; 1662 { 1663 printf("ipc=%d wrc=%d wbc=%d\n", sc->ipc, sc->wrc, sc->wbc); 1664 } 1665 1666 /* 1667 * return 0 if it was done. Or retun TRUE if it is busy. 1668 */ 1669 int 1670 sc_busy(sc, chan) 1671 struct sc_softc *sc; 1672 register int chan; 1673 { 1674 return ((int)sc->chan_stat[chan].scb); 1675 } 1676 1677 1678 /* 1679 * append channel into Waiting Bus_free queue 1680 */ 1681 void 1682 append_wb(sc, cs) 1683 struct sc_softc *sc; 1684 struct sc_chan_stat *cs; 1685 { 1686 int s; 1687 1688 s = splclock(); /* inhibit process switch */ 1689 if (sc->wbq_actf == NULL) 1690 sc->wbq_actf = cs; 1691 else 1692 sc->wbq_actl->wb_next = cs; 1693 sc->wbq_actl = cs; 1694 cs->scb->istatus = INST_WAIT; 1695 sc->wbc++; 1696 splx(s); 1697 } 1698 1699 /* 1700 * get channel from Waiting Bus_free queue 1701 */ 1702 struct sc_chan_stat * 1703 get_wb_chan(sc) 1704 struct sc_softc *sc; 1705 { 1706 struct sc_chan_stat *cs; 1707 int s; 1708 1709 s = splclock(); /* inhibit process switch */ 1710 cs = sc->wbq_actf; 1711 if (cs && cs->chan_num == SC_OWNID) /* needed? */ 1712 cs = NULL; 1713 splx(s); 1714 return cs; 1715 } 1716 1717 /* 1718 * release channel from Waiting Bus_free queue 1719 */ 1720 int 1721 release_wb(sc) 1722 struct sc_softc *sc; 1723 { 1724 struct sc_chan_stat *cs; 1725 int error = 0; 1726 int s; 1727 1728 s = splclock(); /* inhibit process switch */ 1729 if (sc->wbq_actf == NULL) { 1730 error = -1; 1731 } else { 1732 cs = sc->wbq_actf; 1733 sc->wbq_actf = cs->wb_next; 1734 cs->wb_next = NULL; 1735 if (sc->wbq_actl == cs) 1736 sc->wbq_actl = NULL; 1737 cs->scb->istatus &= ~INST_WAIT; 1738 sc->wbc--; 1739 } 1740 splx(s); 1741 return error; 1742 } 1743 1744 void 1745 adjust_transfer(sc, cs) 1746 struct sc_softc *sc; 1747 struct sc_chan_stat *cs; 1748 { 1749 struct sc_scb *scb = cs->scb; 1750 u_int remain_cnt; 1751 u_int offset, sent_byte; 1752 1753 if (sc->pad_start) { 1754 sc->pad_start = 0; 1755 remain_cnt = 0; 1756 } else { 1757 # if defined(__mips__) && defined(CPU_SINGLE) 1758 remain_cnt = GET_CNT(); 1759 remain_cnt -= sc->pad_cnt[cs->chan_num]; 1760 if (sc->dma_stat == SC_DMAC_WR) { 1761 /* 1762 * adjust counter in the FIFO 1763 */ 1764 remain_cnt += sc_ffstr & R5_FIFOREM; 1765 } 1766 # endif 1767 } 1768 1769 sent_byte = scb->sc_ctrnscnt - remain_cnt; 1770 cs->act_trcnt = remain_cnt; 1771 1772 offset = scb->sc_coffset + sent_byte; 1773 cs->act_tag += (offset >> PGSHIFT); 1774 cs->act_offset = offset & PGOFSET; 1775 if ((scb->sc_map == NULL) || (scb->sc_map->mp_pages <= 0)) 1776 cs->act_point += sent_byte; 1777 } 1778 1779 #ifdef __mips__ 1780 static void 1781 clean_k2dcache(scb) 1782 struct sc_scb *scb; 1783 { 1784 struct sc_map *sc_map = scb->sc_map; 1785 paddr_t pa; 1786 int i, pages; 1787 1788 pa = kvtophys((vaddr_t)scb->msgbuf); 1789 mips_dcache_wbinv_range_index(MIPS_PHYS_TO_KSEG0(pa), 1790 sizeof(scb->msgbuf)); 1791 1792 if (MACH_IS_USPACE(scb->sc_cpoint)) 1793 panic("clean_k2dcache: user address is not supported"); 1794 1795 if (MACH_IS_CACHED(scb->sc_cpoint)) { 1796 mips_dcache_wbinv_range_index((vaddr_t)scb->sc_cpoint, 1797 scb->sc_ctrnscnt); 1798 return; 1799 } 1800 1801 if (sc_map) { 1802 pages = sc_map->mp_pages; 1803 for (i = 0; i < pages; i++) { 1804 pa = sc_map->mp_addr[i] << PGSHIFT; 1805 mips_dcache_wbinv_range_index(MIPS_PHYS_TO_KSEG0(pa), 1806 PAGE_SIZE); 1807 } 1808 } 1809 } 1810 #endif 1811
Indexes created Sun Sep 28 12:09:53 GMT 2025