scsi_1185.c revision 1.19
1 /* $NetBSD: scsi_1185.c,v 1.19 2008/04/09 15:40:30 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: $Hdr: scsi_1185.c,v 4.300 91/06/09 06:22:20 root Rel41 $ SONY 35 * 36 * @(#)scsi_1185.c 8.1 (Berkeley) 6/11/93 37 */ 38 39 /* 40 * Copyright (c) 1989- by SONY Corporation. 41 * 42 * scsi_1185.c 43 * 44 * CXD1185Q 45 * SCSI bus low level common routines 46 * for one CPU machine 47 * 48 * MODIFY HISTORY: 49 * 50 * DMAC_WAIT --- DMAC_0266 wo tukau-baai, DMAC mata-wa SCSI-chip ni 51 * tuzukete access suru-baai, 52 * kanarazu wait wo ireru-beshi ! 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: scsi_1185.c,v 1.19 2008/04/09 15:40:30 tsutsui Exp $"); 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/device.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <dev/scsipi/scsi_all.h> 65 #include <dev/scsipi/scsipi_all.h> 66 #include <dev/scsipi/scsiconf.h> 67 68 #include <machine/cpu.h> 69 #include <machine/intr.h> 70 #include <machine/machConst.h> 71 72 #include <mips/cache.h> 73 74 #include <newsmips/dev/screg_1185.h> 75 #include <newsmips/dev/scsireg.h> 76 77 #include "ioconf.h" 78 79 #if defined(news3400) 80 # include <newsmips/dev/dmac_0448.h> 81 # ifndef NDMACMAP 82 # define NDMACMAP 144 83 # endif 84 #endif 85 86 #define ABORT_SYNCTR_MES_FROM_TARGET 87 #define SCSI_1185AQ 88 #define RESET_RECOVER 89 #define DMAC_MAP_INIT /* for nws-3700 parity error */ 90 #define APAD_ALWAYS_ON 91 92 #define CHECK_LOOP_CNT 60 93 #define RSL_LOOP_CNT 60 94 95 #ifndef DMAC_MAP_INIT 96 # define MAP_OVER_ACCESS /* for nws-3700 parity error */ 97 #endif 98 99 #undef CHECK_MRQ 100 101 #ifdef NOT_SUPPORT_SYNCTR 102 # define MAX_OFFSET_BYTES 0 103 #else 104 # define MAX_OFFSET_BYTES MAX_OFFSET 105 #endif 106 107 #define act_point spoint 108 #define act_trcnt stcnt 109 #define act_tag stag 110 #define act_offset soffset 111 112 #define splscsi splsc 113 114 #if defined(__mips__) && defined(CPU_SINGLE) 115 #define nops(x) { int __i; for (__i = 0; __i < (x); __i++) ; } 116 #define DMAC_WAIT0 ; 117 #else 118 #define DMAC_WAIT0 DMAC_WAIT 119 #endif 120 121 #ifdef DMAC_MAP_INIT 122 static int dmac_map_init = 0; 123 #endif 124 125 /* 126 * command flag status 127 */ 128 #define CF_SET 1 129 #define CF_SEND 2 130 #define CF_ENOUGH 3 131 #define CF_EXEC 4 132 133 #define SEL_TIMEOUT_VALUE 0x7a 134 135 void sc_send(struct sc_scb *, int, int); 136 int scintr(void); 137 void scsi_hardreset(void); 138 void scsi_chipreset(struct sc_softc *); 139 void scsi_softreset(struct sc_softc *); 140 int sc_busy(struct sc_softc *, int); 141 142 static int WAIT_STATR_BITCLR(int); 143 static int WAIT_STATR_BITSET(int); 144 static void SET_CMD(struct sc_softc *, int); 145 static void SET_CNT(int); 146 static int GET_CNT(void); 147 static void GET_INTR(uint8_t *, uint8_t *); 148 static void sc_start(struct sc_softc *); 149 static void sc_resel(struct sc_softc *); 150 static void sc_discon(struct sc_softc *); 151 static void sc_pmatch(struct sc_softc *); 152 static void flush_fifo(struct sc_softc *); 153 static void sc_cout(struct sc_softc *, struct sc_chan_stat *); 154 static void sc_min(struct sc_softc *, struct sc_chan_stat *); 155 static void sc_mout(struct sc_softc *, struct sc_chan_stat *); 156 static void sc_sin(struct sc_softc *, volatile struct sc_chan_stat *); 157 static void sc_dio(struct sc_softc *, volatile struct sc_chan_stat *); 158 static void sc_dio_pad(struct sc_softc *, volatile struct sc_chan_stat *); 159 static void print_scsi_stat(struct sc_softc *); 160 static void append_wb(struct sc_softc *, struct sc_chan_stat *); 161 static struct sc_chan_stat *get_wb_chan(struct sc_softc *); 162 static int release_wb(struct sc_softc *); 163 static void adjust_transfer(struct sc_softc *, struct sc_chan_stat *); 164 static void clean_k2dcache(struct sc_scb *); 165 166 extern void sc_done(struct sc_scb *); 167 extern paddr_t kvtophys(vaddr_t); 168 169 #if defined(__mips__) && defined(CPU_SINGLE) 170 #define dma_reset(x) do { \ 171 int __s = splscsi(); \ 172 dmac_gsel = (x); dmac_cctl = DM_RST; dmac_cctl = 0; \ 173 splx(__s); \ 174 } while (/* CONSTCOND */ 0) 175 #endif 176 177 int 178 WAIT_STATR_BITCLR(int bitmask) 179 { 180 int iloop; 181 uint8_t dummy; 182 183 iloop = 0; 184 do { 185 dummy = sc_statr; 186 DMAC_WAIT0; 187 if (iloop++ > CHECK_LOOP_CNT) 188 return -1; 189 } while (dummy & bitmask); 190 return 0; 191 } 192 193 int 194 WAIT_STATR_BITSET(int bitmask) 195 { 196 int iloop; 197 uint8_t dummy; 198 199 iloop = 0; 200 do { 201 dummy = sc_statr; 202 DMAC_WAIT0; 203 if (iloop++ > CHECK_LOOP_CNT) 204 return -1; 205 } while ((dummy & bitmask) == 0); 206 return 0; 207 } 208 209 void 210 SET_CMD(struct sc_softc *sc, int CMD) 211 { 212 213 (void)WAIT_STATR_BITCLR(R0_CIP); 214 sc->lastcmd = CMD; 215 sc_comr = CMD; 216 DMAC_WAIT0; 217 } 218 219 void 220 SET_CNT(int COUNT) 221 { 222 223 sc_tclow = COUNT & 0xff; 224 DMAC_WAIT0; 225 sc_tcmid = (COUNT >> 8) & 0xff; 226 DMAC_WAIT0; 227 sc_tchi = (COUNT >> 16) & 0xff; 228 DMAC_WAIT0; 229 } 230 231 int 232 GET_CNT(void) 233 { 234 int COUNT; 235 236 COUNT = sc_tclow; 237 DMAC_WAIT0; 238 COUNT += (sc_tcmid << 8) & 0xff00; 239 DMAC_WAIT0; 240 COUNT += (sc_tchi << 16) & 0xff0000; 241 DMAC_WAIT0; 242 return COUNT; 243 } 244 245 void 246 GET_INTR(uint8_t *DATA1, uint8_t *DATA2) 247 { 248 249 (void)WAIT_STATR_BITCLR(R0_CIP); 250 while (sc_statr & R0_MIRQ) { 251 DMAC_WAIT0; 252 *DATA1 |= sc_intrq1; 253 DMAC_WAIT0; 254 *DATA2 |= sc_intrq2; 255 DMAC_WAIT0; 256 } 257 } 258 259 260 void 261 sc_send(struct sc_scb *scb, int chan, int ie) 262 { 263 struct sc_softc *sc = scb->scb_softc; 264 struct sc_chan_stat *cs; 265 struct scsipi_xfer *xs; 266 int i; 267 uint8_t *p; 268 269 cs = &sc->chan_stat[chan]; 270 xs = scb->xs; 271 272 p = (uint8_t *)xs->cmd; 273 if (cs->scb != NULL) { 274 printf("SCSI%d: sc_send() NOT NULL cs->sc\n", chan); 275 printf("ie=0x%x scb=%p cs->sc=%p\n", ie, scb, cs->scb); 276 printf("cdb="); 277 for (i = 0; i < 6; i++) 278 printf(" 0x%x", *p++); 279 printf("\n"); 280 panic("SCSI soft error"); 281 /*NOTREACHED*/ 282 } 283 284 if (p[0] == SCOP_RESET && p[1] == SCOP_RESET) { 285 /* 286 * SCSI bus reset command procedure 287 * (vender unique by Sony Corp.) 288 */ 289 #ifdef SCSI_1185AQ 290 if (sc_idenr & 0x08) 291 sc->scsi_1185AQ = 1; 292 else 293 sc->scsi_1185AQ = 0; 294 #endif 295 cs->scb = scb; 296 scsi_hardreset(); 297 scb->istatus = INST_EP; 298 cs->scb = NULL; 299 sc_done(scb); 300 return; 301 } 302 303 if (scb->sc_map && (scb->sc_map->mp_pages > 0)) { 304 /* 305 * use map table 306 */ 307 scb->sc_coffset = scb->sc_map->mp_offset & PGOFSET; 308 if (scb->sc_map->mp_pages > NSCMAP) { 309 printf("SCSI%d: map table overflow\n", chan); 310 scb->istatus = INST_EP|INST_LB|INST_PRE; 311 return; 312 } 313 } else { 314 /* 315 * no use map table 316 */ 317 scb->sc_coffset = (u_int)scb->sc_cpoint & PGOFSET; 318 } 319 scb->sc_ctag = 0; 320 321 cs->scb = scb; 322 cs->comflg = OFF; 323 324 cs->intr_flg = ie; 325 cs->chan_num = chan; 326 sc->perr_flag[chan] = 0; 327 sc->mout_flag[chan] = 0; 328 sc->min_cnt[chan] = 0; 329 330 sc->sel_stat[chan] = SEL_WAIT; 331 append_wb(sc, cs); 332 sc_start(sc); 333 } 334 335 /* 336 * SCSI start up routine 337 */ 338 void 339 sc_start(struct sc_softc *sc) 340 { 341 struct sc_chan_stat *cs; 342 int chan, s; 343 uint8_t dummy; 344 345 s = splscsi(); 346 cs = get_wb_chan(sc); 347 if ((cs == NULL) || (sc->ipc >= 0)) 348 goto sc_start_exit; 349 chan = cs->chan_num; 350 if (sc->sel_stat[chan] != SEL_WAIT) { 351 /* 352 * already started 353 */ 354 goto sc_start_exit; 355 } 356 sc->sel_stat[chan] = SEL_START; 357 358 dummy = sc_cmonr; 359 DMAC_WAIT0; 360 if (dummy & (R4_MBSY|R4_MSEL)) { 361 sc->sel_stat[chan] = SEL_WAIT; 362 goto sc_start_exit; 363 } 364 365 /* 366 * send SELECT with ATN command 367 */ 368 sc->dma_stat = OFF; 369 sc->pad_start = 0; 370 dummy = sc_statr; 371 DMAC_WAIT0; 372 if (dummy & R0_CIP) { 373 sc->sel_stat[chan] = SEL_WAIT; 374 goto sc_start_exit; 375 } 376 sc_idenr = (chan << SC_TG_SHIFT) | SC_OWNID; 377 DMAC_WAIT0; 378 #ifdef SCSI_1185AQ 379 if (sc->scsi_1185AQ) 380 sc_intok1 = Ra_STO|Ra_ARBF; 381 else 382 sc_intok1 = Ra_STO|Ra_RSL|Ra_ARBF; 383 #else 384 sc_intok1 = Ra_STO|Ra_RSL|Ra_ARBF; 385 #endif 386 DMAC_WAIT0; 387 /* 388 * BUGFIX for signal reflection on BSY 389 * !Rb_DCNT 390 */ 391 sc_intok2 = Rb_FNC|Rb_SRST|Rb_PHC|Rb_SPE; 392 DMAC_WAIT0; 393 394 dummy = sc_cmonr; 395 DMAC_WAIT0; 396 if (dummy & (R4_MBSY|R4_MSEL)) { 397 sc->sel_stat[chan] = SEL_WAIT; 398 goto sc_start_exit; 399 } 400 SET_CMD(sc, SCMD_SEL_ATN); 401 402 sc_start_exit: 403 splx(s); 404 } 405 406 /* 407 * SCSI interrupt service routine 408 */ 409 int 410 scintr(void) 411 { 412 int iloop; 413 int chan; 414 uint8_t dummy; 415 struct sc_softc *sc; 416 struct sc_chan_stat *cs; 417 uint8_t s_int1, s_int2; 418 419 sc = device_lookup_private(&sc_cd, 0); /* XXX */ 420 421 scintr_loop: 422 423 #if defined(CHECK_MRQ) && defined(news3400) 424 while (dmac_gstat & CH_MRQ(CH_SCSI)) 425 DMAC_WAIT; 426 #endif 427 428 for (iloop = 0; iloop < 100; iloop++) { 429 dummy = sc_statr; 430 DMAC_WAIT; 431 if ((dummy & R0_CIP) == 0) 432 break; 433 } 434 435 /* 436 * get SCSI interrupt request 437 */ 438 while (sc_statr & R0_MIRQ) { 439 DMAC_WAIT0; 440 s_int1 = sc_intrq1; 441 DMAC_WAIT0; 442 s_int2 = sc_intrq2; 443 DMAC_WAIT0; 444 sc->int_stat1 |= s_int1; 445 sc->int_stat2 |= s_int2; 446 } 447 448 if (sc->int_stat2 & R3_SRST) { 449 /* 450 * RST signal is drived 451 */ 452 sc->int_stat2 &= ~R3_SRST; 453 scsi_softreset(sc); 454 goto scintr_exit; 455 } 456 457 if ((sc->ipc < 0) && (sc->wrc <= 0) && (sc->wbc <= 0)) { 458 sc->int_stat1 = 0; 459 sc->int_stat2 = 0; 460 goto scintr_exit; 461 } 462 463 cs = get_wb_chan(sc); 464 if (cs) 465 chan = cs->chan_num; 466 467 if (cs && (sc->sel_stat[chan] == SEL_START) && 468 (sc->lastcmd == SCMD_SEL_ATN)) { 469 /* 470 * Check the result of SELECTION command 471 */ 472 if (sc->int_stat1 & R2_RSL) { 473 /* 474 * RESELECTION occur 475 */ 476 if (sc->wrc > 0) { 477 sc->sel_stat[chan] = SEL_RSLD; 478 } else { 479 /* 480 * Ghost RESELECTION ??? 481 */ 482 sc->int_stat1 &= ~R2_RSL; 483 } 484 } 485 if (sc->int_stat1 & R2_ARBF) { 486 /* 487 * ARBITRATION fault 488 */ 489 sc->int_stat1 &= ~R2_ARBF; 490 sc->sel_stat[chan] = SEL_ARBF; 491 } 492 if (sc->int_stat1 & R2_STO) { 493 /* 494 * SELECTION timeout 495 */ 496 sc->int_stat1 &= ~R2_STO; 497 if ((sc->int_stat2&(R3_PHC|R3_RMSG)) != 498 (R3_PHC|R3_RMSG)) { 499 sc->ipc = chan; 500 sc->ip = &sc->chan_stat[chan]; 501 sc->sel_stat[chan] = SEL_TIMEOUT; 502 sc->chan_stat[chan].scb->istatus 503 = INST_EP|INST_TO; 504 release_wb(sc); 505 } 506 } 507 508 /* 509 * SELECTION command done 510 */ 511 switch (sc->sel_stat[chan]) { 512 513 case SEL_START: 514 if ((sc->int_stat2 & R3_FNC) == 0) 515 break; 516 /* 517 * SELECTION success 518 */ 519 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE; 520 sc->ipc = chan; 521 sc->ip = &sc->chan_stat[chan]; 522 sc->ip->scb->istatus |= INST_IP; 523 sc->dma_stat = OFF; 524 sc->pad_start = 0; 525 sc->sel_stat[chan] = SEL_SUCCESS; 526 release_wb(sc); 527 #ifndef NOT_SUPPORT_SYNCTR 528 sc_syncr = sc->sync_tr[chan]; 529 DMAC_WAIT0; 530 #endif 531 DMAC_WAIT0; 532 break; 533 534 case SEL_TIMEOUT: 535 /* 536 * SELECTION time out 537 */ 538 sc_discon(sc); 539 goto scintr_exit; 540 541 /* case SEL_RSLD: */ 542 /* case SEL_ARBF: */ 543 default: 544 /* 545 * SELECTION failed 546 */ 547 sc->sel_stat[chan] = SEL_WAIT; 548 break; 549 } 550 if ((sc->int_stat1 & R2_RSL) == 0) 551 sc->int_stat2 &= ~R3_FNC; 552 } 553 554 if (sc->ip != NULL) { 555 /* 556 * check In Process channel's request 557 */ 558 if (sc->dma_stat != OFF) { 559 /* 560 * adjust pointer & counter 561 */ 562 adjust_transfer(sc, sc->ip); 563 } 564 if (sc->int_stat2 & R3_SPE) { 565 int volatile statr; 566 int volatile cmonr; 567 568 statr = sc_statr; 569 DMAC_WAIT0; 570 cmonr = sc_cmonr; 571 sc->int_stat2 &= ~R3_SPE; 572 sc->perr_flag[sc->ip->chan_num] = 1; 573 } 574 } 575 576 if (sc->int_stat2 & R3_DCNT) { 577 /* 578 * Bus Free 579 */ 580 sc_discon(sc); 581 sc->int_stat2 &= ~R3_DCNT; 582 } 583 584 if ((sc->ipc >= 0) && (sc->sel_stat[sc->ipc] == SEL_RSL_WAIT)) { 585 sc->sel_stat[sc->ipc] = SEL_RSLD; 586 sc->ipc = -1; 587 sc->int_stat1 |= R2_RSL; 588 } 589 if (sc->int_stat1 & R2_RSL) { 590 /* 591 * Reselection 592 */ 593 sc_resel(sc); 594 sc->int_stat1 &= ~R2_RSL; 595 if (sc->sel_stat[sc->ipc] == SEL_RSL_WAIT) 596 goto scintr_exit; 597 } 598 599 600 if ((sc->ipc >= 0) && (sc->ipc != SC_OWNID) && 601 (sc->sel_stat[sc->ipc] == SEL_SUCCESS)) { 602 if (sc->int_stat2 & R3_PHC) { 603 /* 604 * Phase change 605 */ 606 sc->int_stat2 &= ~(R3_PHC|R3_RMSG); 607 sc_pmatch(sc); 608 } else if (sc->int_stat2 & R3_RMSG) { 609 /* 610 * message Phase 611 */ 612 if (sc->min_flag > 0) { 613 sc->int_stat2 &= ~(R3_PHC|R3_RMSG); 614 sc_pmatch(sc); 615 } 616 } 617 else if (sc->dma_stat != OFF) { 618 dummy = sc_cmonr; 619 DMAC_WAIT0; 620 if ((dummy & (R4_MMSG|R4_MCD|R4_MREQ)) == R4_MREQ) { 621 /* 622 * still DATA transfer phase 623 */ 624 sc_dio_pad(sc, sc->ip); 625 } 626 } 627 else if (sc->ip->comflg == CF_SEND) { 628 dummy = sc_cmonr; 629 DMAC_WAIT0; 630 if ((dummy & SC_PMASK) == COM_OUT) { 631 /* 632 * command out phase 633 */ 634 sc_cout(sc, sc->ip); 635 } 636 } 637 } else { 638 if (sc->int_stat2 & (R3_PHC|R3_RMSG)) 639 goto scintr_exit; 640 } 641 642 if ((sc->int_stat1 & (R2_STO|R2_RSL|R2_ARBF)) 643 || (sc->int_stat2 & (R3_DCNT|R3_SRST|R3_PHC|R3_SPE))) { 644 /* 645 * still remain intrq 646 */ 647 goto scintr_loop; 648 } 649 650 scintr_exit: 651 return 1; 652 } 653 654 /* 655 * SCSI bus reset routine 656 * scsi_hardreset() is occered a reset interrupt. 657 * And call scsi_softreset(). 658 */ 659 void 660 scsi_hardreset(void) 661 { 662 int s; 663 #ifdef DMAC_MAP_INIT 664 int i; 665 #endif 666 struct sc_softc *sc; 667 668 sc = device_lookup_private(&sc_cd, 0); /* XXX */ 669 s = splscsi(); 670 671 scsi_chipreset(sc); 672 DMAC_WAIT0; 673 sc->int_stat1 = 0; 674 sc->int_stat2 = 0; 675 SET_CMD(sc, SCMD_AST_RST); /* assert RST signal */ 676 677 #ifdef DMAC_MAP_INIT 678 if (dmac_map_init == 0) { 679 dmac_map_init++; 680 for (i = 0; i < NDMACMAP; i++) { 681 # if defined(__mips__) && defined(CPU_SINGLE) 682 dmac_gsel = CH_SCSI; 683 dmac_ctag = (uint8_t)i; 684 dmac_cmap = (uint16_t)0; 685 # endif 686 } 687 } 688 #endif 689 /*cxd1185_init();*/ 690 splx(s); 691 } 692 693 /* 694 * I/O port (sc_ioptr) bit assign 695 * 696 * Rf_PRT3 - <reserved> 697 * Rf_PRT2 - <reserved> 698 * Rf_PRT1 out Floppy Disk Density control 699 * Rf_PRT0 out Floppy Disk Eject control 700 */ 701 702 void 703 scsi_chipreset(struct sc_softc *sc) 704 { 705 int s; 706 uint8_t save_ioptr; 707 708 s = splscsi(); 709 710 #if defined(__mips__) && defined(CPU_SINGLE) 711 dmac_gsel = CH_SCSI; 712 dmac_cwid = 4; /* initialize DMAC SCSI chan */ 713 *(volatile uint8_t *)PINTEN |= DMA_INTEN; 714 dma_reset(CH_SCSI); 715 #endif 716 sc_envir = 0; /* 1/4 clock */ 717 DMAC_WAIT0; 718 save_ioptr = sc_ioptr; 719 DMAC_WAIT0; 720 sc->lastcmd = SCMD_CHIP_RST; 721 sc_comr = SCMD_CHIP_RST; /* reset chip */ 722 DMAC_WAIT; 723 (void)WAIT_STATR_BITCLR(R0_CIP); 724 /* 725 * SCMD_CHIP_RST command reset all register 726 * except sc_statr<7:6> & sc_cmonr. 727 * So, bit R0_MIRQ & R3_FNC will be not set. 728 */ 729 sc_idenr = SC_OWNID; 730 DMAC_WAIT0; 731 732 sc_intok1 = Ra_STO|Ra_RSL|Ra_ARBF; 733 DMAC_WAIT0; 734 sc_intok2 = Rb_FNC|Rb_SRST|Rb_PHC|Rb_SPE|Rb_RMSG; 735 DMAC_WAIT0; 736 737 sc_ioptr = save_ioptr; 738 DMAC_WAIT; 739 740 sc_moder = Rc_TMSL; /* RST drive time = 25.5 us */ 741 DMAC_WAIT0; 742 sc_timer = 0x2; 743 DMAC_WAIT0; 744 745 sc_moder = Rc_SPHI; /* selection timeout = 252 ms */ 746 DMAC_WAIT0; 747 sc_timer = SEL_TIMEOUT_VALUE; 748 DMAC_WAIT0; 749 750 #ifdef SCSI_1185AQ 751 if (sc->scsi_1185AQ) 752 SET_CMD(sc, SCMD_ENB_SEL); /* enable reselection */ 753 #endif 754 755 sc->int_stat1 &= ~R2_RSL; /* ignore RSL inter request */ 756 757 splx(s); 758 } 759 760 void 761 scsi_softreset(struct sc_softc *sc) 762 { 763 struct sc_chan_stat *cs; 764 int i; 765 /* int (*handler)(); */ 766 767 sc->wbq_actf = NULL; 768 sc->wbq_actl = NULL; 769 sc->wbc = 0; 770 sc->wrc = 0; 771 sc->ip = NULL; 772 sc->ipc = -1; 773 sc->dma_stat = OFF; 774 sc->pad_start = 0; 775 776 for (i = 0; i < NTARGET; ++i) { 777 if (i == SC_OWNID) 778 continue; 779 cs = &sc->chan_stat[i]; 780 cs->wb_next = NULL; 781 #ifndef NOT_SUPPORT_SYNCTR 782 sc->sync_tr[i] = 0; /* asynchronous mode */ 783 #endif 784 sc->sel_stat[i] = SEL_WAIT; 785 if (cs->scb != NULL) { 786 struct sc_scb *scb = cs->scb; 787 788 if ((cs->scb->istatus & INST_EP) == 0) 789 cs->scb->istatus = (INST_EP|INST_HE); 790 cs->scb = NULL; 791 #ifdef __mips__ 792 clean_k2dcache(scb); 793 #endif 794 if (cs->intr_flg == SCSI_INTEN) { 795 intrcnt[SCSI_INTR]++; 796 #if 0 797 handler = scintsw[i].sci_inthandler; 798 if (handler) 799 (*handler)(scintsw[i].sci_ctlr); 800 #endif 801 } 802 sc_done(scb); 803 } 804 } 805 } 806 807 /* 808 * RESELECTION interrupt service routine 809 * ( RESELECTION phase ) 810 */ 811 void 812 sc_resel(struct sc_softc *sc) 813 { 814 struct sc_chan_stat *cs; 815 uint8_t chan; 816 uint8_t statr; 817 int iloop; 818 819 sc->min_flag = 0; 820 chan = (sc_idenr & R6_SID_MASK) >> SC_TG_SHIFT; 821 822 if (chan == SC_OWNID) 823 return; 824 825 statr = sc_statr; 826 DMAC_WAIT0; 827 if (statr & R0_CIP) { 828 if (sc->lastcmd == SCMD_SEL_ATN) { 829 /* 830 * SELECTION command dead lock ? 831 * save interrupt request 832 */ 833 while (sc_statr & R0_MIRQ) { 834 DMAC_WAIT0; 835 sc->int_stat1 |= sc_intrq1; 836 DMAC_WAIT0; 837 sc->int_stat2 |= sc_intrq2; 838 DMAC_WAIT0; 839 } 840 scsi_chipreset(sc); 841 } 842 } 843 844 cs = &sc->chan_stat[chan]; 845 if (cs->scb == NULL) { 846 scsi_hardreset(); 847 return; 848 } 849 if ((cs->scb->istatus & INST_WR) == 0) { 850 scsi_hardreset(); 851 return; 852 } 853 854 if (sc->ipc >= 0) { 855 scsi_hardreset(); 856 return; 857 } 858 859 sc->ip = cs; 860 sc->ipc = chan; 861 862 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE; 863 DMAC_WAIT0; 864 865 iloop = 0; 866 while ((sc->int_stat2 & R3_FNC) == 0) { 867 /* 868 * Max 6 usec wait 869 */ 870 if (iloop++ > RSL_LOOP_CNT) { 871 sc->sel_stat[chan] = SEL_RSL_WAIT; 872 return; 873 } 874 GET_INTR(&sc->int_stat1, &sc->int_stat2); 875 } 876 sc->int_stat2 &= ~R3_FNC; 877 878 sc->sel_stat[chan] = SEL_SUCCESS; 879 880 sc->wrc--; 881 sc->dma_stat = OFF; 882 sc->pad_start = 0; 883 cs->scb->istatus |= INST_IP; 884 cs->scb->istatus &= ~INST_WR; 885 886 #ifndef NOT_SUPPORT_SYNCTR 887 sc_syncr = sc->sync_tr[chan]; 888 DMAC_WAIT0; 889 #endif 890 } 891 892 /* 893 * DISCONNECT interrupt service routine 894 * ( Target disconnect / job done ) 895 */ 896 void 897 sc_discon(struct sc_softc *sc) 898 { 899 struct sc_chan_stat *cs; 900 /* int (*handler)(); */ 901 uint8_t dummy; 902 903 /* 904 * Signal reflection on BSY has occurred. 905 * Not Bus Free Phase, ignore. 906 * 907 * But, CXD1185Q reset INIT bit of sc_statr. 908 * So, can't issue Transfer Information command. 909 * 910 * What shall we do ? Bus reset ? 911 */ 912 if ((sc->int_stat2 & R3_DCNT) && ((sc_intok2 & Rb_DCNT) == 0)) 913 return; 914 915 sc_intok2 = Rb_FNC|Rb_SRST|Rb_PHC|Rb_SPE; 916 DMAC_WAIT0; 917 918 sc->min_flag = 0; 919 dummy = sc_cmonr; 920 DMAC_WAIT0; 921 if (dummy & R4_MATN) { 922 SET_CMD(sc, SCMD_NGT_ATN); 923 (void) WAIT_STATR_BITSET(R0_MIRQ); 924 GET_INTR(&sc->int_stat1, &sc->int_stat2); /* clear interrupt */ 925 } 926 927 if ((sc->int_stat1 & R2_RSL) == 0) 928 sc->int_stat2 &= ~R3_FNC; 929 930 cs = sc->ip; 931 if ((cs == NULL) || (sc->ipc < 0)) 932 goto sc_discon_exit; 933 934 if ((sc->sel_stat[cs->chan_num] != SEL_SUCCESS) 935 && (sc->sel_stat[cs->chan_num] != SEL_TIMEOUT)) 936 printf("%s: eh!\n", __func__); 937 938 /* 939 * indicate abnormal terminate 940 */ 941 if ((cs->scb->istatus & (INST_EP|INST_WR)) == 0) 942 cs->scb->istatus |= (INST_EP|INST_PRE|INST_LB); 943 944 cs->scb->istatus &= ~INST_IP; 945 sc->dma_stat = OFF; 946 sc->pad_start = 0; 947 sc->ip = NULL; 948 sc->ipc = -1; 949 950 if ((cs->scb->istatus & INST_WR) == 0) { 951 struct sc_scb *scb = cs->scb; 952 953 if (sc->perr_flag[cs->chan_num] > 0) 954 cs->scb->istatus |= INST_EP|INST_PRE; 955 cs->scb = NULL; 956 #ifdef __mips__ 957 clean_k2dcache(scb); 958 #endif 959 if (cs->intr_flg == SCSI_INTEN) { 960 intrcnt[SCSI_INTR]++; 961 #if 0 962 handler = scintsw[cs->chan_num].sci_inthandler; 963 if (handler) 964 (*handler)(scintsw[cs->chan_num].sci_ctlr); 965 #endif 966 } 967 sc_done(scb); 968 } 969 970 sc_discon_exit: 971 sc_start(sc); 972 } 973 974 /* 975 * SCSI phase match interrupt service routine 976 */ 977 void 978 sc_pmatch(struct sc_softc *sc) 979 { 980 struct sc_chan_stat *cs; 981 uint8_t phase; 982 uint8_t phase2; 983 uint8_t cmonr; 984 985 sc->int_stat2 &= ~R3_FNC; /* XXXXXXXX */ 986 987 cs = sc->ip; 988 if (cs == NULL) 989 return; 990 991 #if defined(__mips__) && defined(CPU_SINGLE) 992 dma_reset(CH_SCSI); 993 #endif 994 phase = sc_cmonr & SC_PMASK; 995 DMAC_WAIT0; 996 for (;;) { 997 phase2 = phase; 998 cmonr = sc_cmonr; 999 DMAC_WAIT0; 1000 phase = cmonr & SC_PMASK; 1001 if (phase == phase2) { 1002 if ((phase == DAT_IN) || (phase == DAT_OUT)) 1003 break; 1004 else if (cmonr & R4_MREQ) 1005 break; 1006 } 1007 } 1008 1009 1010 sc->dma_stat = OFF; 1011 sc->pad_start = 0; 1012 1013 if (phase == COM_OUT) { 1014 sc->min_flag = 0; 1015 if (cs->comflg != CF_SEND) 1016 cs->comflg = CF_SET; 1017 sc_cout(sc, cs); 1018 } else { 1019 cs->comflg = CF_ENOUGH; 1020 sc_intok2 &= ~Rb_FNC; 1021 if (phase == MES_IN) { 1022 sc->min_flag++; 1023 sc_min(sc, cs); 1024 } else { 1025 sc->min_flag = 0; 1026 1027 switch (phase) { 1028 1029 case MES_OUT: 1030 sc_mout(sc, cs); 1031 break; 1032 1033 case DAT_IN: 1034 case DAT_OUT: 1035 sc_dio(sc, cs); 1036 break; 1037 1038 case STAT_IN: 1039 sc_sin(sc, cs); 1040 break; 1041 1042 default: 1043 printf("SCSI%d: unknown phase\n", cs->chan_num); 1044 break; 1045 } 1046 } 1047 } 1048 } 1049 1050 1051 void 1052 flush_fifo(struct sc_softc *sc) 1053 { 1054 uint8_t dummy; 1055 uint8_t tmp; 1056 uint8_t tmp0; 1057 1058 dummy = sc_ffstr; 1059 DMAC_WAIT0; 1060 if (dummy & R5_FIFOREM) { 1061 /* 1062 * flush FIFO 1063 */ 1064 SET_CMD(sc, SCMD_FLSH_FIFO); 1065 tmp = 0; 1066 do { 1067 do { 1068 dummy = sc_statr; 1069 DMAC_WAIT0; 1070 } while (dummy & R0_CIP); 1071 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1072 } while ((tmp & R3_FNC) == 0); 1073 } 1074 } 1075 1076 /* 1077 * SCSI command send routine 1078 */ 1079 void 1080 sc_cout(struct sc_softc *sc, struct sc_chan_stat *cs) 1081 { 1082 int iloop; 1083 int cdb_bytes; 1084 uint8_t dummy; 1085 uint8_t statr; 1086 struct scsipi_xfer *xs; 1087 1088 if (cs->comflg == CF_SET) { 1089 struct sc_scb *scb = cs->scb; 1090 1091 cs->comflg = CF_SEND; 1092 1093 flush_fifo(sc); 1094 1095 xs = scb->xs; 1096 cdb_bytes = xs->cmdlen; 1097 1098 switch (xs->cmd->opcode & CMD_TYPEMASK) { 1099 case CMD_T0: 1100 case CMD_T1: 1101 case CMD_T5: 1102 break; 1103 1104 default: 1105 cdb_bytes = 6; 1106 sc_intok2 |= Rb_FNC; 1107 break; 1108 } 1109 1110 /* 1111 * set Active pointers 1112 */ 1113 sc->act_cmd_pointer = (char *)xs->cmd; 1114 cs->act_trcnt = scb->sc_ctrnscnt; 1115 cs->act_point = scb->sc_cpoint; 1116 cs->act_tag = scb->sc_ctag; 1117 cs->act_offset = scb->sc_coffset; 1118 1119 } else { 1120 cdb_bytes = 1; 1121 iloop = 0; 1122 do { 1123 dummy = sc_cmonr; 1124 DMAC_WAIT0; 1125 if ((dummy & SC_PMASK) != COM_OUT) 1126 return; 1127 statr = sc_statr; 1128 DMAC_WAIT0; 1129 if (statr & R0_MIRQ) 1130 return; 1131 } while ((dummy & R4_MREQ) == 0); 1132 statr = sc_statr; 1133 DMAC_WAIT0; 1134 if (statr & R0_MIRQ) 1135 return; 1136 } 1137 1138 1139 SET_CNT(cdb_bytes); 1140 SET_CMD(sc, SCMD_TR_INFO|R0_TRBE); 1141 1142 for (iloop = 0; iloop < cdb_bytes; iloop++) { 1143 do { 1144 dummy = sc_cmonr; 1145 DMAC_WAIT0; 1146 if ((dummy & SC_PMASK) != COM_OUT) 1147 return; 1148 } while ((dummy & R4_MREQ) == 0); 1149 statr = sc_statr; 1150 DMAC_WAIT0; 1151 if (statr & R0_MIRQ) 1152 return; 1153 sc_datr = *sc->act_cmd_pointer++; 1154 do { 1155 dummy = sc_cmonr; 1156 DMAC_WAIT0; 1157 } while ((dummy & R4_MACK) != 0); 1158 } 1159 } 1160 1161 #define GET_MIN_COUNT 127 1162 1163 /* 1164 * SCSI message accept routine 1165 */ 1166 void 1167 sc_min(struct sc_softc *sc, struct sc_chan_stat *cs) 1168 { 1169 struct sc_scb *scb = cs->scb; 1170 struct scsipi_xfer *xs = scb->xs; 1171 uint8_t dummy; 1172 1173 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE|Rb_RMSG; 1174 DMAC_WAIT0; 1175 1176 if (sc->min_flag == 1) 1177 flush_fifo(sc); 1178 1179 dummy = sc_cmonr; 1180 DMAC_WAIT0; 1181 if ((dummy & R4_MREQ) == 0) { 1182 printf("sc_min: !REQ cmonr=%x\n", dummy); 1183 print_scsi_stat(sc); 1184 scsi_hardreset(); 1185 return; 1186 } 1187 1188 /* retry_cmd_issue: */ 1189 sc->int_stat2 &= ~R3_FNC; 1190 SET_CMD(sc, SCMD_TR_INFO); 1191 do { 1192 do { 1193 dummy = sc_statr; 1194 DMAC_WAIT0; 1195 } while (dummy & R0_CIP); 1196 GET_INTR(&sc->int_stat1, &sc->int_stat2); /* clear interrupt */ 1197 } while ((sc->int_stat2 & R3_FNC) == 0); 1198 sc->int_stat2 &= ~R3_FNC; 1199 1200 dummy = sc_ffstr; 1201 if (dummy & R5_FIE) { 1202 DMAC_WAIT; 1203 dummy = sc_ffstr; 1204 DMAC_WAIT0; 1205 if (dummy & R5_FIE) { 1206 dummy = sc_statr; 1207 DMAC_WAIT0; 1208 if ((dummy & R0_INIT) == 0) { 1209 /* 1210 * CXD1185 detect BSY false 1211 */ 1212 scsi_hardreset(); 1213 return; 1214 } 1215 } 1216 } 1217 dummy = sc_datr; /* get message byte */ 1218 DMAC_WAIT0; 1219 1220 if (sc->min_cnt[cs->chan_num] == 0) { 1221 scb->message = scb->identify; 1222 if (dummy == MSG_EXTND) { 1223 /* Extended Message */ 1224 sc->min_cnt[cs->chan_num] = GET_MIN_COUNT; 1225 sc->min_point[cs->chan_num] = scb->msgbuf; 1226 memset(scb->msgbuf, 0, 8); 1227 *sc->min_point[cs->chan_num]++ = dummy; 1228 } else { 1229 switch ((dummy & MSG_IDENT)? MSG_IDENT : dummy) { 1230 1231 case MSG_CCOMP: 1232 scb->istatus |= INST_EP; 1233 break; 1234 1235 case MSG_MREJ: 1236 #ifndef NOT_SUPPORT_SYNCTR 1237 if (sc->mout_flag[cs->chan_num] == MOUT_SYNC_TR) 1238 sc->sync_tr[cs->chan_num] = 0; 1239 #endif 1240 break; 1241 1242 case MSG_IDENT: 1243 case MSG_RDP: 1244 1245 sc->dma_stat = OFF; 1246 sc->pad_start = 0; 1247 cs->comflg = OFF; 1248 /* 1249 * restore the saved value to Active pointers 1250 */ 1251 sc->act_cmd_pointer = (char *)xs->cmd; 1252 cs->act_trcnt = scb->sc_ctrnscnt; 1253 cs->act_point = scb->sc_cpoint; 1254 cs->act_tag = scb->sc_ctag; 1255 cs->act_offset = scb->sc_coffset; 1256 break; 1257 1258 case MSG_SDP: 1259 /* 1260 * save Active pointers 1261 */ 1262 scb->sc_ctrnscnt = cs->act_trcnt; 1263 scb->sc_ctag = cs->act_tag; 1264 scb->sc_coffset = cs->act_offset; 1265 scb->sc_cpoint = cs->act_point; 1266 break; 1267 1268 case MSG_DCNT: 1269 scb->istatus |= INST_WR; 1270 sc->wrc++; 1271 break; 1272 1273 default: 1274 scb->message = MSG_MREJ; 1275 SET_CMD(sc, SCMD_AST_ATN); 1276 printf("SCSI%d:sc_min() Unknown mes=0x%x, \n", 1277 cs->chan_num, dummy); 1278 } 1279 } 1280 } else { 1281 *sc->min_point[cs->chan_num]++ = dummy; 1282 if (sc->min_cnt[cs->chan_num] == GET_MIN_COUNT) 1283 sc->min_cnt[cs->chan_num] = dummy; 1284 else 1285 sc->min_cnt[cs->chan_num]--; 1286 if (sc->min_cnt[cs->chan_num] <= 0) { 1287 #ifdef ABORT_SYNCTR_MES_FROM_TARGET 1288 if ((scb->msgbuf[2] == 0x01) && 1289 (sc->mout_flag[cs->chan_num] == MOUT_SYNC_TR)) { 1290 #else 1291 if (scb->msgbuf[2] == 0x01) { 1292 #endif 1293 int i; 1294 /* 1295 * receive Synchronous transfer message reply 1296 * calculate transfer period val 1297 * tpm * 4/1000 us = 4/16 * (tpv + 1) 1298 */ 1299 #define TPM2TPV(tpm) (((tpm)*16 + 999) / 1000 - 1) 1300 #ifndef NOT_SUPPORT_SYNCTR 1301 i = scb->msgbuf[3]; /* get tpm */ 1302 i = TPM2TPV(i) << 4; 1303 if (scb->msgbuf[4] == 0) 1304 sc->sync_tr[cs->chan_num] = 0; 1305 else 1306 sc->sync_tr[cs->chan_num] = 1307 i | scb->msgbuf[4]; 1308 #endif /* !NOT_SUPPORT_SYNCTR */ 1309 } else { 1310 scb->message = MSG_MREJ; 1311 SET_CMD(sc, SCMD_AST_ATN); /* assert ATN */ 1312 } 1313 } 1314 } 1315 SET_CMD(sc, SCMD_NGT_ACK); 1316 } 1317 1318 /* 1319 * SCSI message send routine 1320 */ 1321 void 1322 sc_mout(struct sc_softc *sc, struct sc_chan_stat *cs) 1323 { 1324 struct sc_scb *scb = cs->scb; 1325 u_char *mp; 1326 int cnt; 1327 int iloop; 1328 uint8_t dummy; 1329 uint8_t tmp; 1330 uint8_t tmp0; 1331 1332 flush_fifo(sc); 1333 1334 if (sc->mout_flag[cs->chan_num] == 0) { 1335 sc->mout_flag[cs->chan_num] = MOUT_IDENTIFY; 1336 if (scb->message != 0) { 1337 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE|Rb_RMSG; 1338 DMAC_WAIT0; 1339 if ((scb->message == MSG_EXTND) 1340 && (scb->msgbuf[2] == 0x01)) { 1341 cnt = 5; 1342 mp = scb->msgbuf; 1343 scb->msgbuf[3] = MIN_TP; 1344 if (scb->msgbuf[4] > MAX_OFFSET_BYTES) 1345 scb->msgbuf[4] = MAX_OFFSET_BYTES; 1346 sc->mout_flag[cs->chan_num] = MOUT_SYNC_TR; 1347 } else { 1348 cnt = 1; 1349 mp = &scb->message; 1350 } 1351 1352 SET_CNT(cnt); 1353 SET_CMD(sc, SCMD_TR_INFO|R0_TRBE); 1354 sc_datr = scb->identify; 1355 DMAC_WAIT0; 1356 for (iloop = 1; iloop < cnt; iloop++) { 1357 sc_datr = *mp++; 1358 DMAC_WAIT; 1359 } 1360 do { 1361 dummy = sc_cmonr; 1362 DMAC_WAIT0; 1363 if ((dummy & R4_MBSY) == 0) 1364 return; 1365 dummy = sc_statr; 1366 DMAC_WAIT0; 1367 } while (dummy & R0_CIP); 1368 1369 tmp = 0; 1370 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1371 if ((tmp & R3_FNC) == 0) { 1372 (void) WAIT_STATR_BITSET(R0_MIRQ); 1373 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1374 } 1375 1376 do { 1377 dummy = sc_cmonr; 1378 DMAC_WAIT0; 1379 if ((dummy & R4_MBSY) == 0) 1380 return; 1381 } while ((dummy & R4_MREQ) == 0); 1382 SET_CMD(sc, SCMD_NGT_ATN); 1383 (void)WAIT_STATR_BITCLR(R0_CIP); 1384 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1385 1386 dummy = sc_cmonr; 1387 DMAC_WAIT0; 1388 if ((dummy & R4_MREQ) == 0) { 1389 printf("sc_mout: !REQ cmonr=%x\n", dummy); 1390 print_scsi_stat(sc); 1391 scsi_hardreset(); 1392 return; 1393 } 1394 1395 SET_CMD(sc, SCMD_TR_INFO); 1396 sc_datr = *mp++; 1397 DMAC_WAIT0; 1398 } else { 1399 dummy = sc_cmonr; 1400 DMAC_WAIT0; 1401 if (dummy & R4_MATN) { 1402 SET_CMD(sc, SCMD_NGT_ATN); 1403 (void) WAIT_STATR_BITCLR(R0_CIP); 1404 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1405 } 1406 1407 iloop = 0; 1408 do { 1409 dummy = sc_cmonr; 1410 DMAC_WAIT0; 1411 if (iloop++ > CHECK_LOOP_CNT) 1412 break; 1413 } while ((dummy & R4_MREQ) == 0); 1414 SET_CMD(sc, SCMD_TR_INFO); 1415 sc_datr = scb->identify; 1416 DMAC_WAIT0; 1417 } 1418 } else { 1419 dummy = sc_cmonr; 1420 DMAC_WAIT0; 1421 if (dummy & R4_MATN) { 1422 SET_CMD(sc, SCMD_NGT_ATN); 1423 (void) WAIT_STATR_BITCLR(R0_CIP); 1424 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1425 } 1426 1427 dummy = sc_cmonr; 1428 DMAC_WAIT0; 1429 if ((dummy & R4_MREQ) == 0) { 1430 printf("sc_mout: !REQ cmonr=%x\n", dummy); 1431 print_scsi_stat(sc); 1432 scsi_hardreset(); 1433 return; 1434 } 1435 1436 SET_CMD(sc, SCMD_TR_INFO); 1437 sc_datr = scb->message; 1438 DMAC_WAIT0; 1439 } 1440 } 1441 1442 /* 1443 * SCSI status accept routine 1444 */ 1445 void 1446 sc_sin(struct sc_softc *sc, volatile struct sc_chan_stat *cs) 1447 { 1448 uint8_t dummy; 1449 int iloop; 1450 1451 flush_fifo(sc); 1452 1453 dummy = sc_cmonr; 1454 DMAC_WAIT0; 1455 if ((dummy & R4_MREQ) == 0) { 1456 printf("sc_sin: !REQ cmonr=%x\n", dummy); 1457 print_scsi_stat(sc); 1458 scsi_hardreset(); 1459 return; 1460 } 1461 1462 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE|Rb_RMSG; 1463 DMAC_WAIT0; 1464 1465 SET_CMD(sc, SCMD_TR_INFO); 1466 1467 (void)WAIT_STATR_BITCLR(R0_CIP); 1468 1469 sc->int_stat2 &= ~R3_FNC; 1470 iloop = 0; 1471 do { 1472 if (iloop++ > CHECK_LOOP_CNT) 1473 break; 1474 GET_INTR(&sc->int_stat1, &sc->int_stat2); /* clear interrupt */ 1475 } while ((sc->int_stat2 & R3_FNC) == 0); 1476 sc->int_stat2 &= ~R3_FNC; 1477 1478 cs->scb->tstatus = sc_datr; /* get status byte */ 1479 DMAC_WAIT0; 1480 } 1481 1482 /* 1483 * SCSI data in/out routine 1484 */ 1485 void 1486 sc_dio(struct sc_softc *sc, volatile struct sc_chan_stat *cs) 1487 { 1488 struct sc_scb *scb; 1489 int i; 1490 int pages; 1491 uint8_t tag; 1492 uint32_t pfn; 1493 uint8_t phase; 1494 struct scsipi_xfer *xs; 1495 1496 scb = cs->scb; 1497 xs = scb->xs; 1498 1499 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE; 1500 DMAC_WAIT0; 1501 1502 if (cs->act_trcnt <= 0) { 1503 sc_dio_pad(sc, cs); 1504 return; 1505 } 1506 1507 switch (xs->cmd->opcode) { 1508 1509 case SCOP_READ: 1510 case SCOP_WRITE: 1511 case SCOP_EREAD: 1512 case SCOP_EWRITE: 1513 i = (cs->act_trcnt + DEV_BSIZE -1) / DEV_BSIZE; 1514 i *= DEV_BSIZE; 1515 break; 1516 1517 default: 1518 i = cs->act_trcnt; 1519 break; 1520 } 1521 1522 SET_CNT(i); 1523 sc->pad_cnt[cs->chan_num] = i - cs->act_trcnt; 1524 1525 phase = sc_cmonr & SC_PMASK; 1526 DMAC_WAIT0; 1527 if (phase == DAT_IN) { 1528 if (sc_syncr == OFF) { 1529 DMAC_WAIT0; 1530 flush_fifo(sc); 1531 } 1532 } 1533 1534 #if defined(__mips__) && defined(CPU_SINGLE) 1535 SET_CMD(sc, SCMD_TR_INFO|R0_DMA|R0_TRBE); 1536 #endif 1537 1538 #if defined(__mips__) && defined(CPU_SINGLE) 1539 dmac_gsel = CH_SCSI; 1540 dmac_ctrcl = (uint8_t)(cs->act_trcnt & 0xff); 1541 dmac_ctrcm = (uint8_t)((cs->act_trcnt >> 8) & 0xff); 1542 dmac_ctrch = (uint8_t)((cs->act_trcnt >> 16) & 0x0f); 1543 dmac_cofsh = (uint8_t)((cs->act_offset >> 8) & 0xf); 1544 dmac_cofsl = (uint8_t)(cs->act_offset & 0xff); 1545 #endif 1546 tag = 0; 1547 1548 if (scb->sc_map && (scb->sc_map->mp_pages > 0)) { 1549 /* 1550 * Set DMAC map entry from map table 1551 */ 1552 pages = scb->sc_map->mp_pages; 1553 for (i = cs->act_tag; i < pages; i++) { 1554 if ((pfn = scb->sc_map->mp_addr[i]) == 0) 1555 panic("SCSI:sc_dma() zero entry"); 1556 #if defined(__mips__) && defined(CPU_SINGLE) 1557 dmac_gsel = CH_SCSI; 1558 dmac_ctag = (uint8_t)tag++; 1559 dmac_cmap = (uint16_t)pfn; 1560 #endif 1561 } 1562 #ifdef MAP_OVER_ACCESS 1563 # if defined(__mips__) && defined(CPU_SINGLE) 1564 dmac_gsel = CH_SCSI; 1565 dmac_ctag = (uint8_t)tag++; 1566 dmac_cmap = (uint16_t)pfn; 1567 # endif 1568 #endif 1569 } else { 1570 /* 1571 * Set DMAC map entry from logical address 1572 */ 1573 pfn = kvtophys((vaddr_t)cs->act_point) >> PGSHIFT; 1574 pages = (cs->act_trcnt >> PGSHIFT) + 2; 1575 for (i = 0; i < pages; i++) { 1576 #if defined(__mips__) && defined(CPU_SINGLE) 1577 dmac_gsel = CH_SCSI; 1578 dmac_ctag = (uint8_t)tag++; 1579 dmac_cmap = (uint8_t)pfn + i; 1580 #endif 1581 } 1582 } 1583 1584 #if defined(__mips__) && defined(CPU_SINGLE) 1585 dmac_gsel = CH_SCSI; 1586 dmac_ctag = 0; 1587 #endif 1588 1589 if (phase == DAT_IN) { 1590 sc->dma_stat = SC_DMAC_RD; 1591 #if defined(__mips__) && defined(CPU_SINGLE) 1592 /* 1593 * auto pad flag is always on 1594 */ 1595 dmac_gsel = CH_SCSI; 1596 dmac_cctl = DM_MODE|DM_APAD; 1597 DMAC_WAIT; 1598 dmac_cctl = DM_MODE|DM_APAD|DM_ENABLE; 1599 DMAC_WAIT0; 1600 #endif 1601 } 1602 else if (phase == DAT_OUT) { 1603 sc->dma_stat = SC_DMAC_WR; 1604 #if defined(__mips__) && defined(CPU_SINGLE) 1605 dmac_gsel = CH_SCSI; 1606 dmac_cctl = DM_APAD; 1607 DMAC_WAIT; 1608 dmac_cctl = DM_APAD|DM_ENABLE; 1609 DMAC_WAIT0; 1610 #endif 1611 /* DMAC start on mem->I/O */ 1612 } 1613 } 1614 1615 #define MAX_TR_CNT24 ((1 << 24) -1) 1616 void 1617 sc_dio_pad(struct sc_softc *sc, volatile struct sc_chan_stat *cs) 1618 { 1619 uint8_t dummy; 1620 1621 if (cs->act_trcnt >= 0) 1622 return; 1623 sc->pad_start = 1; 1624 1625 SET_CNT(MAX_TR_CNT24); 1626 SET_CMD(sc, SCMD_TR_PAD|R0_TRBE); 1627 dummy = sc_cmonr & SC_PMASK; 1628 DMAC_WAIT0; 1629 if (dummy == DAT_IN) 1630 dummy = sc_datr; /* get data */ 1631 else 1632 sc_datr = 0; /* send data */ 1633 } 1634 1635 void 1636 print_scsi_stat(struct sc_softc *sc) 1637 { 1638 1639 printf("ipc=%d wrc=%d wbc=%d\n", sc->ipc, sc->wrc, sc->wbc); 1640 } 1641 1642 /* 1643 * return 0 if it was done. Or retun TRUE if it is busy. 1644 */ 1645 int 1646 sc_busy(struct sc_softc *sc, int chan) 1647 { 1648 1649 return (int)sc->chan_stat[chan].scb; 1650 } 1651 1652 1653 /* 1654 * append channel into Waiting Bus_free queue 1655 */ 1656 void 1657 append_wb(struct sc_softc *sc, struct sc_chan_stat *cs) 1658 { 1659 int s; 1660 1661 s = splclock(); /* inhibit process switch */ 1662 if (sc->wbq_actf == NULL) 1663 sc->wbq_actf = cs; 1664 else 1665 sc->wbq_actl->wb_next = cs; 1666 sc->wbq_actl = cs; 1667 cs->scb->istatus = INST_WAIT; 1668 sc->wbc++; 1669 splx(s); 1670 } 1671 1672 /* 1673 * get channel from Waiting Bus_free queue 1674 */ 1675 struct sc_chan_stat * 1676 get_wb_chan(struct sc_softc *sc) 1677 { 1678 struct sc_chan_stat *cs; 1679 int s; 1680 1681 s = splclock(); /* inhibit process switch */ 1682 cs = sc->wbq_actf; 1683 if (cs && cs->chan_num == SC_OWNID) /* needed? */ 1684 cs = NULL; 1685 splx(s); 1686 return cs; 1687 } 1688 1689 /* 1690 * release channel from Waiting Bus_free queue 1691 */ 1692 int 1693 release_wb(struct sc_softc *sc) 1694 { 1695 struct sc_chan_stat *cs; 1696 int error = 0; 1697 int s; 1698 1699 s = splclock(); /* inhibit process switch */ 1700 if (sc->wbq_actf == NULL) { 1701 error = -1; 1702 } else { 1703 cs = sc->wbq_actf; 1704 sc->wbq_actf = cs->wb_next; 1705 cs->wb_next = NULL; 1706 if (sc->wbq_actl == cs) 1707 sc->wbq_actl = NULL; 1708 cs->scb->istatus &= ~INST_WAIT; 1709 sc->wbc--; 1710 } 1711 splx(s); 1712 return error; 1713 } 1714 1715 void 1716 adjust_transfer(struct sc_softc *sc, struct sc_chan_stat *cs) 1717 { 1718 struct sc_scb *scb = cs->scb; 1719 u_int remain_cnt; 1720 u_int offset, sent_byte; 1721 1722 if (sc->pad_start) { 1723 sc->pad_start = 0; 1724 remain_cnt = 0; 1725 } else { 1726 # if defined(__mips__) && defined(CPU_SINGLE) 1727 remain_cnt = GET_CNT(); 1728 remain_cnt -= sc->pad_cnt[cs->chan_num]; 1729 if (sc->dma_stat == SC_DMAC_WR) { 1730 /* 1731 * adjust counter in the FIFO 1732 */ 1733 remain_cnt += sc_ffstr & R5_FIFOREM; 1734 } 1735 # endif 1736 } 1737 1738 sent_byte = scb->sc_ctrnscnt - remain_cnt; 1739 cs->act_trcnt = remain_cnt; 1740 1741 offset = scb->sc_coffset + sent_byte; 1742 cs->act_tag += (offset >> PGSHIFT); 1743 cs->act_offset = offset & PGOFSET; 1744 if ((scb->sc_map == NULL) || (scb->sc_map->mp_pages <= 0)) 1745 cs->act_point += sent_byte; 1746 } 1747 1748 #ifdef __mips__ 1749 static void 1750 clean_k2dcache(struct sc_scb *scb) 1751 { 1752 struct sc_map *sc_map = scb->sc_map; 1753 paddr_t pa; 1754 int i, pages; 1755 1756 pa = kvtophys((vaddr_t)scb->msgbuf); 1757 mips_dcache_wbinv_range_index(MIPS_PHYS_TO_KSEG0(pa), 1758 sizeof(scb->msgbuf)); 1759 1760 if (MACH_IS_USPACE(scb->sc_cpoint)) 1761 panic("clean_k2dcache: user address is not supported"); 1762 1763 if (MACH_IS_CACHED(scb->sc_cpoint)) { 1764 mips_dcache_wbinv_range_index((vaddr_t)scb->sc_cpoint, 1765 scb->sc_ctrnscnt); 1766 return; 1767 } 1768 1769 if (sc_map) { 1770 pages = sc_map->mp_pages; 1771 for (i = 0; i < pages; i++) { 1772 pa = sc_map->mp_addr[i] << PGSHIFT; 1773 mips_dcache_wbinv_range_index(MIPS_PHYS_TO_KSEG0(pa), 1774 PAGE_SIZE); 1775 } 1776 } 1777 } 1778 #endif 1779
Indexes created Mon Sep 29 21:09:56 GMT 2025