scsi_1185.c revision 1.8
1 /* $NetBSD: scsi_1185.c,v 1.8 2001/11/14 18:15:30 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: $Hdr: scsi_1185.c,v 4.300 91/06/09 06:22:20 root Rel41 $ SONY 39 * 40 * @(#)scsi_1185.c 8.1 (Berkeley) 6/11/93 41 */ 42 43 /* 44 * Copyright (c) 1989- by SONY Corporation. 45 * 46 * scsi_1185.c 47 * 48 * CXD1185Q 49 * SCSI bus low level common routines 50 * for one cpu machine 51 * 52 * MODIFY HISTORY: 53 * 54 * DMAC_WAIT --- DMAC_0266 wo tukau-baai, DMAC mata-wa SCSI-chip ni 55 * tuzukete access suru-baai, 56 * kanarazu wait wo ireru-beshi ! 57 */ 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/device.h> 62 63 #include <dev/scsipi/scsi_all.h> 64 #include <dev/scsipi/scsipi_all.h> 65 #include <dev/scsipi/scsiconf.h> 66 67 #include <machine/cpu.h> 68 #include <machine/intr.h> 69 #include <machine/machConst.h> 70 71 #include <mips/cache.h> 72 73 #include <newsmips/dev/screg_1185.h> 74 #include <newsmips/dev/scsireg.h> 75 76 #if defined(news3400) 77 # include <newsmips/dev/dmac_0448.h> 78 # ifndef NDMACMAP 79 # define NDMACMAP 144 80 # endif 81 #endif 82 83 #define VOLATILE volatile 84 #define ABORT_SYNCTR_MES_FROM_TARGET 85 #define SCSI_1185AQ 86 #define RESET_RECOVER 87 #define DMAC_MAP_INIT /* for nws-3700 parity error */ 88 #define APAD_ALWAYS_ON 89 90 #define CHECK_LOOP_CNT 60 91 #define RSL_LOOP_CNT 60 92 93 #ifndef DMAC_MAP_INIT 94 # define MAP_OVER_ACCESS /* for nws-3700 parity error */ 95 #endif 96 97 #undef CHECK_MRQ 98 99 #ifdef NOT_SUPPORT_SYNCTR 100 # define MAX_OFFSET_BYTES 0 101 #else 102 # define MAX_OFFSET_BYTES MAX_OFFSET 103 #endif 104 105 #define act_point spoint 106 #define act_trcnt stcnt 107 #define act_tag stag 108 #define act_offset soffset 109 110 #define splscsi splsc 111 112 #if defined(mips) && defined(CPU_SINGLE) 113 #define nops(x) { int i; for (i = 0; i < (x); i++) ; } 114 #define DMAC_WAIT0 ; 115 #else 116 #define DMAC_WAIT0 DMAC_WAIT 117 #endif 118 119 #ifdef DMAC_MAP_INIT 120 static int dmac_map_init = 0; 121 #endif 122 123 /* 124 * command flag status 125 */ 126 #define CF_SET 1 127 #define CF_SEND 2 128 #define CF_ENOUGH 3 129 #define CF_EXEC 4 130 131 #define SEL_TIMEOUT_VALUE 0x7a 132 133 extern struct cfdriver sc_cd; 134 135 void sc_send __P((struct sc_scb *, int, int)); 136 int scintr __P((void)); 137 void scsi_hardreset __P((void)); 138 void scsi_chipreset __P((struct sc_softc *)); 139 void scsi_softreset __P((struct sc_softc *)); 140 int sc_busy __P((struct sc_softc *, int)); 141 142 static int WAIT_STATR_BITCLR __P((int)); 143 static int WAIT_STATR_BITSET __P((int)); 144 static void SET_CMD __P((struct sc_softc *, int)); 145 static void SET_CNT __P((int)); 146 static int GET_CNT __P((void)); 147 static void GET_INTR __P((VOLATILE int *, VOLATILE int *)); 148 static void sc_start __P((struct sc_softc *)); 149 static void sc_resel __P((struct sc_softc *)); 150 static void sc_discon __P((struct sc_softc *)); 151 static void sc_pmatch __P((struct sc_softc *)); 152 static void flush_fifo __P((struct sc_softc *)); 153 static void sc_cout __P((struct sc_softc *, struct sc_chan_stat *)); 154 static void sc_min __P((struct sc_softc *, struct sc_chan_stat *)); 155 static void sc_mout __P((struct sc_softc *, struct sc_chan_stat *)); 156 static void sc_sin __P((struct sc_softc *, VOLATILE struct sc_chan_stat *)); 157 static void sc_dio __P((struct sc_softc *, VOLATILE struct sc_chan_stat *)); 158 static void sc_dio_pad __P((struct sc_softc *, VOLATILE struct sc_chan_stat *)); 159 static void print_scsi_stat __P((struct sc_softc *)); 160 static void append_wb __P((struct sc_softc *, struct sc_chan_stat *)); 161 static struct sc_chan_stat *get_wb_chan __P((struct sc_softc *)); 162 static int release_wb __P((struct sc_softc *)); 163 static void adjust_transfer __P((struct sc_softc *, struct sc_chan_stat *)); 164 static void clean_k2dcache __P((struct sc_scb *)); 165 166 extern void sc_done __P((struct sc_scb *)); 167 extern paddr_t kvtophys __P((vaddr_t)); 168 169 #if defined(mips) && defined(CPU_SINGLE) 170 #define dma_reset(x) { \ 171 int s = splscsi(); \ 172 dmac_gsel = (x); dmac_cctl = DM_RST; dmac_cctl = 0; \ 173 splx(s); \ 174 } 175 #endif 176 177 int 178 WAIT_STATR_BITCLR(bitmask) 179 register int bitmask; 180 { 181 register int iloop; 182 register VOLATILE int dummy; 183 184 iloop = 0; 185 do { 186 dummy = sc_statr; 187 DMAC_WAIT0; 188 if (iloop++ > CHECK_LOOP_CNT) 189 return (-1); 190 } while (dummy & bitmask); 191 return (0); 192 } 193 194 int 195 WAIT_STATR_BITSET(bitmask) 196 register int bitmask; 197 { 198 register int iloop; 199 register VOLATILE int dummy; 200 201 iloop = 0; 202 do { 203 dummy = sc_statr; 204 DMAC_WAIT0; 205 if (iloop++ > CHECK_LOOP_CNT) 206 return (-1); 207 } while ((dummy & bitmask) == 0); 208 return (0); 209 } 210 211 void 212 SET_CMD(sc, CMD) 213 struct sc_softc *sc; 214 register int CMD; 215 { 216 (void) WAIT_STATR_BITCLR(R0_CIP); 217 sc->lastcmd = (CMD); 218 sc_comr = (CMD); 219 DMAC_WAIT0; 220 } 221 222 void 223 SET_CNT(COUNT) 224 register int COUNT; 225 { 226 sc_tclow = (COUNT) & 0xff; 227 DMAC_WAIT0; 228 sc_tcmid = ((COUNT) >> 8) & 0xff; 229 DMAC_WAIT0; 230 sc_tchi = ((COUNT) >> 16) & 0xff; 231 DMAC_WAIT0; 232 } 233 234 int 235 GET_CNT() 236 { 237 register VOLATILE int COUNT; 238 239 COUNT = sc_tclow; 240 DMAC_WAIT0; 241 COUNT += (sc_tcmid << 8) & 0xff00; 242 DMAC_WAIT0; 243 COUNT += (sc_tchi << 16) & 0xff0000; 244 DMAC_WAIT0; 245 return (COUNT); 246 } 247 248 void 249 GET_INTR(DATA1, DATA2) 250 register VOLATILE int *DATA1; 251 register VOLATILE int *DATA2; 252 { 253 (void) WAIT_STATR_BITCLR(R0_CIP); 254 while (sc_statr & R0_MIRQ) { 255 DMAC_WAIT0; 256 *DATA1 |= sc_intrq1; 257 DMAC_WAIT0; 258 *DATA2 |= sc_intrq2; 259 DMAC_WAIT0; 260 } 261 } 262 263 264 void 265 sc_send(scb, chan, ie) 266 struct sc_scb *scb; 267 int chan, ie; 268 { 269 struct sc_softc *sc = scb->scb_softc; 270 struct sc_chan_stat *cs; 271 struct scsipi_xfer *xs; 272 int i; 273 u_char *p; 274 275 cs = &sc->chan_stat[chan]; 276 xs = scb->xs; 277 278 p = (u_char *)xs->cmd; 279 if (cs->scb != NULL) { 280 printf("SCSI%d: sc_send() NOT NULL cs->sc\n", chan); 281 printf("ie=0x%x scb=0x%p cs->sc=0x%p\n", ie, scb, cs->scb); 282 printf("cdb="); 283 for (i = 0; i < 6; i++) 284 printf(" 0x%x", *p++); 285 printf("\n"); 286 panic("SCSI soft error"); 287 /*NOTREACHED*/ 288 } 289 290 if (p[0] == SCOP_RESET && p[1] == SCOP_RESET) { 291 /* 292 * SCSI bus reset command procedure 293 * (vender unique by Sony Corp.) 294 */ 295 #ifdef SCSI_1185AQ 296 if (sc_idenr & 0x08) 297 sc->scsi_1185AQ = 1; 298 else 299 sc->scsi_1185AQ = 0; 300 #endif 301 cs->scb = scb; 302 scsi_hardreset(); 303 scb->istatus = INST_EP; 304 cs->scb = NULL; 305 sc_done(scb); 306 return; 307 } 308 309 if (scb->sc_map && (scb->sc_map->mp_pages > 0)) { 310 /* 311 * use map table 312 */ 313 scb->sc_coffset = scb->sc_map->mp_offset & PGOFSET; 314 if (scb->sc_map->mp_pages > NSCMAP) { 315 printf("SCSI%d: map table overflow\n", chan); 316 scb->istatus = INST_EP|INST_LB|INST_PRE; 317 return; 318 } 319 } else { 320 /* 321 * no use map table 322 */ 323 scb->sc_coffset = (u_int)scb->sc_cpoint & PGOFSET; 324 } 325 scb->sc_ctag = 0; 326 327 cs->scb = scb; 328 cs->comflg = OFF; 329 330 cs->intr_flg = ie; 331 cs->chan_num = chan; 332 sc->perr_flag[chan] = 0; 333 sc->mout_flag[chan] = 0; 334 sc->min_cnt[chan] = 0; 335 336 sc->sel_stat[chan] = SEL_WAIT; 337 append_wb(sc, cs); 338 sc_start(sc); 339 } 340 341 /* 342 * SCSI start up routine 343 */ 344 void 345 sc_start(sc) 346 struct sc_softc *sc; 347 { 348 struct sc_chan_stat *cs; 349 int chan, dummy; 350 int s; 351 352 s = splscsi(); 353 cs = get_wb_chan(sc); 354 if ((cs == NULL) || (sc->ipc >= 0)) 355 goto sc_start_exit; 356 chan = cs->chan_num; 357 if (sc->sel_stat[chan] != SEL_WAIT) { 358 /* 359 * already started 360 */ 361 goto sc_start_exit; 362 } 363 sc->sel_stat[chan] = SEL_START; 364 365 dummy = sc_cmonr; 366 DMAC_WAIT0; 367 if (dummy & (R4_MBSY|R4_MSEL)) { 368 sc->sel_stat[chan] = SEL_WAIT; 369 goto sc_start_exit; 370 } 371 372 /* 373 * send SELECT with ATN command 374 */ 375 sc->dma_stat = OFF; 376 sc->pad_start = 0; 377 dummy = sc_statr; 378 DMAC_WAIT0; 379 if (dummy & R0_CIP) { 380 sc->sel_stat[chan] = SEL_WAIT; 381 goto sc_start_exit; 382 } 383 sc_idenr = (chan << SC_TG_SHIFT) | SC_OWNID; 384 DMAC_WAIT0; 385 #ifdef SCSI_1185AQ 386 if (sc->scsi_1185AQ) 387 sc_intok1 = Ra_STO|Ra_ARBF; 388 else 389 sc_intok1 = Ra_STO|Ra_RSL|Ra_ARBF; 390 #else 391 sc_intok1 = Ra_STO|Ra_RSL|Ra_ARBF; 392 #endif 393 DMAC_WAIT0; 394 /* 395 * BUGFIX for signal reflection on BSY 396 * !Rb_DCNT 397 */ 398 sc_intok2 = Rb_FNC|Rb_SRST|Rb_PHC|Rb_SPE; 399 DMAC_WAIT0; 400 401 dummy = sc_cmonr; 402 DMAC_WAIT0; 403 if (dummy & (R4_MBSY|R4_MSEL)) { 404 sc->sel_stat[chan] = SEL_WAIT; 405 goto sc_start_exit; 406 } 407 SET_CMD(sc, SCMD_SEL_ATN); 408 409 sc_start_exit: 410 splx(s); 411 } 412 413 /* 414 * SCSI interrupt service routine 415 */ 416 int 417 scintr() 418 { 419 register int iloop; 420 register VOLATILE int chan; 421 register VOLATILE int dummy; 422 struct sc_softc *sc; 423 struct sc_chan_stat *cs; 424 int s_int1, s_int2; 425 426 sc = sc_cd.cd_devs[0]; /* XXX */ 427 428 scintr_loop: 429 430 #if defined(CHECK_MRQ) && defined(news3400) 431 while (dmac_gstat & CH_MRQ(CH_SCSI)) 432 DMAC_WAIT; 433 #endif 434 435 for (iloop = 0; iloop < 100; iloop++) { 436 dummy = sc_statr; 437 DMAC_WAIT; 438 if ((dummy & R0_CIP) == 0) 439 break; 440 } 441 442 /* 443 * get SCSI interrupt request 444 */ 445 while (sc_statr & R0_MIRQ) { 446 DMAC_WAIT0; 447 s_int1 = sc_intrq1; 448 DMAC_WAIT0; 449 s_int2 = sc_intrq2; 450 DMAC_WAIT0; 451 sc->int_stat1 |= s_int1; 452 sc->int_stat2 |= s_int2; 453 } 454 455 if (sc->int_stat2 & R3_SRST) { 456 /* 457 * RST signal is drived 458 */ 459 sc->int_stat2 &= ~R3_SRST; 460 scsi_softreset(sc); 461 goto scintr_exit; 462 } 463 464 if ((sc->ipc < 0) && (sc->wrc <= 0) && (sc->wbc <= 0)) { 465 sc->int_stat1 = 0; 466 sc->int_stat2 = 0; 467 goto scintr_exit; 468 } 469 470 cs = get_wb_chan(sc); 471 if (cs) chan = cs->chan_num; 472 473 if (cs && (sc->sel_stat[chan] == SEL_START) && 474 (sc->lastcmd == SCMD_SEL_ATN)) { 475 /* 476 * Check the result of SELECTION command 477 */ 478 if (sc->int_stat1 & R2_RSL) { 479 /* 480 * RESELECTION occur 481 */ 482 if (sc->wrc > 0) { 483 sc->sel_stat[chan] = SEL_RSLD; 484 } else { 485 /* 486 * Ghost RESELECTION ??? 487 */ 488 sc->int_stat1 &= ~R2_RSL; 489 } 490 } 491 if (sc->int_stat1 & R2_ARBF) { 492 /* 493 * ARBITRATION fault 494 */ 495 sc->int_stat1 &= ~R2_ARBF; 496 sc->sel_stat[chan] = SEL_ARBF; 497 } 498 if (sc->int_stat1 & R2_STO) { 499 /* 500 * SELECTION timeout 501 */ 502 sc->int_stat1 &= ~R2_STO; 503 if ((sc->int_stat2&(R3_PHC|R3_RMSG)) != (R3_PHC|R3_RMSG)) { 504 sc->ipc = chan; 505 sc->ip = &sc->chan_stat[chan]; 506 sc->sel_stat[chan] = SEL_TIMEOUT; 507 sc->chan_stat[chan].scb->istatus 508 = INST_EP|INST_TO; 509 release_wb(sc); 510 } 511 } 512 513 /* 514 * SELECTION command done 515 */ 516 switch (sc->sel_stat[chan]) { 517 518 case SEL_START: 519 if ((sc->int_stat2 & R3_FNC) == 0) 520 break; 521 /* 522 * SELECTION success 523 */ 524 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE; 525 sc->ipc = chan; 526 sc->ip = &sc->chan_stat[chan]; 527 sc->ip->scb->istatus |= INST_IP; 528 sc->dma_stat = OFF; 529 sc->pad_start = 0; 530 sc->sel_stat[chan] = SEL_SUCCESS; 531 release_wb(sc); 532 #ifndef NOT_SUPPORT_SYNCTR 533 sc_syncr = sc->sync_tr[chan]; 534 DMAC_WAIT0; 535 #endif 536 DMAC_WAIT0; 537 break; 538 539 case SEL_TIMEOUT: 540 /* 541 * SELECTION time out 542 */ 543 sc_discon(sc); 544 goto scintr_exit; 545 546 /* case SEL_RSLD: */ 547 /* case SEL_ARBF: */ 548 default: 549 /* 550 * SELECTION failed 551 */ 552 sc->sel_stat[chan] = SEL_WAIT; 553 break; 554 } 555 if ((sc->int_stat1 & R2_RSL) == 0) 556 sc->int_stat2 &= ~R3_FNC; 557 } 558 559 if (sc->ip != NULL) { 560 /* 561 * check In Process channel's request 562 */ 563 if (sc->dma_stat != OFF) { 564 /* 565 * adjust pointer & counter 566 */ 567 adjust_transfer(sc, sc->ip); 568 } 569 if (sc->int_stat2 & R3_SPE) { 570 register int VOLATILE statr; 571 register int VOLATILE cmonr; 572 573 statr = sc_statr; 574 DMAC_WAIT0; 575 cmonr = sc_cmonr; 576 sc->int_stat2 &= ~R3_SPE; 577 sc->perr_flag[sc->ip->chan_num] = 1; 578 } 579 } 580 581 if (sc->int_stat2 & R3_DCNT) { 582 /* 583 * Bus Free 584 */ 585 sc_discon(sc); 586 sc->int_stat2 &= ~R3_DCNT; 587 } 588 589 if ((sc->ipc >= 0) && (sc->sel_stat[sc->ipc] == SEL_RSL_WAIT)) { 590 sc->sel_stat[sc->ipc] = SEL_RSLD; 591 sc->ipc = -1; 592 sc->int_stat1 |= R2_RSL; 593 } 594 if (sc->int_stat1 & R2_RSL) { 595 /* 596 * Reselection 597 */ 598 sc_resel(sc); 599 sc->int_stat1 &= ~R2_RSL; 600 if (sc->sel_stat[sc->ipc] == SEL_RSL_WAIT) 601 goto scintr_exit; 602 } 603 604 605 if ((sc->ipc >= 0) && (sc->ipc != SC_OWNID) && 606 (sc->sel_stat[sc->ipc] == SEL_SUCCESS)) { 607 if (sc->int_stat2 & R3_PHC) { 608 /* 609 * Phase change 610 */ 611 sc->int_stat2 &= ~(R3_PHC|R3_RMSG); 612 sc_pmatch(sc); 613 } else if (sc->int_stat2 & R3_RMSG) { 614 /* 615 * message Phase 616 */ 617 if (sc->min_flag > 0) { 618 sc->int_stat2 &= ~(R3_PHC|R3_RMSG); 619 sc_pmatch(sc); 620 } 621 } 622 else if (sc->dma_stat != OFF) { 623 dummy = sc_cmonr; 624 DMAC_WAIT0; 625 if ((dummy & (R4_MMSG|R4_MCD|R4_MREQ)) == R4_MREQ) { 626 /* 627 * still DATA transfer phase 628 */ 629 sc_dio_pad(sc, sc->ip); 630 } 631 } 632 else if (sc->ip->comflg == CF_SEND) { 633 dummy = sc_cmonr; 634 DMAC_WAIT0; 635 if ((dummy & SC_PMASK) == COM_OUT) { 636 /* 637 * command out phase 638 */ 639 sc_cout(sc, sc->ip); 640 } 641 } 642 } else { 643 if (sc->int_stat2 & (R3_PHC|R3_RMSG)) 644 goto scintr_exit; 645 } 646 647 if ((sc->int_stat1 & (R2_STO|R2_RSL|R2_ARBF)) 648 || (sc->int_stat2 & (R3_DCNT|R3_SRST|R3_PHC|R3_SPE))) { 649 /* 650 * still remain intrq 651 */ 652 goto scintr_loop; 653 } 654 655 scintr_exit: 656 return (1); 657 } 658 659 /* 660 * SCSI bus reset routine 661 * scsi_hardreset() is occered a reset interrupt. 662 * And call scsi_softreset(). 663 */ 664 void 665 scsi_hardreset() 666 { 667 register int s; 668 #ifdef DMAC_MAP_INIT 669 register int i; 670 #endif 671 struct sc_softc *sc; 672 673 sc = sc_cd.cd_devs[0]; /* XXX */ 674 s = splscsi(); 675 676 scsi_chipreset(sc); 677 DMAC_WAIT0; 678 sc->int_stat1 = 0; 679 sc->int_stat2 = 0; 680 SET_CMD(sc, SCMD_AST_RST); /* assert RST signal */ 681 682 #ifdef DMAC_MAP_INIT 683 if (dmac_map_init == 0) { 684 dmac_map_init++; 685 for (i = 0; i < NDMACMAP; i++) { 686 # if defined(mips) && defined(CPU_SINGLE) 687 dmac_gsel = CH_SCSI; 688 dmac_ctag = (u_char)i; 689 dmac_cmap = (u_short)0; 690 # endif 691 } 692 } 693 #endif 694 /*cxd1185_init();*/ 695 splx(s); 696 } 697 698 /* 699 * I/O port (sc_ioptr) bit assign 700 * 701 * Rf_PRT3 - <reserved> 702 * Rf_PRT2 - <reserved> 703 * Rf_PRT1 out Floppy Disk Density control 704 * Rf_PRT0 out Floppy Disk Eject control 705 */ 706 707 void 708 scsi_chipreset(sc) 709 struct sc_softc *sc; 710 { 711 register int s; 712 register VOLATILE int save_ioptr; 713 714 s = splscsi(); 715 716 #if defined(mips) && defined(CPU_SINGLE) 717 dmac_gsel = CH_SCSI; 718 dmac_cwid = 4; /* initialize DMAC SCSI chan */ 719 *(unsigned VOLATILE char *)PINTEN |= DMA_INTEN; 720 dma_reset(CH_SCSI); 721 #endif 722 sc_envir = 0; /* 1/4 clock */ 723 DMAC_WAIT0; 724 save_ioptr = sc_ioptr; 725 DMAC_WAIT0; 726 sc->lastcmd = SCMD_CHIP_RST; 727 sc_comr = SCMD_CHIP_RST; /* reset chip */ 728 DMAC_WAIT; 729 (void) WAIT_STATR_BITCLR(R0_CIP); 730 /* 731 * SCMD_CHIP_RST command reset all register 732 * except sc_statr<7:6> & sc_cmonr. 733 * So, bit R0_MIRQ & R3_FNC will be not set. 734 */ 735 sc_idenr = SC_OWNID; 736 DMAC_WAIT0; 737 738 sc_intok1 = Ra_STO|Ra_RSL|Ra_ARBF; 739 DMAC_WAIT0; 740 sc_intok2 = Rb_FNC|Rb_SRST|Rb_PHC|Rb_SPE|Rb_RMSG; 741 DMAC_WAIT0; 742 743 sc_ioptr = save_ioptr; 744 DMAC_WAIT; 745 746 sc_moder = Rc_TMSL; /* RST drive time = 25.5 us */ 747 DMAC_WAIT0; 748 sc_timer = 0x2; 749 DMAC_WAIT0; 750 751 sc_moder = Rc_SPHI; /* selection timeout = 252 ms */ 752 DMAC_WAIT0; 753 sc_timer = SEL_TIMEOUT_VALUE; 754 DMAC_WAIT0; 755 756 #ifdef SCSI_1185AQ 757 if (sc->scsi_1185AQ) 758 SET_CMD(sc, SCMD_ENB_SEL); /* enable reselection */ 759 #endif 760 761 sc->int_stat1 &= ~R2_RSL; /* ignore RSL inter request */ 762 763 splx(s); 764 } 765 766 void 767 scsi_softreset(sc) 768 struct sc_softc *sc; 769 { 770 register VOLATILE struct sc_chan_stat *cs; 771 int i; 772 /* register int (*handler)(); */ 773 774 sc->wbq_actf = NULL; 775 sc->wbq_actl = NULL; 776 sc->wbc = 0; 777 sc->wrc = 0; 778 sc->ip = NULL; 779 sc->ipc = -1; 780 sc->dma_stat = OFF; 781 sc->pad_start = 0; 782 783 for (i = 0; i < NTARGET; ++i) { 784 if (i == SC_OWNID) 785 continue; 786 cs = &sc->chan_stat[i]; 787 cs->wb_next = NULL; 788 #ifndef NOT_SUPPORT_SYNCTR 789 sc->sync_tr[i] = 0; /* asynchronous mode */ 790 #endif 791 sc->sel_stat[i] = SEL_WAIT; 792 if (cs->scb != NULL) { 793 struct sc_scb *scb = cs->scb; 794 795 if ((cs->scb->istatus & INST_EP) == 0) 796 cs->scb->istatus = (INST_EP|INST_HE); 797 cs->scb = NULL; 798 #ifdef mips 799 clean_k2dcache(scb); 800 #endif 801 if (cs->intr_flg == SCSI_INTEN) { 802 intrcnt[SCSI_INTR]++; 803 #if 0 804 handler = scintsw[i].sci_inthandler; 805 if (handler) 806 (*handler)(scintsw[i].sci_ctlr); 807 #endif 808 } 809 sc_done(scb); 810 } 811 } 812 } 813 814 /* 815 * RESELECTION interrupt service routine 816 * ( RESELECTION phase ) 817 */ 818 void 819 sc_resel(sc) 820 struct sc_softc *sc; 821 { 822 register struct sc_chan_stat *cs; 823 register VOLATILE int chan; 824 register VOLATILE int statr; 825 register int iloop; 826 827 sc->min_flag = 0; 828 chan = (sc_idenr & R6_SID_MASK) >> SC_TG_SHIFT; 829 830 if (chan == SC_OWNID) 831 return; 832 833 statr = sc_statr; 834 DMAC_WAIT0; 835 if (statr & R0_CIP) { 836 if (sc->lastcmd == SCMD_SEL_ATN) { 837 /* 838 * SELECTION command dead lock ? 839 * save interrupt request 840 */ 841 while (sc_statr & R0_MIRQ) { 842 DMAC_WAIT0; 843 sc->int_stat1 |= sc_intrq1; 844 DMAC_WAIT0; 845 sc->int_stat2 |= sc_intrq2; 846 DMAC_WAIT0; 847 } 848 scsi_chipreset(sc); 849 } 850 } 851 852 cs = &sc->chan_stat[chan]; 853 if (cs->scb == NULL) { 854 scsi_hardreset(); 855 return; 856 } 857 if ((cs->scb->istatus & INST_WR) == 0) { 858 scsi_hardreset(); 859 return; 860 } 861 862 if (sc->ipc >= 0) { 863 scsi_hardreset(); 864 return; 865 } 866 867 sc->ip = cs; 868 sc->ipc = chan; 869 870 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE; 871 DMAC_WAIT0; 872 873 iloop = 0; 874 while ((sc->int_stat2 & R3_FNC) == 0) { 875 /* 876 * Max 6 usec wait 877 */ 878 if (iloop++ > RSL_LOOP_CNT) { 879 sc->sel_stat[chan] = SEL_RSL_WAIT; 880 return; 881 } 882 GET_INTR(&sc->int_stat1, &sc->int_stat2); 883 } 884 sc->int_stat2 &= ~R3_FNC; 885 886 sc->sel_stat[chan] = SEL_SUCCESS; 887 888 sc->wrc--; 889 sc->dma_stat = OFF; 890 sc->pad_start = 0; 891 cs->scb->istatus |= INST_IP; 892 cs->scb->istatus &= ~INST_WR; 893 894 #ifndef NOT_SUPPORT_SYNCTR 895 sc_syncr = sc->sync_tr[chan]; 896 DMAC_WAIT0; 897 #endif 898 } 899 900 /* 901 * DISCONNECT interrupt service routine 902 * ( Target disconnect / job done ) 903 */ 904 void 905 sc_discon(sc) 906 struct sc_softc *sc; 907 { 908 register VOLATILE struct sc_chan_stat *cs; 909 /* register int (*handler)(); */ 910 register VOLATILE int dummy; 911 912 /* 913 * Signal reflection on BSY has occurred. 914 * Not Bus Free Phase, ignore. 915 * 916 * But, CXD1185Q reset INIT bit of sc_statr. 917 * So, can't issue Transfer Information command. 918 * 919 * What shall we do ? Bus reset ? 920 */ 921 if ((sc->int_stat2 & R3_DCNT) && ((sc_intok2 & Rb_DCNT) == 0)) 922 return; 923 924 sc_intok2 = Rb_FNC|Rb_SRST|Rb_PHC|Rb_SPE; 925 DMAC_WAIT0; 926 927 sc->min_flag = 0; 928 dummy = sc_cmonr; 929 DMAC_WAIT0; 930 if (dummy & R4_MATN) { 931 SET_CMD(sc, SCMD_NGT_ATN); 932 (void) WAIT_STATR_BITSET(R0_MIRQ); 933 GET_INTR(&sc->int_stat1, &sc->int_stat2); /* clear interrupt */ 934 } 935 936 if ((sc->int_stat1 & R2_RSL) == 0) 937 sc->int_stat2 &= ~R3_FNC; 938 939 cs = sc->ip; 940 if ((cs == NULL) || (sc->ipc < 0)) 941 goto sc_discon_exit; 942 943 if ((sc->sel_stat[cs->chan_num] != SEL_SUCCESS) 944 && (sc->sel_stat[cs->chan_num] != SEL_TIMEOUT)) 945 printf("sc_discon: eh!\n"); 946 947 /* 948 * indicate abnormal terminate 949 */ 950 if ((cs->scb->istatus & (INST_EP|INST_WR)) == 0) 951 cs->scb->istatus |= (INST_EP|INST_PRE|INST_LB); 952 953 cs->scb->istatus &= ~INST_IP; 954 sc->dma_stat = OFF; 955 sc->pad_start = 0; 956 sc->ip = NULL; 957 sc->ipc = -1; 958 959 if ((cs->scb->istatus & INST_WR) == 0) { 960 struct sc_scb *scb = cs->scb; 961 962 if (sc->perr_flag[cs->chan_num] > 0) 963 cs->scb->istatus |= INST_EP|INST_PRE; 964 cs->scb = NULL; 965 #ifdef mips 966 clean_k2dcache(scb); 967 #endif 968 if (cs->intr_flg == SCSI_INTEN) { 969 intrcnt[SCSI_INTR]++; 970 #if 0 971 handler = scintsw[cs->chan_num].sci_inthandler; 972 if (handler) 973 (*handler)(scintsw[cs->chan_num].sci_ctlr); 974 #endif 975 } 976 sc_done(scb); 977 } 978 979 sc_discon_exit: 980 sc_start(sc); 981 } 982 983 /* 984 * SCSI phase match interrupt service routine 985 */ 986 void 987 sc_pmatch(sc) 988 struct sc_softc *sc; 989 { 990 struct sc_chan_stat *cs; 991 register VOLATILE int phase; 992 register VOLATILE int phase2; 993 register VOLATILE int cmonr; 994 995 sc->int_stat2 &= ~R3_FNC; /* XXXXXXXX */ 996 997 cs = sc->ip; 998 if (cs == NULL) 999 return; 1000 1001 #if defined(mips) && defined(CPU_SINGLE) 1002 dma_reset(CH_SCSI); 1003 #endif 1004 phase = sc_cmonr & SC_PMASK; 1005 DMAC_WAIT0; 1006 for (;;) { 1007 phase2 = phase; 1008 cmonr = sc_cmonr; 1009 DMAC_WAIT0; 1010 phase = cmonr & SC_PMASK; 1011 if (phase == phase2) { 1012 if ((phase == DAT_IN) || (phase == DAT_OUT)) 1013 break; 1014 else if (cmonr & R4_MREQ) 1015 break; 1016 } 1017 } 1018 1019 1020 sc->dma_stat = OFF; 1021 sc->pad_start = 0; 1022 1023 if (phase == COM_OUT) { 1024 sc->min_flag = 0; 1025 if (cs->comflg != CF_SEND) 1026 cs->comflg = CF_SET; 1027 sc_cout(sc, cs); 1028 } else { 1029 cs->comflg = CF_ENOUGH; 1030 sc_intok2 &= ~Rb_FNC; 1031 if (phase == MES_IN) { 1032 sc->min_flag++; 1033 sc_min(sc, cs); 1034 } else { 1035 sc->min_flag = 0; 1036 1037 switch (phase) { 1038 1039 case MES_OUT: 1040 sc_mout(sc, cs); 1041 break; 1042 1043 case DAT_IN: 1044 case DAT_OUT: 1045 sc_dio(sc, cs); 1046 break; 1047 1048 case STAT_IN: 1049 sc_sin(sc, cs); 1050 break; 1051 1052 default: 1053 printf("SCSI%d: unknown phase\n", cs->chan_num); 1054 break; 1055 } 1056 } 1057 } 1058 } 1059 1060 1061 void 1062 flush_fifo(sc) 1063 struct sc_softc *sc; 1064 { 1065 register VOLATILE int dummy; 1066 VOLATILE int tmp; 1067 VOLATILE int tmp0; 1068 1069 dummy = sc_ffstr; 1070 DMAC_WAIT0; 1071 if (dummy & R5_FIFOREM) { 1072 /* 1073 * flush FIFO 1074 */ 1075 SET_CMD(sc, SCMD_FLSH_FIFO); 1076 tmp = 0; 1077 do { 1078 do { 1079 dummy = sc_statr; 1080 DMAC_WAIT0; 1081 } while (dummy & R0_CIP); 1082 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1083 } while ((tmp & R3_FNC) == 0); 1084 } 1085 } 1086 1087 /* 1088 * SCSI command send routine 1089 */ 1090 void 1091 sc_cout(sc, cs) 1092 struct sc_softc *sc; 1093 register struct sc_chan_stat *cs; 1094 { 1095 register int iloop; 1096 register int cdb_bytes; 1097 register VOLATILE int dummy; 1098 register VOLATILE int statr; 1099 struct scsipi_xfer *xs; 1100 1101 if (cs->comflg == CF_SET) { 1102 struct sc_scb *scb = cs->scb; 1103 1104 cs->comflg = CF_SEND; 1105 1106 flush_fifo(sc); 1107 1108 xs = scb->xs; 1109 cdb_bytes = xs->cmdlen; 1110 1111 switch (xs->cmd->opcode & CMD_TYPEMASK) { 1112 case CMD_T0: 1113 case CMD_T1: 1114 case CMD_T5: 1115 break; 1116 1117 default: 1118 cdb_bytes = 6; 1119 sc_intok2 |= Rb_FNC; 1120 break; 1121 } 1122 1123 /* 1124 * set Active pointers 1125 */ 1126 sc->act_cmd_pointer = (char *)xs->cmd; 1127 cs->act_trcnt = scb->sc_ctrnscnt; 1128 cs->act_point = scb->sc_cpoint; 1129 cs->act_tag = scb->sc_ctag; 1130 cs->act_offset = scb->sc_coffset; 1131 1132 } else { 1133 cdb_bytes = 1; 1134 iloop = 0; 1135 do { 1136 dummy = sc_cmonr; 1137 DMAC_WAIT0; 1138 if ((dummy & SC_PMASK) != COM_OUT) 1139 return; 1140 statr = sc_statr; 1141 DMAC_WAIT0; 1142 if (statr & R0_MIRQ) 1143 return; 1144 } while ((dummy & R4_MREQ) == 0); 1145 statr = sc_statr; 1146 DMAC_WAIT0; 1147 if (statr & R0_MIRQ) 1148 return; 1149 } 1150 1151 1152 SET_CNT(cdb_bytes); 1153 SET_CMD(sc, SCMD_TR_INFO|R0_TRBE); 1154 1155 for (iloop = 0; iloop < cdb_bytes; iloop++) { 1156 do { 1157 dummy = sc_cmonr; 1158 DMAC_WAIT0; 1159 if ((dummy & SC_PMASK) != COM_OUT) 1160 return; 1161 } while ((dummy & R4_MREQ) == 0); 1162 statr = sc_statr; 1163 DMAC_WAIT0; 1164 if (statr & R0_MIRQ) 1165 return; 1166 sc_datr = *sc->act_cmd_pointer++; 1167 do { 1168 dummy = sc_cmonr; 1169 DMAC_WAIT0; 1170 } while ((dummy & R4_MACK) != 0); 1171 } 1172 } 1173 1174 #define GET_MIN_COUNT 127 1175 1176 /* 1177 * SCSI message accept routine 1178 */ 1179 void 1180 sc_min(sc, cs) 1181 struct sc_softc *sc; 1182 register struct sc_chan_stat *cs; 1183 { 1184 struct sc_scb *scb = cs->scb; 1185 struct scsipi_xfer *xs = scb->xs; 1186 register VOLATILE int dummy; 1187 1188 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE|Rb_RMSG; 1189 DMAC_WAIT0; 1190 1191 if (sc->min_flag == 1) 1192 flush_fifo(sc); 1193 1194 dummy = sc_cmonr; 1195 DMAC_WAIT0; 1196 if ((dummy & R4_MREQ) == 0) { 1197 printf("sc_min: !REQ cmonr=%x\n", dummy); 1198 print_scsi_stat(sc); 1199 scsi_hardreset(); 1200 return; 1201 } 1202 1203 /* retry_cmd_issue: */ 1204 sc->int_stat2 &= ~R3_FNC; 1205 SET_CMD(sc, SCMD_TR_INFO); 1206 do { 1207 do { 1208 dummy = sc_statr; 1209 DMAC_WAIT0; 1210 } while (dummy & R0_CIP); 1211 GET_INTR(&sc->int_stat1, &sc->int_stat2); /* clear interrupt */ 1212 } while ((sc->int_stat2 & R3_FNC) == 0); 1213 sc->int_stat2 &= ~R3_FNC; 1214 1215 dummy = sc_ffstr; 1216 if (dummy & R5_FIE) { 1217 DMAC_WAIT; 1218 dummy = sc_ffstr; 1219 DMAC_WAIT0; 1220 if (dummy & R5_FIE) { 1221 dummy = sc_statr; 1222 DMAC_WAIT0; 1223 if ((dummy & R0_INIT) == 0) { 1224 /* 1225 * CXD1185 detect BSY false 1226 */ 1227 scsi_hardreset(); 1228 return; 1229 } 1230 } 1231 } 1232 dummy = sc_datr; /* get message byte */ 1233 DMAC_WAIT0; 1234 1235 if (sc->min_cnt[cs->chan_num] == 0) { 1236 scb->message = scb->identify; 1237 if (dummy == MSG_EXTND) { 1238 /* Extended Message */ 1239 sc->min_cnt[cs->chan_num] = GET_MIN_COUNT; 1240 sc->min_point[cs->chan_num] = scb->msgbuf; 1241 bzero(scb->msgbuf, 8); 1242 *sc->min_point[cs->chan_num]++ = dummy; 1243 } else { 1244 switch ((dummy & MSG_IDENT)? MSG_IDENT : dummy) { 1245 1246 case MSG_CCOMP: 1247 scb->istatus |= INST_EP; 1248 break; 1249 1250 case MSG_MREJ: 1251 #ifndef NOT_SUPPORT_SYNCTR 1252 if (sc->mout_flag[cs->chan_num] == MOUT_SYNC_TR) 1253 sc->sync_tr[cs->chan_num] = 0; 1254 #endif 1255 break; 1256 1257 case MSG_IDENT: 1258 case MSG_RDP: 1259 1260 sc->dma_stat = OFF; 1261 sc->pad_start = 0; 1262 cs->comflg = OFF; 1263 /* 1264 * restore the saved value to Active pointers 1265 */ 1266 sc->act_cmd_pointer = (char *)xs->cmd; 1267 cs->act_trcnt = scb->sc_ctrnscnt; 1268 cs->act_point = scb->sc_cpoint; 1269 cs->act_tag = scb->sc_ctag; 1270 cs->act_offset = scb->sc_coffset; 1271 break; 1272 1273 case MSG_SDP: 1274 /* 1275 * save Active pointers 1276 */ 1277 scb->sc_ctrnscnt = cs->act_trcnt; 1278 scb->sc_ctag = cs->act_tag; 1279 scb->sc_coffset = cs->act_offset; 1280 scb->sc_cpoint = cs->act_point; 1281 break; 1282 1283 case MSG_DCNT: 1284 scb->istatus |= INST_WR; 1285 sc->wrc++; 1286 break; 1287 1288 default: 1289 scb->message = MSG_MREJ; 1290 SET_CMD(sc, SCMD_AST_ATN); 1291 printf("SCSI%d:sc_min() Unknown mes=0x%x, \n", 1292 cs->chan_num, dummy); 1293 } 1294 } 1295 } else { 1296 *sc->min_point[cs->chan_num]++ = dummy; 1297 if (sc->min_cnt[cs->chan_num] == GET_MIN_COUNT) 1298 sc->min_cnt[cs->chan_num] = dummy; 1299 else 1300 sc->min_cnt[cs->chan_num]--; 1301 if (sc->min_cnt[cs->chan_num] <= 0) { 1302 #ifdef ABORT_SYNCTR_MES_FROM_TARGET 1303 if ((scb->msgbuf[2] == 0x01) && 1304 (sc->mout_flag[cs->chan_num] == MOUT_SYNC_TR)) { 1305 #else 1306 if (scb->msgbuf[2] == 0x01) { 1307 #endif 1308 register int i; 1309 /* 1310 * receive Synchronous transfer message reply 1311 * calculate transfer period val 1312 * tpm * 4/1000 us = 4/16 * (tpv + 1) 1313 */ 1314 #define TPM2TPV(tpm) (((tpm)*16 + 999) / 1000 - 1) 1315 #ifndef NOT_SUPPORT_SYNCTR 1316 i = scb->msgbuf[3]; /* get tpm */ 1317 i = TPM2TPV(i) << 4; 1318 if (scb->msgbuf[4] == 0) 1319 sc->sync_tr[cs->chan_num] = 0; 1320 else 1321 sc->sync_tr[cs->chan_num] = 1322 i | scb->msgbuf[4]; 1323 #endif /* !NOT_SUPPORT_SYNCTR */ 1324 } else { 1325 scb->message = MSG_MREJ; 1326 SET_CMD(sc, SCMD_AST_ATN); /* assert ATN */ 1327 } 1328 } 1329 } 1330 SET_CMD(sc, SCMD_NGT_ACK); 1331 } 1332 1333 /* 1334 * SCSI message send routine 1335 */ 1336 void 1337 sc_mout(sc, cs) 1338 struct sc_softc *sc; 1339 register struct sc_chan_stat *cs; 1340 { 1341 register struct sc_scb *scb = cs->scb; 1342 register u_char *mp; 1343 register int cnt; 1344 register int iloop; 1345 register VOLATILE int dummy; 1346 VOLATILE int tmp; 1347 VOLATILE int tmp0; 1348 1349 flush_fifo(sc); 1350 1351 if (sc->mout_flag[cs->chan_num] == 0) { 1352 sc->mout_flag[cs->chan_num] = MOUT_IDENTIFY; 1353 if (scb->message != 0) { 1354 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE|Rb_RMSG; 1355 DMAC_WAIT0; 1356 if ((scb->message == MSG_EXTND) 1357 && (scb->msgbuf[2] == 0x01)) { 1358 cnt = 5; 1359 mp = scb->msgbuf; 1360 scb->msgbuf[3] = MIN_TP; 1361 if (scb->msgbuf[4] > MAX_OFFSET_BYTES) 1362 scb->msgbuf[4] = MAX_OFFSET_BYTES; 1363 sc->mout_flag[cs->chan_num] = MOUT_SYNC_TR; 1364 } else { 1365 cnt = 1; 1366 mp = &scb->message; 1367 } 1368 1369 SET_CNT(cnt); 1370 SET_CMD(sc, SCMD_TR_INFO|R0_TRBE); 1371 sc_datr = scb->identify; 1372 DMAC_WAIT0; 1373 for (iloop = 1; iloop < cnt; iloop++) { 1374 sc_datr = *mp++; 1375 DMAC_WAIT; 1376 } 1377 do { 1378 dummy = sc_cmonr; 1379 DMAC_WAIT0; 1380 if ((dummy & R4_MBSY) == 0) 1381 return; 1382 dummy = sc_statr; 1383 DMAC_WAIT0; 1384 } while (dummy & R0_CIP); 1385 1386 tmp = 0; 1387 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1388 if ((tmp & R3_FNC) == 0) { 1389 (void) WAIT_STATR_BITSET(R0_MIRQ); 1390 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1391 } 1392 1393 do { 1394 dummy = sc_cmonr; 1395 DMAC_WAIT0; 1396 if ((dummy & R4_MBSY) == 0) 1397 return; 1398 } while ((dummy & R4_MREQ) == 0); 1399 SET_CMD(sc, SCMD_NGT_ATN); 1400 (void) WAIT_STATR_BITCLR(R0_CIP); 1401 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1402 1403 dummy = sc_cmonr; 1404 DMAC_WAIT0; 1405 if ((dummy & R4_MREQ) == 0) { 1406 printf("sc_mout: !REQ cmonr=%x\n", dummy); 1407 print_scsi_stat(sc); 1408 scsi_hardreset(); 1409 return; 1410 } 1411 1412 SET_CMD(sc, SCMD_TR_INFO); 1413 sc_datr = *mp++; 1414 DMAC_WAIT0; 1415 } else { 1416 dummy = sc_cmonr; 1417 DMAC_WAIT0; 1418 if (dummy & R4_MATN) { 1419 SET_CMD(sc, SCMD_NGT_ATN); 1420 (void) WAIT_STATR_BITCLR(R0_CIP); 1421 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1422 } 1423 1424 iloop = 0; 1425 do { 1426 dummy = sc_cmonr; 1427 DMAC_WAIT0; 1428 if (iloop++ > CHECK_LOOP_CNT) 1429 break; 1430 } while ((dummy & R4_MREQ) == 0); 1431 SET_CMD(sc, SCMD_TR_INFO); 1432 sc_datr = scb->identify; 1433 DMAC_WAIT0; 1434 } 1435 } else { 1436 dummy = sc_cmonr; 1437 DMAC_WAIT0; 1438 if (dummy & R4_MATN) { 1439 SET_CMD(sc, SCMD_NGT_ATN); 1440 (void) WAIT_STATR_BITCLR(R0_CIP); 1441 GET_INTR(&tmp0, &tmp); /* clear interrupt */ 1442 } 1443 1444 dummy = sc_cmonr; 1445 DMAC_WAIT0; 1446 if ((dummy & R4_MREQ) == 0) { 1447 printf("sc_mout: !REQ cmonr=%x\n", dummy); 1448 print_scsi_stat(sc); 1449 scsi_hardreset(); 1450 return; 1451 } 1452 1453 SET_CMD(sc, SCMD_TR_INFO); 1454 sc_datr = scb->message; 1455 DMAC_WAIT0; 1456 } 1457 } 1458 1459 /* 1460 * SCSI status accept routine 1461 */ 1462 void 1463 sc_sin(sc, cs) 1464 struct sc_softc *sc; 1465 register VOLATILE struct sc_chan_stat *cs; 1466 { 1467 register VOLATILE int dummy; 1468 register int iloop; 1469 1470 flush_fifo(sc); 1471 1472 dummy = sc_cmonr; 1473 DMAC_WAIT0; 1474 if ((dummy & R4_MREQ) == 0) { 1475 printf("sc_sin: !REQ cmonr=%x\n", dummy); 1476 print_scsi_stat(sc); 1477 scsi_hardreset(); 1478 return; 1479 } 1480 1481 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE|Rb_RMSG; 1482 DMAC_WAIT0; 1483 1484 SET_CMD(sc, SCMD_TR_INFO); 1485 1486 (void) WAIT_STATR_BITCLR(R0_CIP); 1487 1488 sc->int_stat2 &= ~R3_FNC; 1489 iloop = 0; 1490 do { 1491 if (iloop++ > CHECK_LOOP_CNT) 1492 break; 1493 GET_INTR(&sc->int_stat1, &sc->int_stat2); /* clear interrupt */ 1494 } while ((sc->int_stat2 & R3_FNC) == 0); 1495 sc->int_stat2 &= ~R3_FNC; 1496 1497 cs->scb->tstatus = sc_datr; /* get status byte */ 1498 DMAC_WAIT0; 1499 } 1500 1501 /* 1502 * SCSI data in/out routine 1503 */ 1504 void 1505 sc_dio(sc, cs) 1506 struct sc_softc *sc; 1507 register VOLATILE struct sc_chan_stat *cs; 1508 { 1509 register VOLATILE struct sc_scb *scb; 1510 register int i; 1511 register int pages; 1512 register u_int tag; 1513 register u_int pfn; 1514 VOLATILE int phase; 1515 struct scsipi_xfer *xs; 1516 1517 scb = cs->scb; 1518 xs = scb->xs; 1519 1520 sc_intok2 = Rb_FNC|Rb_DCNT|Rb_SRST|Rb_PHC|Rb_SPE; 1521 DMAC_WAIT0; 1522 1523 if (cs->act_trcnt <= 0) { 1524 sc_dio_pad(sc, cs); 1525 return; 1526 } 1527 1528 switch (xs->cmd->opcode) { 1529 1530 case SCOP_READ: 1531 case SCOP_WRITE: 1532 case SCOP_EREAD: 1533 case SCOP_EWRITE: 1534 i = (cs->act_trcnt + DEV_BSIZE -1) / DEV_BSIZE; 1535 i *= DEV_BSIZE; 1536 break; 1537 1538 default: 1539 i = cs->act_trcnt; 1540 break; 1541 } 1542 1543 SET_CNT(i); 1544 sc->pad_cnt[cs->chan_num] = i - cs->act_trcnt; 1545 1546 phase = sc_cmonr & SC_PMASK; 1547 DMAC_WAIT0; 1548 if (phase == DAT_IN) { 1549 if (sc_syncr == OFF) { 1550 DMAC_WAIT0; 1551 flush_fifo(sc); 1552 } 1553 } 1554 1555 #if defined(mips) && defined(CPU_SINGLE) 1556 SET_CMD(sc, SCMD_TR_INFO|R0_DMA|R0_TRBE); 1557 #endif 1558 1559 #if defined(mips) && defined(CPU_SINGLE) 1560 dmac_gsel = CH_SCSI; 1561 dmac_ctrcl = (u_char)(cs->act_trcnt & 0xff); 1562 dmac_ctrcm = (u_char)((cs->act_trcnt >> 8) & 0xff); 1563 dmac_ctrch = (u_char)((cs->act_trcnt >> 16) & 0x0f); 1564 dmac_cofsh = (u_char)((cs->act_offset >> 8) & 0xf); 1565 dmac_cofsl = (u_char)(cs->act_offset & 0xff); 1566 #endif 1567 tag = 0; 1568 1569 if (scb->sc_map && (scb->sc_map->mp_pages > 0)) { 1570 /* 1571 * Set DMAC map entry from map table 1572 */ 1573 pages = scb->sc_map->mp_pages; 1574 for (i = cs->act_tag; i < pages; i++) { 1575 if ((pfn = scb->sc_map->mp_addr[i]) == 0) 1576 panic("SCSI:sc_dma() zero entry"); 1577 #if defined(mips) && defined(CPU_SINGLE) 1578 dmac_gsel = CH_SCSI; 1579 dmac_ctag = (u_char)tag++; 1580 dmac_cmap = (u_short)pfn; 1581 #endif 1582 } 1583 #ifdef MAP_OVER_ACCESS 1584 # if defined(mips) && defined(CPU_SINGLE) 1585 dmac_gsel = CH_SCSI; 1586 dmac_ctag = (u_char)tag++; 1587 dmac_cmap = (u_short)pfn; 1588 # endif 1589 #endif 1590 } else { 1591 /* 1592 * Set DMAC map entry from logical address 1593 */ 1594 pfn = kvtophys((vaddr_t)cs->act_point) >> PGSHIFT; 1595 pages = (cs->act_trcnt >> PGSHIFT) + 2; 1596 for (i = 0; i < pages; i++) { 1597 #if defined(mips) && defined(CPU_SINGLE) 1598 dmac_gsel = CH_SCSI; 1599 dmac_ctag = (u_char)tag++; 1600 dmac_cmap = (u_short)pfn + i; 1601 #endif 1602 } 1603 } 1604 1605 #if defined(mips) && defined(CPU_SINGLE) 1606 dmac_gsel = CH_SCSI; 1607 dmac_ctag = 0; 1608 #endif 1609 1610 if (phase == DAT_IN) { 1611 sc->dma_stat = SC_DMAC_RD; 1612 #if defined(mips) && defined(CPU_SINGLE) 1613 /* 1614 * auto pad flag is always on 1615 */ 1616 dmac_gsel = CH_SCSI; 1617 dmac_cctl = DM_MODE|DM_APAD; 1618 DMAC_WAIT; 1619 dmac_cctl = DM_MODE|DM_APAD|DM_ENABLE; 1620 DMAC_WAIT0; 1621 #endif 1622 } 1623 else if (phase == DAT_OUT) { 1624 sc->dma_stat = SC_DMAC_WR; 1625 #if defined(mips) && defined(CPU_SINGLE) 1626 dmac_gsel = CH_SCSI; 1627 dmac_cctl = DM_APAD; 1628 DMAC_WAIT; 1629 dmac_cctl = DM_APAD|DM_ENABLE; 1630 DMAC_WAIT0; 1631 #endif 1632 /* DMAC start on mem->I/O */ 1633 } 1634 } 1635 1636 #define MAX_TR_CNT24 ((1 << 24) -1) 1637 void 1638 sc_dio_pad(sc, cs) 1639 struct sc_softc *sc; 1640 register VOLATILE struct sc_chan_stat *cs; 1641 { 1642 register int dummy; 1643 1644 if (cs->act_trcnt >= 0) 1645 return; 1646 sc->pad_start = 1; 1647 1648 SET_CNT(MAX_TR_CNT24); 1649 SET_CMD(sc, SCMD_TR_PAD|R0_TRBE); 1650 dummy = sc_cmonr & SC_PMASK; 1651 DMAC_WAIT0; 1652 if (dummy == DAT_IN) 1653 dummy = sc_datr; /* get data */ 1654 else 1655 sc_datr = 0; /* send data */ 1656 } 1657 1658 void 1659 print_scsi_stat(sc) 1660 struct sc_softc *sc; 1661 { 1662 printf("ipc=%d wrc=%d wbc=%d\n", sc->ipc, sc->wrc, sc->wbc); 1663 } 1664 1665 /* 1666 * return 0 if it was done. Or retun TRUE if it is busy. 1667 */ 1668 int 1669 sc_busy(sc, chan) 1670 struct sc_softc *sc; 1671 register int chan; 1672 { 1673 return ((int)sc->chan_stat[chan].scb); 1674 } 1675 1676 1677 /* 1678 * append channel into Waiting Bus_free queue 1679 */ 1680 void 1681 append_wb(sc, cs) 1682 struct sc_softc *sc; 1683 struct sc_chan_stat *cs; 1684 { 1685 int s; 1686 1687 s = splclock(); /* inhibit process switch */ 1688 if (sc->wbq_actf == NULL) 1689 sc->wbq_actf = cs; 1690 else 1691 sc->wbq_actl->wb_next = cs; 1692 sc->wbq_actl = cs; 1693 cs->scb->istatus = INST_WAIT; 1694 sc->wbc++; 1695 splx(s); 1696 } 1697 1698 /* 1699 * get channel from Waiting Bus_free queue 1700 */ 1701 struct sc_chan_stat * 1702 get_wb_chan(sc) 1703 struct sc_softc *sc; 1704 { 1705 struct sc_chan_stat *cs; 1706 int s; 1707 1708 s = splclock(); /* inhibit process switch */ 1709 cs = sc->wbq_actf; 1710 if (cs && cs->chan_num == SC_OWNID) /* needed? */ 1711 cs = NULL; 1712 splx(s); 1713 return cs; 1714 } 1715 1716 /* 1717 * release channel from Waiting Bus_free queue 1718 */ 1719 int 1720 release_wb(sc) 1721 struct sc_softc *sc; 1722 { 1723 struct sc_chan_stat *cs; 1724 int error = 0; 1725 int s; 1726 1727 s = splclock(); /* inhibit process switch */ 1728 if (sc->wbq_actf == NULL) { 1729 error = -1; 1730 } else { 1731 cs = sc->wbq_actf; 1732 sc->wbq_actf = cs->wb_next; 1733 cs->wb_next = NULL; 1734 if (sc->wbq_actl == cs) 1735 sc->wbq_actl = NULL; 1736 cs->scb->istatus &= ~INST_WAIT; 1737 sc->wbc--; 1738 } 1739 splx(s); 1740 return error; 1741 } 1742 1743 void 1744 adjust_transfer(sc, cs) 1745 struct sc_softc *sc; 1746 struct sc_chan_stat *cs; 1747 { 1748 struct sc_scb *scb = cs->scb; 1749 u_int remain_cnt; 1750 u_int offset, sent_byte; 1751 1752 if (sc->pad_start) { 1753 sc->pad_start = 0; 1754 remain_cnt = 0; 1755 } else { 1756 # if defined(mips) && defined(CPU_SINGLE) 1757 remain_cnt = GET_CNT(); 1758 remain_cnt -= sc->pad_cnt[cs->chan_num]; 1759 if (sc->dma_stat == SC_DMAC_WR) { 1760 /* 1761 * adjust counter in the FIFO 1762 */ 1763 remain_cnt += sc_ffstr & R5_FIFOREM; 1764 } 1765 # endif 1766 } 1767 1768 sent_byte = scb->sc_ctrnscnt - remain_cnt; 1769 cs->act_trcnt = remain_cnt; 1770 1771 offset = scb->sc_coffset + sent_byte; 1772 cs->act_tag += (offset >> PGSHIFT); 1773 cs->act_offset = offset & PGOFSET; 1774 if ((scb->sc_map == NULL) || (scb->sc_map->mp_pages <= 0)) 1775 cs->act_point += sent_byte; 1776 } 1777 1778 #ifdef mips 1779 static void 1780 clean_k2dcache(scb) 1781 struct sc_scb *scb; 1782 { 1783 struct sc_map *sc_map = scb->sc_map; 1784 paddr_t pa; 1785 int i, pages; 1786 1787 pa = kvtophys((vaddr_t)scb->msgbuf); 1788 mips_dcache_wbinv_range_index(MIPS_PHYS_TO_KSEG0(pa), 1789 sizeof(scb->msgbuf)); 1790 1791 if (MACH_IS_USPACE(scb->sc_cpoint)) 1792 panic("clean_k2dcache: user address is not supported"); 1793 1794 if (MACH_IS_CACHED(scb->sc_cpoint)) { 1795 mips_dcache_wbinv_range_index((vaddr_t)scb->sc_cpoint, 1796 scb->sc_ctrnscnt); 1797 return; 1798 } 1799 1800 if (sc_map) { 1801 pages = sc_map->mp_pages; 1802 for (i = 0; i < pages; i++) { 1803 pa = sc_map->mp_addr[i] << PGSHIFT; 1804 mips_dcache_wbinv_range_index(MIPS_PHYS_TO_KSEG0(pa), 1805 NBPG); 1806 } 1807 } 1808 } 1809 #endif 1810
Indexes created Sun Sep 28 16:09:52 GMT 2025