zs.c revision 1.1
1 /* $NetBSD: zs.c,v 1.1 1998/02/18 13:48:14 tsubai Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/conf.h> 50 #include <sys/device.h> 51 #include <sys/file.h> 52 #include <sys/ioctl.h> 53 #include <sys/kernel.h> 54 #include <sys/proc.h> 55 #include <sys/tty.h> 56 #include <sys/time.h> 57 #include <sys/syslog.h> 58 59 #include <machine/autoconf.h> 60 #include <machine/cpu.h> 61 #include <machine/adrsmap.h> 62 #include <machine/z8530var.h> 63 64 #include <dev/cons.h> 65 #include <dev/ic/z8530reg.h> 66 67 #include "zsc.h" /* NZSC */ 68 #define NZS NZSC 69 70 /* Make life easier for the initialized arrays here. */ 71 #if NZS < 2 72 #undef NZS 73 #define NZS 2 74 #endif 75 76 extern void Debugger __P((void)); 77 78 /* 79 * Some warts needed by z8530tty.c - 80 * The default parity REALLY needs to be the same as the PROM uses, 81 * or you can not see messages done with printf during boot-up... 82 */ 83 int zs_def_cflag = (CREAD | CS8 | HUPCL); 84 int zs_major = 1; 85 86 /* 87 * The news3400 provides a 4.9152 MHz clock to the ZS chips. 88 */ 89 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ 90 91 /* 92 * Define interrupt levels. 93 */ 94 #define ZSHARD_PRI 64 95 96 #define ZS_DELAY() delay(2) 97 98 /* The layout of this is hardware-dependent (padding, order). */ 99 struct zschan { 100 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 101 volatile u_char zc_data; /* data */ 102 }; 103 struct zsdevice { 104 /* Yes, they are backwards. */ 105 struct zschan zs_chan_b; 106 struct zschan zs_chan_a; 107 }; 108 109 110 /* Saved PROM mappings */ 111 static struct zsdevice *zsaddr[NZS] = { 112 (void *)SCCPORT0B, 113 (void *)SCCPORT1B, 114 }; 115 116 /* Flags from cninit() */ 117 static int zs_hwflags[NZS][2]; 118 119 /* Default speed for each channel */ 120 static int zs_defspeed[NZS][2] = { 121 { 9600, /* tty00 */ 122 9600 }, /* tty01 */ 123 { 9600, /* tty10 */ 124 9600 }, /* tty11 */ 125 }; 126 127 static u_char zs_init_reg[16] = { 128 0, /* 0: CMD (reset, etc.) */ 129 0, /* 1: No interrupts yet. */ 130 ZSHARD_PRI, /* IVECT */ 131 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 132 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 133 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 134 0, /* 6: TXSYNC/SYNCLO */ 135 0, /* 7: RXSYNC/SYNCHI */ 136 0, /* 8: alias for data port */ 137 ZSWR9_MASTER_IE, 138 0, /*10: Misc. TX/RX control bits */ 139 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 140 14, /*12: BAUDLO (default=9600) */ 141 0, /*13: BAUDHI (default=9600) */ 142 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 143 ZSWR15_BREAK_IE | ZSWR15_DCD_IE, 144 }; 145 146 147 struct zschan * 148 zs_get_chan_addr(zs_unit, channel) 149 int zs_unit, channel; 150 { 151 struct zsdevice *addr; 152 struct zschan *zc; 153 154 if (zs_unit >= NZS) 155 return NULL; 156 addr = zsaddr[zs_unit]; 157 if (addr == NULL) 158 return NULL; 159 if (channel == 0) { 160 zc = &addr->zs_chan_a; 161 } else { 162 zc = &addr->zs_chan_b; 163 } 164 return (zc); 165 } 166 167 168 /**************************************************************** 169 * Autoconfig 170 ****************************************************************/ 171 172 /* Definition of the driver for autoconfig. */ 173 static int zs_match __P((struct device *, struct cfdata *, void *)); 174 static void zs_attach __P((struct device *, struct device *, void *)); 175 static int zs_print __P((void *, const char *name)); 176 177 struct cfattach zsc_ca = { 178 sizeof(struct zsc_softc), zs_match, zs_attach 179 }; 180 181 extern struct cfdriver zsc_cd; 182 183 static void zshard __P((void *)); 184 static void zssoft __P((void *)); 185 static int zs_get_speed __P((struct zs_chanstate *)); 186 187 188 /* 189 * Is the zs chip present? 190 */ 191 static int 192 zs_match(parent, cf, aux) 193 struct device *parent; 194 struct cfdata *cf; 195 void *aux; 196 { 197 struct confargs *ca = aux; 198 int unit = cf->cf_unit; 199 void *va; 200 201 if (strcmp(ca->ca_name, "zsc")) 202 return 0; 203 204 /* Make sure zs_init() found mappings. */ 205 va = zsaddr[unit]; 206 if (va == NULL) 207 return 0; 208 209 /* This returns -1 on a fault (bus error). */ 210 if (badaddr(va, 1)) 211 return 0; 212 213 return 1; 214 } 215 216 /* 217 * Attach a found zs. 218 * 219 * Match slave number to zs unit number, so that misconfiguration will 220 * not set up the keyboard as ttya, etc. 221 */ 222 static void 223 zs_attach(parent, self, aux) 224 struct device *parent; 225 struct device *self; 226 void *aux; 227 { 228 struct zsc_softc *zsc = (void *) self; 229 /* struct confargs *ca = aux; */ 230 struct zsc_attach_args zsc_args; 231 volatile struct zschan *zc; 232 struct zs_chanstate *cs; 233 int s, zs_unit, channel; 234 static int didintr; 235 236 zs_unit = zsc->zsc_dev.dv_unit; 237 238 printf("\n"); 239 240 /* 241 * Initialize software state for each channel. 242 */ 243 for (channel = 0; channel < 2; channel++) { 244 zsc_args.channel = channel; 245 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 246 cs = &zsc->zsc_cs_store[channel]; 247 zsc->zsc_cs[channel] = cs; 248 249 cs->cs_channel = channel; 250 cs->cs_private = NULL; 251 cs->cs_ops = &zsops_null; 252 cs->cs_brg_clk = PCLK / 16; 253 254 zc = zs_get_chan_addr(zs_unit, channel); 255 cs->cs_reg_csr = &zc->zc_csr; 256 cs->cs_reg_data = &zc->zc_data; 257 258 bcopy(zs_init_reg, cs->cs_creg, 16); 259 bcopy(zs_init_reg, cs->cs_preg, 16); 260 261 /* XXX: Get these from the EEPROM instead? */ 262 /* XXX: See the mvme167 code. Better. */ 263 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 264 cs->cs_defspeed = zs_get_speed(cs); 265 else 266 cs->cs_defspeed = zs_defspeed[zs_unit][channel]; 267 cs->cs_defcflag = zs_def_cflag; 268 269 /* Make these correspond to cs_defcflag (-crtscts) */ 270 cs->cs_rr0_dcd = ZSRR0_DCD; 271 cs->cs_rr0_cts = 0; 272 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 273 cs->cs_wr5_rts = 0; 274 275 /* 276 * Clear the master interrupt enable. 277 * The INTENA is common to both channels, 278 * so just do it on the A channel. 279 */ 280 if (channel == 0) { 281 zs_write_reg(cs, 9, 0); 282 } 283 284 /* 285 * Look for a child driver for this channel. 286 * The child attach will setup the hardware. 287 */ 288 if (!config_found(self, (void *)&zsc_args, zs_print)) { 289 /* No sub-driver. Just reset it. */ 290 u_char reset = (channel == 0) ? 291 ZSWR9_A_RESET : ZSWR9_B_RESET; 292 s = splhigh(); 293 zs_write_reg(cs, 9, reset); 294 splx(s); 295 } 296 } 297 298 /* 299 * Now safe to install interrupt handlers. Note the arguments 300 * to the interrupt handlers aren't used. Note, we only do this 301 * once since both SCCs interrupt at the same level and vector. 302 */ 303 if (!didintr) { 304 didintr = 1; 305 #if 0 306 isr_add_autovect(zssoft, NULL, ZSSOFT_PRI); 307 isr_add_autovect(zshard, NULL, ca->ca_intpri); 308 #endif 309 } 310 /* XXX; evcnt_attach() ? */ 311 312 /* 313 * Set the master interrupt enable and interrupt vector. 314 * (common to both channels, do it on A) 315 */ 316 cs = zsc->zsc_cs[0]; 317 s = splhigh(); 318 /* interrupt vector */ 319 zs_write_reg(cs, 2, zs_init_reg[2]); 320 /* master interrupt control (enable) */ 321 zs_write_reg(cs, 9, zs_init_reg[9]); 322 splx(s); 323 } 324 325 static int 326 zs_print(aux, name) 327 void *aux; 328 const char *name; 329 { 330 struct zsc_attach_args *args = aux; 331 332 if (name != NULL) 333 printf("%s: ", name); 334 335 if (args->channel != -1) 336 printf(" channel %d", args->channel); 337 338 return UNCONF; 339 } 340 341 static volatile int zssoftpending; 342 343 /* 344 * Our ZS chips all share a common, autovectored interrupt, 345 * so we have to look at all of them on each interrupt. 346 */ 347 static void 348 zshard(arg) 349 void *arg; 350 { 351 register struct zsc_softc *zsc; 352 register int unit, rval, softreq; 353 354 rval = softreq = 0; 355 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 356 zsc = zsc_cd.cd_devs[unit]; 357 if (zsc == NULL) 358 continue; 359 rval |= zsc_intr_hard(zsc); 360 softreq |= zsc->zsc_cs[0]->cs_softreq; 361 softreq |= zsc->zsc_cs[1]->cs_softreq; 362 } 363 364 /* We are at splzs here, so no need to lock. */ 365 if (softreq && (zssoftpending == 0)) { 366 zssoftpending = 1; 367 timeout(zssoft, arg, 1); /*isr_soft_request(ZSSOFT_PRI);*/ 368 } 369 return; 370 } 371 372 /* 373 * Similar scheme as for zshard (look at all of them) 374 */ 375 static void 376 zssoft(arg) 377 void *arg; 378 { 379 register struct zsc_softc *zsc; 380 register int s, unit; 381 382 /* This is not the only ISR on this IPL. */ 383 if (zssoftpending == 0) 384 return; 385 386 /* 387 * The soft intr. bit will be set by zshard only if 388 * the variable zssoftpending is zero. The order of 389 * these next two statements prevents our clearing 390 * the soft intr bit just after zshard has set it. 391 */ 392 /*isr_soft_clear(ZSSOFT_PRI);*/ 393 /*zssoftpending = 0;*/ 394 395 /* Make sure we call the tty layer at spltty. */ 396 s = spltty(); 397 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 398 zsc = zsc_cd.cd_devs[unit]; 399 if (zsc == NULL) 400 continue; 401 (void) zsc_intr_soft(zsc); 402 } 403 splx(s); 404 zssoftpending = 0; 405 return; 406 } 407 408 409 /* 410 * Compute the current baud rate given a ZS channel. 411 */ 412 static int 413 zs_get_speed(cs) 414 struct zs_chanstate *cs; 415 { 416 int tconst; 417 418 tconst = zs_read_reg(cs, 12); 419 tconst |= zs_read_reg(cs, 13) << 8; 420 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 421 } 422 423 /* 424 * MD functions for setting the baud rate and control modes. 425 */ 426 int 427 zs_set_speed(cs, bps) 428 struct zs_chanstate *cs; 429 int bps; /* bits per second */ 430 { 431 int tconst, real_bps; 432 433 if (bps == 0) 434 return (0); 435 436 #ifdef DIAGNOSTIC 437 if (cs->cs_brg_clk == 0) 438 panic("zs_set_speed"); 439 #endif 440 441 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 442 if (tconst < 0) 443 return (EINVAL); 444 445 /* Convert back to make sure we can do it. */ 446 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 447 448 /* XXX - Allow some tolerance here? */ 449 if (real_bps != bps) 450 return (EINVAL); 451 452 cs->cs_preg[12] = tconst; 453 cs->cs_preg[13] = tconst >> 8; 454 455 /* Caller will stuff the pending registers. */ 456 return (0); 457 } 458 459 int 460 zs_set_modes(cs, cflag) 461 struct zs_chanstate *cs; 462 int cflag; /* bits per second */ 463 { 464 int s; 465 466 /* 467 * Output hardware flow control on the chip is horrendous: 468 * if carrier detect drops, the receiver is disabled, and if 469 * CTS drops, the transmitter is stoped IN MID CHARACTER! 470 * Therefore, NEVER set the HFC bit, and instead use the 471 * status interrupt to detect CTS changes. 472 */ 473 s = splzs(); 474 if ((cflag & (CLOCAL | MDMBUF)) != 0) 475 cs->cs_rr0_dcd = 0; 476 else 477 cs->cs_rr0_dcd = ZSRR0_DCD; 478 if ((cflag & CRTSCTS) != 0) { 479 cs->cs_wr5_dtr = ZSWR5_DTR; 480 cs->cs_wr5_rts = ZSWR5_RTS; 481 cs->cs_rr0_cts = ZSRR0_CTS; 482 } else if ((cflag & MDMBUF) != 0) { 483 cs->cs_wr5_dtr = 0; 484 cs->cs_wr5_rts = ZSWR5_DTR; 485 cs->cs_rr0_cts = ZSRR0_DCD; 486 } else { 487 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 488 cs->cs_wr5_rts = 0; 489 cs->cs_rr0_cts = 0; 490 } 491 splx(s); 492 493 /* Caller will stuff the pending registers. */ 494 return (0); 495 } 496 497 498 /* 499 * Read or write the chip with suitable delays. 500 */ 501 502 u_char 503 zs_read_reg(cs, reg) 504 struct zs_chanstate *cs; 505 u_char reg; 506 { 507 u_char val; 508 509 *cs->cs_reg_csr = reg; 510 ZS_DELAY(); 511 val = *cs->cs_reg_csr; 512 ZS_DELAY(); 513 return val; 514 } 515 516 void 517 zs_write_reg(cs, reg, val) 518 struct zs_chanstate *cs; 519 u_char reg, val; 520 { 521 *cs->cs_reg_csr = reg; 522 ZS_DELAY(); 523 *cs->cs_reg_csr = val; 524 ZS_DELAY(); 525 } 526 527 u_char zs_read_csr(cs) 528 struct zs_chanstate *cs; 529 { 530 register u_char val; 531 532 val = *cs->cs_reg_csr; 533 ZS_DELAY(); 534 return val; 535 } 536 537 void zs_write_csr(cs, val) 538 struct zs_chanstate *cs; 539 u_char val; 540 { 541 *cs->cs_reg_csr = val; 542 ZS_DELAY(); 543 } 544 545 u_char zs_read_data(cs) 546 struct zs_chanstate *cs; 547 { 548 register u_char val; 549 550 val = *cs->cs_reg_data; 551 ZS_DELAY(); 552 return val; 553 } 554 555 void zs_write_data(cs, val) 556 struct zs_chanstate *cs; 557 u_char val; 558 { 559 *cs->cs_reg_data = val; 560 ZS_DELAY(); 561 } 562 563 void 564 zs_abort(cs) 565 struct zs_chanstate *cs; 566 { 567 } 568 569 /* 570 * Polled input char. 571 */ 572 int 573 zs_getc(arg) 574 void *arg; 575 { 576 register volatile struct zschan *zc = arg; 577 register int s, c, rr0; 578 579 s = splhigh(); 580 /* Wait for a character to arrive. */ 581 do { 582 rr0 = zc->zc_csr; 583 ZS_DELAY(); 584 } while ((rr0 & ZSRR0_RX_READY) == 0); 585 586 c = zc->zc_data; 587 ZS_DELAY(); 588 splx(s); 589 590 /* 591 * This is used by the kd driver to read scan codes, 592 * so don't translate '\r' ==> '\n' here... 593 */ 594 return (c); 595 } 596 597 /* 598 * Polled output char. 599 */ 600 void 601 zs_putc(arg, c) 602 void *arg; 603 int c; 604 { 605 register volatile struct zschan *zc = arg; 606 register int s, rr0; 607 608 s = splhigh(); 609 /* Wait for transmitter to become ready. */ 610 do { 611 rr0 = zc->zc_csr; 612 ZS_DELAY(); 613 } while ((rr0 & ZSRR0_TX_READY) == 0); 614 615 zc->zc_data = c; 616 ZS_DELAY(); 617 splx(s); 618 } 619 620 /*****************************************************************/ 621 622 static void zscnprobe __P((struct consdev *)); 623 static void zscninit __P((struct consdev *)); 624 static int zscngetc __P((dev_t)); 625 static void zscnputc __P((dev_t, int)); 626 static void zscnpollc __P((dev_t, int)); 627 628 struct consdev consdev_zs = { 629 zscnprobe, 630 zscninit, 631 zscngetc, 632 zscnputc, 633 zscnpollc 634 }; 635 636 void 637 zscnprobe(cn) 638 struct consdev *cn; 639 { 640 } 641 642 void 643 zscninit(cn) 644 struct consdev *cn; 645 { 646 cn->cn_dev = makedev(zs_major, 0); 647 cn->cn_pri = CN_REMOTE; 648 zs_hwflags[0][0] = ZS_HWFLAG_CONSOLE; 649 } 650 651 int 652 zscngetc(dev) 653 dev_t dev; 654 { 655 return zs_getc(SCCPORT0A); 656 } 657 658 void 659 zscnputc(dev, c) 660 dev_t dev; 661 int c; 662 { 663 zs_putc(SCCPORT0A, c); 664 } 665 666 void 667 zscnpollc(dev, on) 668 dev_t dev; 669 int on; 670 { 671 } 672 673 /* 674 * ZS vector interrupt service routine. 675 */ 676 void 677 zs_intr() 678 { 679 int vec; 680 681 vec = *(volatile u_char *)SCCVECT; 682 zshard((void *)vec); /* XXX vec is not used */ 683 } 684
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