zs.c revision 1.17
1 /* $NetBSD: zs.c,v 1.17 2003/04/26 18:43:20 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include "opt_ddb.h" 48 49 #include <sys/param.h> 50 #include <sys/device.h> 51 #include <sys/tty.h> 52 #include <sys/systm.h> 53 54 #include <machine/adrsmap.h> 55 #include <machine/cpu.h> 56 #include <machine/z8530var.h> 57 58 #include <dev/ic/z8530reg.h> 59 60 #define ZS_DELAY() (*zs_delay)() 61 62 extern struct cfdriver zsc_cd; 63 64 /* 65 * Some warts needed by z8530tty.c - 66 * The default parity REALLY needs to be the same as the PROM uses, 67 * or you can not see messages done with printf during boot-up... 68 */ 69 int zs_def_cflag = (CREAD | CS8 | HUPCL); 70 71 int 72 zs_print(aux, name) 73 void *aux; 74 const char *name; 75 { 76 struct zsc_attach_args *args = aux; 77 78 if (name != NULL) 79 aprint_normal("%s: ", name); 80 81 if (args->channel != -1) 82 aprint_normal(" channel %d", args->channel); 83 84 return UNCONF; 85 } 86 87 static volatile int zssoftpending; 88 89 /* 90 * Our ZS chips all share a common, autovectored interrupt, 91 * so we have to look at all of them on each interrupt. 92 */ 93 int 94 zshard(arg) 95 void *arg; 96 { 97 struct zsc_softc *zsc; 98 int unit, rval, softreq; 99 100 rval = softreq = 0; 101 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 102 zsc = zsc_cd.cd_devs[unit]; 103 if (zsc == NULL) 104 continue; 105 rval |= zsc_intr_hard(zsc); 106 softreq |= zsc->zsc_cs[0]->cs_softreq; 107 softreq |= zsc->zsc_cs[1]->cs_softreq; 108 } 109 110 /* We are at splzs here, so no need to lock. */ 111 if (softreq && (zssoftpending == 0)) { 112 zssoftpending = 1; 113 setsoftserial(); 114 } 115 116 return rval; 117 } 118 119 /* 120 * Similar scheme as for zshard (look at all of them) 121 */ 122 void 123 zssoft(arg) 124 void *arg; 125 { 126 struct zsc_softc *zsc; 127 int s, unit; 128 129 /* This is not the only ISR on this IPL. */ 130 if (zssoftpending == 0) 131 return; 132 133 /* 134 * The soft intr. bit will be set by zshard only if 135 * the variable zssoftpending is zero. The order of 136 * these next two statements prevents our clearing 137 * the soft intr bit just after zshard has set it. 138 */ 139 /* clearsoftnet(); */ 140 zssoftpending = 0; 141 142 /* Make sure we call the tty layer at spltty. */ 143 s = spltty(); 144 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 145 zsc = zsc_cd.cd_devs[unit]; 146 if (zsc == NULL) 147 continue; 148 (void)zsc_intr_soft(zsc); 149 } 150 splx(s); 151 } 152 153 /* 154 * Compute the current baud rate given a ZS channel. 155 */ 156 int 157 zs_get_speed(cs) 158 struct zs_chanstate *cs; 159 { 160 int tconst; 161 162 tconst = zs_read_reg(cs, 12); 163 tconst |= zs_read_reg(cs, 13) << 8; 164 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 165 } 166 167 /* 168 * MD functions for setting the baud rate and control modes. 169 */ 170 int 171 zs_set_speed(cs, bps) 172 struct zs_chanstate *cs; 173 int bps; /* bits per second */ 174 { 175 int tconst, real_bps; 176 177 if (bps == 0) 178 return (0); 179 180 #ifdef DIAGNOSTIC 181 if (cs->cs_brg_clk == 0) 182 panic("zs_set_speed"); 183 #endif 184 185 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 186 if (tconst < 0) 187 return (EINVAL); 188 189 /* Convert back to make sure we can do it. */ 190 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 191 192 /* XXX - Allow some tolerance here? */ 193 if (real_bps != bps) 194 return (EINVAL); 195 196 cs->cs_preg[12] = tconst; 197 cs->cs_preg[13] = tconst >> 8; 198 199 /* Caller will stuff the pending registers. */ 200 return (0); 201 } 202 203 int 204 zs_set_modes(cs, cflag) 205 struct zs_chanstate *cs; 206 int cflag; /* bits per second */ 207 { 208 int s; 209 210 /* 211 * Output hardware flow control on the chip is horrendous: 212 * if carrier detect drops, the receiver is disabled, and if 213 * CTS drops, the transmitter is stoped IN MID CHARACTER! 214 * Therefore, NEVER set the HFC bit, and instead use the 215 * status interrupt to detect CTS changes. 216 */ 217 s = splzs(); 218 cs->cs_rr0_pps = 0; 219 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 220 cs->cs_rr0_dcd = 0; 221 if ((cflag & MDMBUF) == 0) 222 cs->cs_rr0_pps = ZSRR0_DCD; 223 } else 224 cs->cs_rr0_dcd = ZSRR0_DCD; 225 if ((cflag & CRTSCTS) != 0) { 226 cs->cs_wr5_dtr = ZSWR5_DTR; 227 cs->cs_wr5_rts = ZSWR5_RTS; 228 cs->cs_rr0_cts = ZSRR0_CTS; 229 } else if ((cflag & MDMBUF) != 0) { 230 cs->cs_wr5_dtr = 0; 231 cs->cs_wr5_rts = ZSWR5_DTR; 232 cs->cs_rr0_cts = ZSRR0_DCD; 233 } else { 234 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 235 cs->cs_wr5_rts = 0; 236 cs->cs_rr0_cts = 0; 237 } 238 splx(s); 239 240 /* Caller will stuff the pending registers. */ 241 return (0); 242 } 243 244 /* 245 * Read or write the chip with suitable delays. 246 */ 247 248 u_char 249 zs_read_reg(cs, reg) 250 struct zs_chanstate *cs; 251 u_char reg; 252 { 253 u_char val; 254 255 *cs->cs_reg_csr = reg; 256 ZS_DELAY(); 257 val = *cs->cs_reg_csr; 258 ZS_DELAY(); 259 return val; 260 } 261 262 void 263 zs_write_reg(cs, reg, val) 264 struct zs_chanstate *cs; 265 u_char reg, val; 266 { 267 *cs->cs_reg_csr = reg; 268 ZS_DELAY(); 269 *cs->cs_reg_csr = val; 270 ZS_DELAY(); 271 } 272 273 u_char zs_read_csr(cs) 274 struct zs_chanstate *cs; 275 { 276 u_char val; 277 278 val = *cs->cs_reg_csr; 279 ZS_DELAY(); 280 return val; 281 } 282 283 void zs_write_csr(cs, val) 284 struct zs_chanstate *cs; 285 u_char val; 286 { 287 *cs->cs_reg_csr = val; 288 ZS_DELAY(); 289 } 290 291 u_char zs_read_data(cs) 292 struct zs_chanstate *cs; 293 { 294 u_char val; 295 296 val = *cs->cs_reg_data; 297 ZS_DELAY(); 298 return val; 299 } 300 301 void zs_write_data(cs, val) 302 struct zs_chanstate *cs; 303 u_char val; 304 { 305 *cs->cs_reg_data = val; 306 ZS_DELAY(); 307 } 308 309 void 310 zs_abort(cs) 311 struct zs_chanstate *cs; 312 { 313 #ifdef DDB 314 Debugger(); 315 #endif 316 } 317
Indexes created Mon Sep 29 13:09:55 GMT 2025