zs.c revision 1.7
1 /* $NetBSD: zs.c,v 1.7 1999/03/27 01:21:36 wrstuden Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include "opt_ddb.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/conf.h> 52 #include <sys/device.h> 53 #include <sys/file.h> 54 #include <sys/ioctl.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/syslog.h> 60 61 #include <machine/autoconf.h> 62 #include <machine/cpu.h> 63 #include <machine/adrsmap.h> 64 #include <machine/z8530var.h> 65 66 #include <dev/cons.h> 67 #include <dev/ic/z8530reg.h> 68 69 #include "zsc.h" /* NZSC */ 70 #define NZS NZSC 71 72 /* Make life easier for the initialized arrays here. */ 73 #if NZS < 2 74 #undef NZS 75 #define NZS 2 76 #endif 77 78 extern void Debugger __P((void)); 79 80 /* 81 * Some warts needed by z8530tty.c - 82 * The default parity REALLY needs to be the same as the PROM uses, 83 * or you can not see messages done with printf during boot-up... 84 */ 85 int zs_def_cflag = (CREAD | CS8 | HUPCL); 86 int zs_major = 1; 87 88 /* 89 * The news3400 provides a 4.9152 MHz clock to the ZS chips. 90 */ 91 #define PCLK1 (9600 * 512) /* PCLK pin input clock rate */ 92 #define PCLK2 (9600 * 384) 93 94 /* 95 * Define interrupt levels. 96 */ 97 #define ZSHARD_PRI 64 98 99 #define ZS_DELAY() {(void)*(volatile char *)INTEN1; delay(2);} 100 101 /* The layout of this is hardware-dependent (padding, order). */ 102 struct zschan { 103 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 104 volatile u_char zc_data; /* data */ 105 }; 106 struct zsdevice { 107 /* Yes, they are backwards. */ 108 struct zschan zs_chan_b; 109 struct zschan zs_chan_a; 110 }; 111 112 static struct zsdevice *zsaddr[NZS]; 113 114 /* Flags from cninit() */ 115 static int zs_hwflags[NZS][2]; 116 117 /* Default speed for all channels */ 118 static int zs_defspeed = 9600; 119 120 static u_char zs_init_reg[16] = { 121 0, /* 0: CMD (reset, etc.) */ 122 0, /* 1: No interrupts yet. */ 123 ZSHARD_PRI, /* IVECT */ 124 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 125 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 126 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 127 0, /* 6: TXSYNC/SYNCLO */ 128 0, /* 7: RXSYNC/SYNCHI */ 129 0, /* 8: alias for data port */ 130 ZSWR9_MASTER_IE, 131 0, /*10: Misc. TX/RX control bits */ 132 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 133 ((PCLK1/32)/9600)-2, /*12: BAUDLO (default=9600) */ 134 0, /*13: BAUDHI (default=9600) */ 135 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 136 ZSWR15_BREAK_IE, 137 }; 138 139 140 struct zschan * 141 zs_get_chan_addr(zs_unit, channel) 142 int zs_unit, channel; 143 { 144 struct zsdevice *addr; 145 struct zschan *zc; 146 147 if (zs_unit >= NZS) 148 return NULL; 149 addr = zsaddr[zs_unit]; 150 if (addr == NULL) 151 return NULL; 152 if (channel == 0) { 153 zc = &addr->zs_chan_a; 154 } else { 155 zc = &addr->zs_chan_b; 156 } 157 return (zc); 158 } 159 160 161 /**************************************************************** 162 * Autoconfig 163 ****************************************************************/ 164 165 /* Definition of the driver for autoconfig. */ 166 static int zs_match __P((struct device *, struct cfdata *, void *)); 167 static void zs_attach __P((struct device *, struct device *, void *)); 168 static int zs_print __P((void *, const char *name)); 169 170 struct cfattach zsc_ca = { 171 sizeof(struct zsc_softc), zs_match, zs_attach 172 }; 173 174 extern struct cfdriver zsc_cd; 175 176 static void zshard __P((void *)); 177 static void zssoft __P((void *)); 178 static int zs_get_speed __P((struct zs_chanstate *)); 179 180 181 /* 182 * Is the zs chip present? 183 */ 184 static int 185 zs_match(parent, cf, aux) 186 struct device *parent; 187 struct cfdata *cf; 188 void *aux; 189 { 190 struct confargs *ca = aux; 191 int unit = cf->cf_unit; 192 void *va; 193 194 if (strcmp(ca->ca_name, "zsc")) 195 return 0; 196 197 va = zsaddr[unit]; 198 if (va == NULL) 199 va = zsaddr[unit] = (void *)cf->cf_addr; 200 201 /* This returns -1 on a fault (bus error). */ 202 if (badaddr(va, 1)) 203 return 0; 204 205 return 1; 206 } 207 208 /* 209 * Attach a found zs. 210 * 211 * Match slave number to zs unit number, so that misconfiguration will 212 * not set up the keyboard as ttya, etc. 213 */ 214 static void 215 zs_attach(parent, self, aux) 216 struct device *parent; 217 struct device *self; 218 void *aux; 219 { 220 struct zsc_softc *zsc = (void *) self; 221 /* struct confargs *ca = aux; */ 222 struct zsc_attach_args zsc_args; 223 volatile struct zschan *zc; 224 struct zs_chanstate *cs; 225 int s, zs_unit, channel; 226 static int didintr; 227 228 zs_unit = zsc->zsc_dev.dv_unit; 229 230 printf("\n"); 231 232 /* 233 * Initialize software state for each channel. 234 */ 235 for (channel = 0; channel < 2; channel++) { 236 zsc_args.channel = channel; 237 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 238 cs = &zsc->zsc_cs_store[channel]; 239 zsc->zsc_cs[channel] = cs; 240 241 cs->cs_channel = channel; 242 cs->cs_private = NULL; 243 cs->cs_ops = &zsops_null; 244 if (zs_unit == 0) 245 cs->cs_brg_clk = PCLK1 / 16; 246 else 247 cs->cs_brg_clk = PCLK2 / 16; 248 249 zc = zs_get_chan_addr(zs_unit, channel); 250 cs->cs_reg_csr = &zc->zc_csr; 251 cs->cs_reg_data = &zc->zc_data; 252 253 bcopy(zs_init_reg, cs->cs_creg, 16); 254 bcopy(zs_init_reg, cs->cs_preg, 16); 255 256 /* XXX: Get these from the EEPROM instead? */ 257 /* XXX: See the mvme167 code. Better. */ 258 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 259 cs->cs_defspeed = zs_get_speed(cs); 260 else 261 cs->cs_defspeed = zs_defspeed; 262 cs->cs_defcflag = zs_def_cflag; 263 264 /* Make these correspond to cs_defcflag (-crtscts) */ 265 cs->cs_rr0_dcd = ZSRR0_DCD; 266 cs->cs_rr0_cts = 0; 267 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 268 cs->cs_wr5_rts = 0; 269 270 /* 271 * Clear the master interrupt enable. 272 * The INTENA is common to both channels, 273 * so just do it on the A channel. 274 */ 275 if (channel == 0) { 276 zs_write_reg(cs, 9, 0); 277 } 278 279 /* 280 * Look for a child driver for this channel. 281 * The child attach will setup the hardware. 282 */ 283 if (!config_found(self, (void *)&zsc_args, zs_print)) { 284 /* No sub-driver. Just reset it. */ 285 u_char reset = (channel == 0) ? 286 ZSWR9_A_RESET : ZSWR9_B_RESET; 287 s = splhigh(); 288 zs_write_reg(cs, 9, reset); 289 splx(s); 290 } 291 } 292 293 /* 294 * Now safe to install interrupt handlers. Note the arguments 295 * to the interrupt handlers aren't used. Note, we only do this 296 * once since both SCCs interrupt at the same level and vector. 297 */ 298 if (!didintr) { 299 didintr = 1; 300 #if 0 301 isr_add_autovect(zssoft, NULL, ZSSOFT_PRI); 302 isr_add_autovect(zshard, NULL, ca->ca_intpri); 303 #endif 304 } 305 /* XXX; evcnt_attach() ? */ 306 307 /* 308 * Set the master interrupt enable and interrupt vector. 309 * (common to both channels, do it on A) 310 */ 311 cs = zsc->zsc_cs[0]; 312 s = splhigh(); 313 /* interrupt vector */ 314 zs_write_reg(cs, 2, zs_init_reg[2]); 315 /* master interrupt control (enable) */ 316 zs_write_reg(cs, 9, zs_init_reg[9]); 317 splx(s); 318 } 319 320 static int 321 zs_print(aux, name) 322 void *aux; 323 const char *name; 324 { 325 struct zsc_attach_args *args = aux; 326 327 if (name != NULL) 328 printf("%s: ", name); 329 330 if (args->channel != -1) 331 printf(" channel %d", args->channel); 332 333 return UNCONF; 334 } 335 336 static volatile int zssoftpending; 337 338 /* 339 * Our ZS chips all share a common, autovectored interrupt, 340 * so we have to look at all of them on each interrupt. 341 */ 342 static void 343 zshard(arg) 344 void *arg; 345 { 346 register struct zsc_softc *zsc; 347 register int unit, rval, softreq; 348 349 rval = softreq = 0; 350 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 351 zsc = zsc_cd.cd_devs[unit]; 352 if (zsc == NULL) 353 continue; 354 rval |= zsc_intr_hard(zsc); 355 softreq |= zsc->zsc_cs[0]->cs_softreq; 356 softreq |= zsc->zsc_cs[1]->cs_softreq; 357 } 358 359 /* We are at splzs here, so no need to lock. */ 360 if (softreq && (zssoftpending == 0)) { 361 zssoftpending = 1; 362 zssoft(arg); /*isr_soft_request(ZSSOFT_PRI);*/ 363 } 364 return; 365 } 366 367 /* 368 * Similar scheme as for zshard (look at all of them) 369 */ 370 static void 371 zssoft(arg) 372 void *arg; 373 { 374 register struct zsc_softc *zsc; 375 register int s, unit; 376 377 /* This is not the only ISR on this IPL. */ 378 if (zssoftpending == 0) 379 return; 380 381 /* 382 * The soft intr. bit will be set by zshard only if 383 * the variable zssoftpending is zero. The order of 384 * these next two statements prevents our clearing 385 * the soft intr bit just after zshard has set it. 386 */ 387 /*isr_soft_clear(ZSSOFT_PRI);*/ 388 /*zssoftpending = 0;*/ 389 390 /* Make sure we call the tty layer at spltty. */ 391 s = spltty(); 392 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 393 zsc = zsc_cd.cd_devs[unit]; 394 if (zsc == NULL) 395 continue; 396 (void) zsc_intr_soft(zsc); 397 } 398 splx(s); 399 zssoftpending = 0; 400 return; 401 } 402 403 404 /* 405 * Compute the current baud rate given a ZS channel. 406 */ 407 static int 408 zs_get_speed(cs) 409 struct zs_chanstate *cs; 410 { 411 int tconst; 412 413 tconst = zs_read_reg(cs, 12); 414 tconst |= zs_read_reg(cs, 13) << 8; 415 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 416 } 417 418 /* 419 * MD functions for setting the baud rate and control modes. 420 */ 421 int 422 zs_set_speed(cs, bps) 423 struct zs_chanstate *cs; 424 int bps; /* bits per second */ 425 { 426 int tconst, real_bps; 427 428 if (bps == 0) 429 return (0); 430 431 #ifdef DIAGNOSTIC 432 if (cs->cs_brg_clk == 0) 433 panic("zs_set_speed"); 434 #endif 435 436 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 437 if (tconst < 0) 438 return (EINVAL); 439 440 /* Convert back to make sure we can do it. */ 441 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 442 443 /* XXX - Allow some tolerance here? */ 444 if (real_bps != bps) 445 return (EINVAL); 446 447 cs->cs_preg[12] = tconst; 448 cs->cs_preg[13] = tconst >> 8; 449 450 /* Caller will stuff the pending registers. */ 451 return (0); 452 } 453 454 int 455 zs_set_modes(cs, cflag) 456 struct zs_chanstate *cs; 457 int cflag; /* bits per second */ 458 { 459 int s; 460 461 /* 462 * Output hardware flow control on the chip is horrendous: 463 * if carrier detect drops, the receiver is disabled, and if 464 * CTS drops, the transmitter is stoped IN MID CHARACTER! 465 * Therefore, NEVER set the HFC bit, and instead use the 466 * status interrupt to detect CTS changes. 467 */ 468 s = splzs(); 469 cs->cs_rr0_pps = 0; 470 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 471 cs->cs_rr0_dcd = 0; 472 if ((cflag & MDMBUF) == 0) 473 cs->cs_rr0_pps = ZSRR0_DCD; 474 } else 475 cs->cs_rr0_dcd = ZSRR0_DCD; 476 if ((cflag & CRTSCTS) != 0) { 477 cs->cs_wr5_dtr = ZSWR5_DTR; 478 cs->cs_wr5_rts = ZSWR5_RTS; 479 cs->cs_rr0_cts = ZSRR0_CTS; 480 } else if ((cflag & MDMBUF) != 0) { 481 cs->cs_wr5_dtr = 0; 482 cs->cs_wr5_rts = ZSWR5_DTR; 483 cs->cs_rr0_cts = ZSRR0_DCD; 484 } else { 485 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 486 cs->cs_wr5_rts = 0; 487 cs->cs_rr0_cts = 0; 488 } 489 splx(s); 490 491 /* Caller will stuff the pending registers. */ 492 return (0); 493 } 494 495 496 /* 497 * Read or write the chip with suitable delays. 498 */ 499 500 u_char 501 zs_read_reg(cs, reg) 502 struct zs_chanstate *cs; 503 u_char reg; 504 { 505 u_char val; 506 507 *cs->cs_reg_csr = reg; 508 ZS_DELAY(); 509 val = *cs->cs_reg_csr; 510 ZS_DELAY(); 511 return val; 512 } 513 514 void 515 zs_write_reg(cs, reg, val) 516 struct zs_chanstate *cs; 517 u_char reg, val; 518 { 519 *cs->cs_reg_csr = reg; 520 ZS_DELAY(); 521 *cs->cs_reg_csr = val; 522 ZS_DELAY(); 523 } 524 525 u_char zs_read_csr(cs) 526 struct zs_chanstate *cs; 527 { 528 register u_char val; 529 530 val = *cs->cs_reg_csr; 531 ZS_DELAY(); 532 return val; 533 } 534 535 void zs_write_csr(cs, val) 536 struct zs_chanstate *cs; 537 u_char val; 538 { 539 *cs->cs_reg_csr = val; 540 ZS_DELAY(); 541 } 542 543 u_char zs_read_data(cs) 544 struct zs_chanstate *cs; 545 { 546 register u_char val; 547 548 val = *cs->cs_reg_data; 549 ZS_DELAY(); 550 return val; 551 } 552 553 void zs_write_data(cs, val) 554 struct zs_chanstate *cs; 555 u_char val; 556 { 557 *cs->cs_reg_data = val; 558 ZS_DELAY(); 559 } 560 561 void 562 zs_abort(cs) 563 struct zs_chanstate *cs; 564 { 565 #ifdef DDB 566 Debugger(); 567 #endif 568 } 569 570 /* 571 * Polled input char. 572 */ 573 int 574 zs_getc(arg) 575 void *arg; 576 { 577 register volatile struct zschan *zc = arg; 578 register int s, c, rr0; 579 580 s = splhigh(); 581 /* Wait for a character to arrive. */ 582 do { 583 rr0 = zc->zc_csr; 584 ZS_DELAY(); 585 } while ((rr0 & ZSRR0_RX_READY) == 0); 586 587 c = zc->zc_data; 588 ZS_DELAY(); 589 splx(s); 590 591 /* 592 * This is used by the kd driver to read scan codes, 593 * so don't translate '\r' ==> '\n' here... 594 */ 595 return (c); 596 } 597 598 /* 599 * Polled output char. 600 */ 601 void 602 zs_putc(arg, c) 603 void *arg; 604 int c; 605 { 606 register volatile struct zschan *zc = arg; 607 register int s, rr0; 608 609 s = splhigh(); 610 /* Wait for transmitter to become ready. */ 611 do { 612 rr0 = zc->zc_csr; 613 ZS_DELAY(); 614 } while ((rr0 & ZSRR0_TX_READY) == 0); 615 616 zc->zc_data = c; 617 ZS_DELAY(); 618 splx(s); 619 } 620 621 /*****************************************************************/ 622 623 static void zscnprobe __P((struct consdev *)); 624 static void zscninit __P((struct consdev *)); 625 static int zscngetc __P((dev_t)); 626 static void zscnputc __P((dev_t, int)); 627 static void zscnpollc __P((dev_t, int)); 628 629 struct consdev consdev_zs = { 630 zscnprobe, 631 zscninit, 632 zscngetc, 633 zscnputc, 634 zscnpollc 635 }; 636 637 void 638 zscnprobe(cn) 639 struct consdev *cn; 640 { 641 } 642 643 void 644 zscninit(cn) 645 struct consdev *cn; 646 { 647 cn->cn_dev = makedev(zs_major, 0); 648 cn->cn_pri = CN_REMOTE; 649 zs_hwflags[0][0] = ZS_HWFLAG_CONSOLE; 650 } 651 652 int 653 zscngetc(dev) 654 dev_t dev; 655 { 656 return zs_getc(SCCPORT0A); 657 } 658 659 void 660 zscnputc(dev, c) 661 dev_t dev; 662 int c; 663 { 664 zs_putc(SCCPORT0A, c); 665 } 666 667 void 668 zscnpollc(dev, on) 669 dev_t dev; 670 int on; 671 { 672 } 673 674 /* 675 * ZS vector interrupt service routine. 676 */ 677 void 678 zs_intr() 679 { 680 int vec; 681 682 vec = *(volatile u_char *)SCCVECT; 683 zshard((void *)vec); /* XXX vec is not used */ 684 } 685
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