zs.c revision 1.9
1 /* $NetBSD: zs.c,v 1.9 1999/12/17 06:05:40 tsubai Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include "opt_ddb.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/conf.h> 52 #include <sys/device.h> 53 #include <sys/file.h> 54 #include <sys/ioctl.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/syslog.h> 60 61 #include <machine/autoconf.h> 62 #include <machine/cpu.h> 63 #include <machine/adrsmap.h> 64 #include <machine/z8530var.h> 65 66 #include <dev/cons.h> 67 #include <dev/ic/z8530reg.h> 68 69 #include "zsc.h" /* NZSC */ 70 #define NZS NZSC 71 72 /* Make life easier for the initialized arrays here. */ 73 #if NZS < 2 74 #undef NZS 75 #define NZS 2 76 #endif 77 78 extern void Debugger __P((void)); 79 80 /* 81 * Some warts needed by z8530tty.c - 82 * The default parity REALLY needs to be the same as the PROM uses, 83 * or you can not see messages done with printf during boot-up... 84 */ 85 int zs_def_cflag = (CREAD | CS8 | HUPCL); 86 int zs_major = 1; 87 88 /* 89 * The news3400 provides a 4.9152 MHz clock to the ZS chips. 90 */ 91 #define PCLK1 (9600 * 512) /* PCLK pin input clock rate */ 92 #define PCLK2 (9600 * 384) 93 94 /* 95 * Define interrupt levels. 96 */ 97 #define ZSHARD_PRI 64 98 99 #define ZS_DELAY() {(void)*(volatile char *)INTEN1; delay(2);} 100 101 /* The layout of this is hardware-dependent (padding, order). */ 102 struct zschan { 103 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 104 volatile u_char zc_data; /* data */ 105 }; 106 struct zsdevice { 107 /* Yes, they are backwards. */ 108 struct zschan zs_chan_b; 109 struct zschan zs_chan_a; 110 }; 111 112 static struct zsdevice *zsaddr[NZS]; 113 114 /* Flags from cninit() */ 115 static int zs_hwflags[NZS][2]; 116 117 /* Default speed for all channels */ 118 static int zs_defspeed = 9600; 119 120 static u_char zs_init_reg[16] = { 121 0, /* 0: CMD (reset, etc.) */ 122 0, /* 1: No interrupts yet. */ 123 ZSHARD_PRI, /* IVECT */ 124 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 125 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 126 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 127 0, /* 6: TXSYNC/SYNCLO */ 128 0, /* 7: RXSYNC/SYNCHI */ 129 0, /* 8: alias for data port */ 130 ZSWR9_MASTER_IE, 131 0, /*10: Misc. TX/RX control bits */ 132 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 133 ((PCLK1/32)/9600)-2, /*12: BAUDLO (default=9600) */ 134 0, /*13: BAUDHI (default=9600) */ 135 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 136 ZSWR15_BREAK_IE, 137 }; 138 139 140 struct zschan * 141 zs_get_chan_addr(zs_unit, channel) 142 int zs_unit, channel; 143 { 144 struct zsdevice *addr; 145 struct zschan *zc; 146 147 if (zs_unit >= NZS) 148 return NULL; 149 addr = zsaddr[zs_unit]; 150 if (addr == NULL) 151 return NULL; 152 if (channel == 0) { 153 zc = &addr->zs_chan_a; 154 } else { 155 zc = &addr->zs_chan_b; 156 } 157 return (zc); 158 } 159 160 161 /**************************************************************** 162 * Autoconfig 163 ****************************************************************/ 164 165 /* Definition of the driver for autoconfig. */ 166 static int zs_match __P((struct device *, struct cfdata *, void *)); 167 static void zs_attach __P((struct device *, struct device *, void *)); 168 static int zs_print __P((void *, const char *name)); 169 170 struct cfattach zsc_ca = { 171 sizeof(struct zsc_softc), zs_match, zs_attach 172 }; 173 174 extern struct cfdriver zsc_cd; 175 176 static int zshard __P((void *)); 177 static void zssoft __P((void *)); 178 static int zs_get_speed __P((struct zs_chanstate *)); 179 180 181 /* 182 * Is the zs chip present? 183 */ 184 static int 185 zs_match(parent, cf, aux) 186 struct device *parent; 187 struct cfdata *cf; 188 void *aux; 189 { 190 struct confargs *ca = aux; 191 192 if (strcmp(ca->ca_name, "zsc")) 193 return 0; 194 195 /* This returns -1 on a fault (bus error). */ 196 if (badaddr((char *)cf->cf_addr, 1)) 197 return 0; 198 199 return 1; 200 } 201 202 /* 203 * Attach a found zs. 204 * 205 * Match slave number to zs unit number, so that misconfiguration will 206 * not set up the keyboard as ttya, etc. 207 */ 208 static void 209 zs_attach(parent, self, aux) 210 struct device *parent; 211 struct device *self; 212 void *aux; 213 { 214 struct zsc_softc *zsc = (void *)self; 215 /* struct confargs *ca = aux; */ 216 struct zsc_attach_args zsc_args; 217 volatile struct zschan *zc; 218 struct zs_chanstate *cs; 219 int s, zs_unit, channel, intlevel; 220 static int didintr; 221 222 zs_unit = zsc->zsc_dev.dv_unit; 223 intlevel = zsc->zsc_dev.dv_cfdata->cf_level; 224 zsaddr[zs_unit] = (void *)zsc->zsc_dev.dv_cfdata->cf_addr; 225 226 if (intlevel == -1) { 227 #if 0 228 printf(": interrupt level not configured\n"); 229 return; 230 #else 231 printf(": interrupt level not configured; using"); 232 intlevel = 1; 233 #endif 234 } 235 236 printf(" level %d\n", intlevel); 237 238 /* 239 * Initialize software state for each channel. 240 */ 241 for (channel = 0; channel < 2; channel++) { 242 zsc_args.channel = channel; 243 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 244 cs = &zsc->zsc_cs_store[channel]; 245 zsc->zsc_cs[channel] = cs; 246 247 cs->cs_channel = channel; 248 cs->cs_private = NULL; 249 cs->cs_ops = &zsops_null; 250 if (zs_unit == 0) 251 cs->cs_brg_clk = PCLK1 / 16; 252 else 253 cs->cs_brg_clk = PCLK2 / 16; 254 255 zc = zs_get_chan_addr(zs_unit, channel); 256 cs->cs_reg_csr = &zc->zc_csr; 257 cs->cs_reg_data = &zc->zc_data; 258 259 bcopy(zs_init_reg, cs->cs_creg, 16); 260 bcopy(zs_init_reg, cs->cs_preg, 16); 261 262 /* XXX: Get these from the EEPROM instead? */ 263 /* XXX: See the mvme167 code. Better. */ 264 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 265 cs->cs_defspeed = zs_get_speed(cs); 266 else 267 cs->cs_defspeed = zs_defspeed; 268 cs->cs_defcflag = zs_def_cflag; 269 270 /* Make these correspond to cs_defcflag (-crtscts) */ 271 cs->cs_rr0_dcd = ZSRR0_DCD; 272 cs->cs_rr0_cts = 0; 273 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 274 cs->cs_wr5_rts = 0; 275 276 /* 277 * Clear the master interrupt enable. 278 * The INTENA is common to both channels, 279 * so just do it on the A channel. 280 */ 281 if (channel == 0) { 282 zs_write_reg(cs, 9, 0); 283 } 284 285 /* 286 * Look for a child driver for this channel. 287 * The child attach will setup the hardware. 288 */ 289 if (!config_found(self, (void *)&zsc_args, zs_print)) { 290 /* No sub-driver. Just reset it. */ 291 u_char reset = (channel == 0) ? 292 ZSWR9_A_RESET : ZSWR9_B_RESET; 293 s = splhigh(); 294 zs_write_reg(cs, 9, reset); 295 splx(s); 296 } 297 } 298 299 /* 300 * Now safe to install interrupt handlers. Note the arguments 301 * to the interrupt handlers aren't used. Note, we only do this 302 * once since both SCCs interrupt at the same level and vector. 303 */ 304 if (!didintr) { 305 didintr = 1; 306 307 hb_intr_establish(intlevel, IPL_SERIAL, zshard, NULL); 308 } 309 /* XXX; evcnt_attach() ? */ 310 311 /* 312 * Set the master interrupt enable and interrupt vector. 313 * (common to both channels, do it on A) 314 */ 315 cs = zsc->zsc_cs[0]; 316 s = splhigh(); 317 /* interrupt vector */ 318 zs_write_reg(cs, 2, zs_init_reg[2]); 319 /* master interrupt control (enable) */ 320 zs_write_reg(cs, 9, zs_init_reg[9]); 321 splx(s); 322 } 323 324 static int 325 zs_print(aux, name) 326 void *aux; 327 const char *name; 328 { 329 struct zsc_attach_args *args = aux; 330 331 if (name != NULL) 332 printf("%s: ", name); 333 334 if (args->channel != -1) 335 printf(" channel %d", args->channel); 336 337 return UNCONF; 338 } 339 340 static volatile int zssoftpending; 341 342 /* 343 * Our ZS chips all share a common, autovectored interrupt, 344 * so we have to look at all of them on each interrupt. 345 */ 346 static int 347 zshard(arg) 348 void *arg; 349 { 350 register struct zsc_softc *zsc; 351 register int unit, rval, softreq; 352 353 (void) *(volatile u_char *)SCCVECT; 354 355 rval = softreq = 0; 356 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 357 zsc = zsc_cd.cd_devs[unit]; 358 if (zsc == NULL) 359 continue; 360 rval |= zsc_intr_hard(zsc); 361 softreq |= zsc->zsc_cs[0]->cs_softreq; 362 softreq |= zsc->zsc_cs[1]->cs_softreq; 363 } 364 365 /* We are at splzs here, so no need to lock. */ 366 if (softreq && (zssoftpending == 0)) { 367 zssoftpending = 1; 368 zssoft(arg); /*isr_soft_request(ZSSOFT_PRI);*/ 369 } 370 return rval; 371 } 372 373 /* 374 * Similar scheme as for zshard (look at all of them) 375 */ 376 static void 377 zssoft(arg) 378 void *arg; 379 { 380 register struct zsc_softc *zsc; 381 register int s, unit; 382 383 /* This is not the only ISR on this IPL. */ 384 if (zssoftpending == 0) 385 return; 386 387 /* 388 * The soft intr. bit will be set by zshard only if 389 * the variable zssoftpending is zero. The order of 390 * these next two statements prevents our clearing 391 * the soft intr bit just after zshard has set it. 392 */ 393 /*isr_soft_clear(ZSSOFT_PRI);*/ 394 /*zssoftpending = 0;*/ 395 396 /* Make sure we call the tty layer at spltty. */ 397 s = spltty(); 398 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 399 zsc = zsc_cd.cd_devs[unit]; 400 if (zsc == NULL) 401 continue; 402 (void) zsc_intr_soft(zsc); 403 } 404 splx(s); 405 zssoftpending = 0; 406 return; 407 } 408 409 410 /* 411 * Compute the current baud rate given a ZS channel. 412 */ 413 static int 414 zs_get_speed(cs) 415 struct zs_chanstate *cs; 416 { 417 int tconst; 418 419 tconst = zs_read_reg(cs, 12); 420 tconst |= zs_read_reg(cs, 13) << 8; 421 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 422 } 423 424 /* 425 * MD functions for setting the baud rate and control modes. 426 */ 427 int 428 zs_set_speed(cs, bps) 429 struct zs_chanstate *cs; 430 int bps; /* bits per second */ 431 { 432 int tconst, real_bps; 433 434 if (bps == 0) 435 return (0); 436 437 #ifdef DIAGNOSTIC 438 if (cs->cs_brg_clk == 0) 439 panic("zs_set_speed"); 440 #endif 441 442 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 443 if (tconst < 0) 444 return (EINVAL); 445 446 /* Convert back to make sure we can do it. */ 447 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 448 449 /* XXX - Allow some tolerance here? */ 450 if (real_bps != bps) 451 return (EINVAL); 452 453 cs->cs_preg[12] = tconst; 454 cs->cs_preg[13] = tconst >> 8; 455 456 /* Caller will stuff the pending registers. */ 457 return (0); 458 } 459 460 int 461 zs_set_modes(cs, cflag) 462 struct zs_chanstate *cs; 463 int cflag; /* bits per second */ 464 { 465 int s; 466 467 /* 468 * Output hardware flow control on the chip is horrendous: 469 * if carrier detect drops, the receiver is disabled, and if 470 * CTS drops, the transmitter is stoped IN MID CHARACTER! 471 * Therefore, NEVER set the HFC bit, and instead use the 472 * status interrupt to detect CTS changes. 473 */ 474 s = splzs(); 475 cs->cs_rr0_pps = 0; 476 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 477 cs->cs_rr0_dcd = 0; 478 if ((cflag & MDMBUF) == 0) 479 cs->cs_rr0_pps = ZSRR0_DCD; 480 } else 481 cs->cs_rr0_dcd = ZSRR0_DCD; 482 if ((cflag & CRTSCTS) != 0) { 483 cs->cs_wr5_dtr = ZSWR5_DTR; 484 cs->cs_wr5_rts = ZSWR5_RTS; 485 cs->cs_rr0_cts = ZSRR0_CTS; 486 } else if ((cflag & MDMBUF) != 0) { 487 cs->cs_wr5_dtr = 0; 488 cs->cs_wr5_rts = ZSWR5_DTR; 489 cs->cs_rr0_cts = ZSRR0_DCD; 490 } else { 491 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 492 cs->cs_wr5_rts = 0; 493 cs->cs_rr0_cts = 0; 494 } 495 splx(s); 496 497 /* Caller will stuff the pending registers. */ 498 return (0); 499 } 500 501 502 /* 503 * Read or write the chip with suitable delays. 504 */ 505 506 u_char 507 zs_read_reg(cs, reg) 508 struct zs_chanstate *cs; 509 u_char reg; 510 { 511 u_char val; 512 513 *cs->cs_reg_csr = reg; 514 ZS_DELAY(); 515 val = *cs->cs_reg_csr; 516 ZS_DELAY(); 517 return val; 518 } 519 520 void 521 zs_write_reg(cs, reg, val) 522 struct zs_chanstate *cs; 523 u_char reg, val; 524 { 525 *cs->cs_reg_csr = reg; 526 ZS_DELAY(); 527 *cs->cs_reg_csr = val; 528 ZS_DELAY(); 529 } 530 531 u_char zs_read_csr(cs) 532 struct zs_chanstate *cs; 533 { 534 register u_char val; 535 536 val = *cs->cs_reg_csr; 537 ZS_DELAY(); 538 return val; 539 } 540 541 void zs_write_csr(cs, val) 542 struct zs_chanstate *cs; 543 u_char val; 544 { 545 *cs->cs_reg_csr = val; 546 ZS_DELAY(); 547 } 548 549 u_char zs_read_data(cs) 550 struct zs_chanstate *cs; 551 { 552 register u_char val; 553 554 val = *cs->cs_reg_data; 555 ZS_DELAY(); 556 return val; 557 } 558 559 void zs_write_data(cs, val) 560 struct zs_chanstate *cs; 561 u_char val; 562 { 563 *cs->cs_reg_data = val; 564 ZS_DELAY(); 565 } 566 567 void 568 zs_abort(cs) 569 struct zs_chanstate *cs; 570 { 571 #ifdef DDB 572 Debugger(); 573 #endif 574 } 575 576 /* 577 * Polled input char. 578 */ 579 int 580 zs_getc(arg) 581 void *arg; 582 { 583 register volatile struct zschan *zc = arg; 584 register int s, c, rr0; 585 586 s = splhigh(); 587 /* Wait for a character to arrive. */ 588 do { 589 rr0 = zc->zc_csr; 590 ZS_DELAY(); 591 } while ((rr0 & ZSRR0_RX_READY) == 0); 592 593 c = zc->zc_data; 594 ZS_DELAY(); 595 splx(s); 596 597 /* 598 * This is used by the kd driver to read scan codes, 599 * so don't translate '\r' ==> '\n' here... 600 */ 601 return (c); 602 } 603 604 /* 605 * Polled output char. 606 */ 607 void 608 zs_putc(arg, c) 609 void *arg; 610 int c; 611 { 612 register volatile struct zschan *zc = arg; 613 register int s, rr0; 614 615 s = splhigh(); 616 /* Wait for transmitter to become ready. */ 617 do { 618 rr0 = zc->zc_csr; 619 ZS_DELAY(); 620 } while ((rr0 & ZSRR0_TX_READY) == 0); 621 622 zc->zc_data = c; 623 ZS_DELAY(); 624 splx(s); 625 } 626 627 /*****************************************************************/ 628 629 static void zscnprobe __P((struct consdev *)); 630 static void zscninit __P((struct consdev *)); 631 static int zscngetc __P((dev_t)); 632 static void zscnputc __P((dev_t, int)); 633 static void zscnpollc __P((dev_t, int)); 634 635 struct consdev consdev_zs = { 636 zscnprobe, 637 zscninit, 638 zscngetc, 639 zscnputc, 640 zscnpollc 641 }; 642 643 void 644 zscnprobe(cn) 645 struct consdev *cn; 646 { 647 } 648 649 void 650 zscninit(cn) 651 struct consdev *cn; 652 { 653 cn->cn_dev = makedev(zs_major, 0); 654 cn->cn_pri = CN_REMOTE; 655 zs_hwflags[0][0] = ZS_HWFLAG_CONSOLE; 656 } 657 658 int 659 zscngetc(dev) 660 dev_t dev; 661 { 662 return zs_getc(SCCPORT0A); 663 } 664 665 void 666 zscnputc(dev, c) 667 dev_t dev; 668 int c; 669 { 670 zs_putc(SCCPORT0A, c); 671 } 672 673 void 674 zscnpollc(dev, on) 675 dev_t dev; 676 int on; 677 { 678 } 679
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