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adrsmap.h revision 1.2
      1  1.2  hubertf /*	$NetBSD: adrsmap.h,v 1.2 1999/02/15 04:36:35 hubertf Exp $	*/
      2  1.1   tsubai /*
      3  1.1   tsubai  * Copyright (c) 1992, 1993
      4  1.1   tsubai  *	The Regents of the University of California.  All rights reserved.
      5  1.1   tsubai  *
      6  1.1   tsubai  * This code is derived from software contributed to Berkeley by
      7  1.1   tsubai  * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc.
      8  1.1   tsubai  *
      9  1.1   tsubai  * Redistribution and use in source and binary forms, with or without
     10  1.1   tsubai  * modification, are permitted provided that the following conditions
     11  1.1   tsubai  * are met:
     12  1.1   tsubai  * 1. Redistributions of source code must retain the above copyright
     13  1.1   tsubai  *    notice, this list of conditions and the following disclaimer.
     14  1.1   tsubai  * 2. Redistributions in binary form must reproduce the above copyright
     15  1.1   tsubai  *    notice, this list of conditions and the following disclaimer in the
     16  1.1   tsubai  *    documentation and/or other materials provided with the distribution.
     17  1.1   tsubai  * 3. All advertising materials mentioning features or use of this software
     18  1.1   tsubai  *    must display the following acknowledgement:
     19  1.1   tsubai  *	This product includes software developed by the University of
     20  1.1   tsubai  *	California, Berkeley and its contributors.
     21  1.1   tsubai  * 4. Neither the name of the University nor the names of its contributors
     22  1.1   tsubai  *    may be used to endorse or promote products derived from this software
     23  1.1   tsubai  *    without specific prior written permission.
     24  1.1   tsubai  *
     25  1.1   tsubai  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     26  1.1   tsubai  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     27  1.1   tsubai  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     28  1.1   tsubai  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     29  1.1   tsubai  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     30  1.1   tsubai  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     31  1.1   tsubai  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     32  1.1   tsubai  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     33  1.1   tsubai  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     34  1.1   tsubai  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     35  1.1   tsubai  * SUCH DAMAGE.
     36  1.1   tsubai  *
     37  1.1   tsubai  * from: $Hdr: adrsmap.h,v 4.300 91/06/09 06:34:29 root Rel41 $ SONY
     38  1.1   tsubai  *
     39  1.1   tsubai  *	@(#)adrsmap.h	8.1 (Berkeley) 6/11/93
     40  1.1   tsubai  */
     41  1.1   tsubai 
     42  1.1   tsubai /*
     43  1.1   tsubai  * adrsmap.h
     44  1.1   tsubai  *
     45  1.1   tsubai  * Define all hardware address map.
     46  1.1   tsubai  */
     47  1.1   tsubai 
     48  1.1   tsubai #ifndef __ADRSMAP__
     49  1.1   tsubai #define	__ADRSMAP__	1
     50  1.1   tsubai 
     51  1.1   tsubai #ifdef news3400
     52  1.1   tsubai /*----------------------------------------------------------------------
     53  1.1   tsubai  *	news3400
     54  1.1   tsubai  *----------------------------------------------------------------------*/
     55  1.1   tsubai /*
     56  1.1   tsubai  * timer
     57  1.1   tsubai  */
     58  1.1   tsubai #define	RTC_PORT	0xbff407f8
     59  1.1   tsubai #define	DATA_PORT	0xbff407f9
     60  1.1   tsubai 
     61  1.1   tsubai #ifdef notdef
     62  1.1   tsubai #define	EN_ITIMER	0xb8000004	/*XXX:???*/
     63  1.1   tsubai #endif
     64  1.1   tsubai 
     65  1.1   tsubai #define	INTEN0	0xbfc80000
     66  1.1   tsubai #define		INTEN0_PERR	0x80
     67  1.1   tsubai #define		INTEN0_ABORT	0x40
     68  1.1   tsubai #define		INTEN0_BERR	0x20
     69  1.1   tsubai #define		INTEN0_TIMINT	0x10
     70  1.1   tsubai #define		INTEN0_KBDINT	0x08
     71  1.1   tsubai #define		INTEN0_MSINT	0x04
     72  1.1   tsubai #define		INTEN0_CFLT	0x02
     73  1.1   tsubai #define		INTEN0_CBSY	0x01
     74  1.1   tsubai 
     75  1.1   tsubai #define	INTEN1	0xbfc80001
     76  1.1   tsubai #define		INTEN1_BEEP	0x80
     77  1.1   tsubai #define		INTEN1_SCC	0x40
     78  1.1   tsubai #define		INTEN1_LANCE	0x20
     79  1.1   tsubai #define		INTEN1_DMA	0x10
     80  1.1   tsubai #define		INTEN1_SLOT1	0x08
     81  1.1   tsubai #define		INTEN1_SLOT3	0x04
     82  1.1   tsubai #define		INTEN1_EXT1	0x02
     83  1.1   tsubai #define		INTEN1_EXT3	0x01
     84  1.1   tsubai 
     85  1.1   tsubai #define	INTST0	0xbfc80002
     86  1.1   tsubai #define		INTST0_PERR	0x80
     87  1.1   tsubai #define		INTST0_ABORT	0x40
     88  1.1   tsubai #define		INTST0_BERR	0x00	/* N/A */
     89  1.1   tsubai #define		INTST0_TIMINT	0x10
     90  1.1   tsubai #define		INTST0_KBDINT	0x08
     91  1.1   tsubai #define		INTST0_MSINT	0x04
     92  1.1   tsubai #define		INTST0_CFLT	0x02
     93  1.1   tsubai #define		INTST0_CBSY	0x01
     94  1.1   tsubai #define			INTST0_PERR_BIT		7
     95  1.1   tsubai #define			INTST0_ABORT_BIT	6
     96  1.1   tsubai #define			INTST0_BERR_BIT		5	/* N/A */
     97  1.1   tsubai #define			INTST0_TIMINT_BIT	4
     98  1.1   tsubai #define			INTST0_KBDINT_BIT	3
     99  1.1   tsubai #define			INTST0_MSINT_BIT	2
    100  1.1   tsubai #define			INTST0_CFLT_BIT		1
    101  1.1   tsubai #define			INTST0_CBSY_BIT		0
    102  1.1   tsubai 
    103  1.1   tsubai #define	INTST1	0xbfc80003
    104  1.1   tsubai #define		INTST1_BEEP	0x80
    105  1.1   tsubai #define		INTST1_SCC	0x40
    106  1.1   tsubai #define		INTST1_LANCE	0x20
    107  1.1   tsubai #define		INTST1_DMA	0x10
    108  1.1   tsubai #define		INTST1_SLOT1	0x08
    109  1.1   tsubai #define		INTST1_SLOT3	0x04
    110  1.1   tsubai #define		INTST1_EXT1	0x02
    111  1.1   tsubai #define		INTST1_EXT3	0x01
    112  1.1   tsubai #define			INTST1_BEEP_BIT		7
    113  1.1   tsubai #define			INTST1_SCC_BIT		6
    114  1.1   tsubai #define			INTST1_LANCE_BIT	5
    115  1.1   tsubai #define			INTST1_DMA_BIT		4
    116  1.1   tsubai #define			INTST1_SLOT1_BIT	3
    117  1.1   tsubai #define			INTST1_SLOT3_BIT	2
    118  1.1   tsubai #define			INTST1_EXT1_BIT		1
    119  1.1   tsubai #define			INTST1_EXT3_BIT		0
    120  1.1   tsubai 
    121  1.1   tsubai #define	INTCLR0	0xbfc80004
    122  1.1   tsubai #define		INTCLR0_PERR	0x80
    123  1.1   tsubai #define		INTCLR0_ABORT	0x40
    124  1.1   tsubai #define		INTCLR0_BERR	0x20
    125  1.1   tsubai #define		INTCLR0_TIMINT	0x10
    126  1.1   tsubai #define		INTCLR0_KBDINT	0x00	/* N/A */
    127  1.1   tsubai #define		INTCLR0_MSINT	0x00	/* N/A */
    128  1.1   tsubai #define		INTCLR0_CFLT	0x02
    129  1.1   tsubai #define		INTCLR0_CBSY	0x01
    130  1.1   tsubai 
    131  1.1   tsubai #define	INTCLR1	0xbfc80005
    132  1.1   tsubai #define		INTCLR1_BEEP	0x80
    133  1.1   tsubai #define		INTCLR1_SCC	0x00	/* N/A */
    134  1.1   tsubai #define		INTCLR1_LANCE	0x00	/* N/A */
    135  1.1   tsubai #define		INTCLR1_DMA	0x00	/* N/A */
    136  1.1   tsubai #define		INTCLR1_SLOT1	0x00	/* N/A */
    137  1.1   tsubai #define		INTCLR1_SLOT3	0x00	/* N/A */
    138  1.1   tsubai #define		INTCLR1_EXT1	0x00	/* N/A */
    139  1.1   tsubai #define		INTCLR1_EXT3	0x00	/* N/A */
    140  1.1   tsubai 
    141  1.1   tsubai #define	ITIMER		0xbfc80006
    142  1.1   tsubai #define	IOCLOCK		4915200
    143  1.1   tsubai 
    144  1.1   tsubai #define	DIP_SWITCH	0xbfe40000
    145  1.1   tsubai #define	IDROM		0xbfe80000
    146  1.1   tsubai 
    147  1.1   tsubai #define	DEBUG_PORT	0xbfcc0003
    148  1.1   tsubai #define		DP_READ		0x00
    149  1.1   tsubai #define		DP_WRITE	0xf0
    150  1.1   tsubai #define		DP_LED0		0x01
    151  1.1   tsubai #define		DP_LED1		0x02
    152  1.1   tsubai #define		DP_LED2		0x04
    153  1.1   tsubai #define		DP_LED3		0x08
    154  1.1   tsubai 
    155  1.1   tsubai 
    156  1.1   tsubai #define	LANCE_PORT	0xbff80000
    157  1.1   tsubai #define	LANCE_MEMORY	0xbffc0000
    158  1.1   tsubai #define	ETHER_ID	IDROM_PORT
    159  1.1   tsubai 
    160  1.1   tsubai #define	LANCE_PORT1	0xb8c30000	/* expansion lance #1 */
    161  1.1   tsubai #define	LANCE_MEMORY1	0xb8c20000
    162  1.1   tsubai #define	ETHER_ID1	0xb8c38000
    163  1.1   tsubai 
    164  1.1   tsubai #define	LANCE_PORT2	0xb8c70000	/* expansion lance #2 */
    165  1.1   tsubai #define	LANCE_MEMORY2	0xb8c60000
    166  1.1   tsubai #define	ETHER_ID2	0xb8c78000
    167  1.1   tsubai 
    168  1.1   tsubai #define	IDROM_PORT	0xbfe80000
    169  1.1   tsubai 
    170  1.1   tsubai #define	SCCPORT0B	0xbfec0000
    171  1.1   tsubai #define	SCCPORT0A	0xbfec0002
    172  1.1   tsubai #define SCCPORT1B	0xb8c40100
    173  1.1   tsubai #define SCCPORT1A	0xb8c40102
    174  1.1   tsubai #define SCCPORT2B	0xb8c40104
    175  1.1   tsubai #define SCCPORT2A	0xb8c40106
    176  1.1   tsubai #define SCCPORT3B	0xb8c40110
    177  1.1   tsubai #define SCCPORT3A	0xb8c40112
    178  1.1   tsubai #define SCCPORT4B	0xb8c40114
    179  1.1   tsubai #define SCCPORT4A	0xb8c40116
    180  1.1   tsubai 
    181  1.1   tsubai #define	SCC_STATUS0	0xbfcc0002
    182  1.1   tsubai #define	SCC_STATUS1	0xb8c40108
    183  1.1   tsubai #define	SCC_STATUS2	0xb8c40118
    184  1.1   tsubai 
    185  1.1   tsubai #define	SCCVECT		(0x1fcc0007 | MIPS_KSEG1_START)
    186  1.1   tsubai #define	SCC_RECV	2
    187  1.1   tsubai #define	SCC_XMIT	0
    188  1.1   tsubai #define	SCC_CTRL	3
    189  1.1   tsubai #define	SCC_STAT	1
    190  1.1   tsubai #define	SCC_INT_MASK	0x6
    191  1.1   tsubai 
    192  1.1   tsubai /*XXX: SHOULD BE FIX*/
    193  1.1   tsubai #define	KEYB_DATA	0xbfd00000	/* keyboard data port */
    194  1.1   tsubai #define KEYB_STAT	0xbfd00001	/* keyboard status port */
    195  1.1   tsubai #define	KEYB_INTE	INTEN0		/* keyboard interrupt enable */
    196  1.1   tsubai #define	KEYB_RESET	0xbfd00002	/* keyboard reset port*/
    197  1.1   tsubai #define	KEYB_INIT1	0xbfd00003	/* keyboard speed */
    198  1.1   tsubai #define	KEYB_INIT2	KEYB_INIT1	/* keyboard clock */
    199  1.1   tsubai #define	KEYB_BUZZ	0xbfd40001	/* keyboard buzzer (length) */
    200  1.1   tsubai #define	KEYB_BUZZF	0xbfd40000	/* keyboard buzzer frequency */
    201  1.1   tsubai #define	MOUSE_DATA	0xbfd00004	/* mouse data port */
    202  1.1   tsubai #define MOUSE_STAT	0xbfd00005	/* mouse status port */
    203  1.1   tsubai #define	MOUSE_INTE	INTEN0		/* mouse interrupt enable */
    204  1.1   tsubai #define	MOUSE_RESET	0xbfd00006	/* mouse reset port */
    205  1.1   tsubai #define	MOUSE_INIT1	0xbfd00007	/* mouse speed */
    206  1.1   tsubai #define	MOUSE_INIT2	MOUSE_INIT1	/* mouse clock */
    207  1.1   tsubai 
    208  1.1   tsubai #define	RX_MSINTE	0x04		/* Mouse Interrupt Enable */
    209  1.1   tsubai #define RX_KBINTE	0x08		/* Keyboard Intr. Enable */
    210  1.1   tsubai #define	RX_MSINT	0x04		/* Mouse Interrupted */
    211  1.1   tsubai #define	RX_KBINT	0x08		/* Keyboard Interrupted */
    212  1.1   tsubai #define	RX_MSBUF	0x01		/* Mouse data buffer Full */
    213  1.1   tsubai #define	RX_KBBUF	0x01		/* Keyboard data Full */
    214  1.1   tsubai #define	RX_MSRDY	0x02		/* Mouse data ready */
    215  1.1   tsubai #define	RX_KBRDY	0x02		/* Keyboard data ready */
    216  1.1   tsubai /*XXX: SHOULD BE FIX*/
    217  1.1   tsubai 
    218  1.1   tsubai #define	ABEINT_BADDR	0xbfdc0038
    219  1.1   tsubai #endif /* news3400 */
    220  1.1   tsubai 
    221  1.1   tsubai #endif /* !__ADRSMAP__ */
    222