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adrsmap.h revision 1.9
      1  1.9  tsutsui /*	$NetBSD: adrsmap.h,v 1.9 2018/10/14 00:10:11 tsutsui Exp $	*/
      2  1.3   tsubai 
      3  1.1   tsubai /*
      4  1.1   tsubai  * Copyright (c) 1992, 1993
      5  1.1   tsubai  *	The Regents of the University of California.  All rights reserved.
      6  1.1   tsubai  *
      7  1.1   tsubai  * This code is derived from software contributed to Berkeley by
      8  1.1   tsubai  * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc.
      9  1.1   tsubai  *
     10  1.1   tsubai  * Redistribution and use in source and binary forms, with or without
     11  1.1   tsubai  * modification, are permitted provided that the following conditions
     12  1.1   tsubai  * are met:
     13  1.1   tsubai  * 1. Redistributions of source code must retain the above copyright
     14  1.1   tsubai  *    notice, this list of conditions and the following disclaimer.
     15  1.1   tsubai  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.1   tsubai  *    notice, this list of conditions and the following disclaimer in the
     17  1.1   tsubai  *    documentation and/or other materials provided with the distribution.
     18  1.7      agc  * 3. Neither the name of the University nor the names of its contributors
     19  1.1   tsubai  *    may be used to endorse or promote products derived from this software
     20  1.1   tsubai  *    without specific prior written permission.
     21  1.1   tsubai  *
     22  1.1   tsubai  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     23  1.1   tsubai  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     24  1.1   tsubai  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     25  1.1   tsubai  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     26  1.1   tsubai  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     27  1.1   tsubai  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     28  1.1   tsubai  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29  1.1   tsubai  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30  1.1   tsubai  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31  1.1   tsubai  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  1.1   tsubai  * SUCH DAMAGE.
     33  1.1   tsubai  *
     34  1.1   tsubai  * from: $Hdr: adrsmap.h,v 4.300 91/06/09 06:34:29 root Rel41 $ SONY
     35  1.1   tsubai  *
     36  1.1   tsubai  *	@(#)adrsmap.h	8.1 (Berkeley) 6/11/93
     37  1.1   tsubai  */
     38  1.1   tsubai 
     39  1.1   tsubai /*
     40  1.1   tsubai  * adrsmap.h
     41  1.1   tsubai  *
     42  1.1   tsubai  * Define all hardware address map.
     43  1.1   tsubai  */
     44  1.1   tsubai 
     45  1.3   tsubai #ifndef __MACHINE_ADRSMAP__
     46  1.3   tsubai #define __MACHINE_ADRSMAP__
     47  1.1   tsubai 
     48  1.1   tsubai /*----------------------------------------------------------------------
     49  1.1   tsubai  *	news3400
     50  1.1   tsubai  *----------------------------------------------------------------------*/
     51  1.1   tsubai /*
     52  1.1   tsubai  * timer
     53  1.1   tsubai  */
     54  1.1   tsubai #define	RTC_PORT	0xbff407f8
     55  1.1   tsubai #define	DATA_PORT	0xbff407f9
     56  1.1   tsubai 
     57  1.1   tsubai #ifdef notdef
     58  1.1   tsubai #define	EN_ITIMER	0xb8000004	/*XXX:???*/
     59  1.1   tsubai #endif
     60  1.1   tsubai 
     61  1.1   tsubai #define	INTEN0	0xbfc80000
     62  1.1   tsubai #define		INTEN0_PERR	0x80
     63  1.1   tsubai #define		INTEN0_ABORT	0x40
     64  1.1   tsubai #define		INTEN0_BERR	0x20
     65  1.1   tsubai #define		INTEN0_TIMINT	0x10
     66  1.1   tsubai #define		INTEN0_KBDINT	0x08
     67  1.1   tsubai #define		INTEN0_MSINT	0x04
     68  1.1   tsubai #define		INTEN0_CFLT	0x02
     69  1.1   tsubai #define		INTEN0_CBSY	0x01
     70  1.1   tsubai 
     71  1.1   tsubai #define	INTEN1	0xbfc80001
     72  1.1   tsubai #define		INTEN1_BEEP	0x80
     73  1.1   tsubai #define		INTEN1_SCC	0x40
     74  1.1   tsubai #define		INTEN1_LANCE	0x20
     75  1.1   tsubai #define		INTEN1_DMA	0x10
     76  1.1   tsubai #define		INTEN1_SLOT1	0x08
     77  1.1   tsubai #define		INTEN1_SLOT3	0x04
     78  1.1   tsubai #define		INTEN1_EXT1	0x02
     79  1.1   tsubai #define		INTEN1_EXT3	0x01
     80  1.1   tsubai 
     81  1.1   tsubai #define	INTST0	0xbfc80002
     82  1.1   tsubai #define		INTST0_PERR	0x80
     83  1.1   tsubai #define		INTST0_ABORT	0x40
     84  1.1   tsubai #define		INTST0_BERR	0x00	/* N/A */
     85  1.1   tsubai #define		INTST0_TIMINT	0x10
     86  1.1   tsubai #define		INTST0_KBDINT	0x08
     87  1.1   tsubai #define		INTST0_MSINT	0x04
     88  1.1   tsubai #define		INTST0_CFLT	0x02
     89  1.1   tsubai #define		INTST0_CBSY	0x01
     90  1.1   tsubai #define			INTST0_PERR_BIT		7
     91  1.1   tsubai #define			INTST0_ABORT_BIT	6
     92  1.1   tsubai #define			INTST0_BERR_BIT		5	/* N/A */
     93  1.1   tsubai #define			INTST0_TIMINT_BIT	4
     94  1.1   tsubai #define			INTST0_KBDINT_BIT	3
     95  1.1   tsubai #define			INTST0_MSINT_BIT	2
     96  1.1   tsubai #define			INTST0_CFLT_BIT		1
     97  1.1   tsubai #define			INTST0_CBSY_BIT		0
     98  1.1   tsubai 
     99  1.1   tsubai #define	INTST1	0xbfc80003
    100  1.1   tsubai #define		INTST1_BEEP	0x80
    101  1.1   tsubai #define		INTST1_SCC	0x40
    102  1.1   tsubai #define		INTST1_LANCE	0x20
    103  1.1   tsubai #define		INTST1_DMA	0x10
    104  1.1   tsubai #define		INTST1_SLOT1	0x08
    105  1.1   tsubai #define		INTST1_SLOT3	0x04
    106  1.1   tsubai #define		INTST1_EXT1	0x02
    107  1.1   tsubai #define		INTST1_EXT3	0x01
    108  1.1   tsubai #define			INTST1_BEEP_BIT		7
    109  1.1   tsubai #define			INTST1_SCC_BIT		6
    110  1.1   tsubai #define			INTST1_LANCE_BIT	5
    111  1.1   tsubai #define			INTST1_DMA_BIT		4
    112  1.1   tsubai #define			INTST1_SLOT1_BIT	3
    113  1.1   tsubai #define			INTST1_SLOT3_BIT	2
    114  1.1   tsubai #define			INTST1_EXT1_BIT		1
    115  1.1   tsubai #define			INTST1_EXT3_BIT		0
    116  1.1   tsubai 
    117  1.1   tsubai #define	INTCLR0	0xbfc80004
    118  1.1   tsubai #define		INTCLR0_PERR	0x80
    119  1.1   tsubai #define		INTCLR0_ABORT	0x40
    120  1.1   tsubai #define		INTCLR0_BERR	0x20
    121  1.1   tsubai #define		INTCLR0_TIMINT	0x10
    122  1.1   tsubai #define		INTCLR0_KBDINT	0x00	/* N/A */
    123  1.1   tsubai #define		INTCLR0_MSINT	0x00	/* N/A */
    124  1.1   tsubai #define		INTCLR0_CFLT	0x02
    125  1.1   tsubai #define		INTCLR0_CBSY	0x01
    126  1.1   tsubai 
    127  1.1   tsubai #define	INTCLR1	0xbfc80005
    128  1.1   tsubai #define		INTCLR1_BEEP	0x80
    129  1.1   tsubai #define		INTCLR1_SCC	0x00	/* N/A */
    130  1.1   tsubai #define		INTCLR1_LANCE	0x00	/* N/A */
    131  1.1   tsubai #define		INTCLR1_DMA	0x00	/* N/A */
    132  1.1   tsubai #define		INTCLR1_SLOT1	0x00	/* N/A */
    133  1.1   tsubai #define		INTCLR1_SLOT3	0x00	/* N/A */
    134  1.1   tsubai #define		INTCLR1_EXT1	0x00	/* N/A */
    135  1.1   tsubai #define		INTCLR1_EXT3	0x00	/* N/A */
    136  1.1   tsubai 
    137  1.1   tsubai #define	ITIMER		0xbfc80006
    138  1.1   tsubai #define	IOCLOCK		4915200
    139  1.1   tsubai 
    140  1.1   tsubai #define	DIP_SWITCH	0xbfe40000
    141  1.1   tsubai #define	IDROM		0xbfe80000
    142  1.1   tsubai 
    143  1.1   tsubai #define	DEBUG_PORT	0xbfcc0003
    144  1.1   tsubai #define		DP_READ		0x00
    145  1.1   tsubai #define		DP_WRITE	0xf0
    146  1.1   tsubai #define		DP_LED0		0x01
    147  1.1   tsubai #define		DP_LED1		0x02
    148  1.1   tsubai #define		DP_LED2		0x04
    149  1.1   tsubai #define		DP_LED3		0x08
    150  1.1   tsubai 
    151  1.1   tsubai 
    152  1.1   tsubai #define	LANCE_PORT	0xbff80000
    153  1.1   tsubai #define	LANCE_MEMORY	0xbffc0000
    154  1.1   tsubai #define	ETHER_ID	IDROM_PORT
    155  1.1   tsubai 
    156  1.1   tsubai #define	LANCE_PORT1	0xb8c30000	/* expansion lance #1 */
    157  1.1   tsubai #define	LANCE_MEMORY1	0xb8c20000
    158  1.1   tsubai #define	ETHER_ID1	0xb8c38000
    159  1.1   tsubai 
    160  1.1   tsubai #define	LANCE_PORT2	0xb8c70000	/* expansion lance #2 */
    161  1.1   tsubai #define	LANCE_MEMORY2	0xb8c60000
    162  1.1   tsubai #define	ETHER_ID2	0xb8c78000
    163  1.1   tsubai 
    164  1.1   tsubai #define	IDROM_PORT	0xbfe80000
    165  1.1   tsubai 
    166  1.1   tsubai #define	SCCPORT0B	0xbfec0000
    167  1.1   tsubai #define	SCCPORT0A	0xbfec0002
    168  1.1   tsubai #define SCCPORT1B	0xb8c40100
    169  1.1   tsubai #define SCCPORT1A	0xb8c40102
    170  1.1   tsubai #define SCCPORT2B	0xb8c40104
    171  1.1   tsubai #define SCCPORT2A	0xb8c40106
    172  1.1   tsubai #define SCCPORT3B	0xb8c40110
    173  1.1   tsubai #define SCCPORT3A	0xb8c40112
    174  1.1   tsubai #define SCCPORT4B	0xb8c40114
    175  1.1   tsubai #define SCCPORT4A	0xb8c40116
    176  1.1   tsubai 
    177  1.1   tsubai #define	SCC_STATUS0	0xbfcc0002
    178  1.1   tsubai #define	SCC_STATUS1	0xb8c40108
    179  1.1   tsubai #define	SCC_STATUS2	0xb8c40118
    180  1.1   tsubai 
    181  1.1   tsubai #define	SCCVECT		(0x1fcc0007 | MIPS_KSEG1_START)
    182  1.1   tsubai #define	SCC_RECV	2
    183  1.1   tsubai #define	SCC_XMIT	0
    184  1.1   tsubai #define	SCC_CTRL	3
    185  1.1   tsubai #define	SCC_STAT	1
    186  1.1   tsubai #define	SCC_INT_MASK	0x6
    187  1.1   tsubai 
    188  1.1   tsubai /*XXX: SHOULD BE FIX*/
    189  1.1   tsubai #define	KEYB_DATA	0xbfd00000	/* keyboard data port */
    190  1.1   tsubai #define KEYB_STAT	0xbfd00001	/* keyboard status port */
    191  1.1   tsubai #define	KEYB_INTE	INTEN0		/* keyboard interrupt enable */
    192  1.1   tsubai #define	KEYB_RESET	0xbfd00002	/* keyboard reset port*/
    193  1.1   tsubai #define	KEYB_INIT1	0xbfd00003	/* keyboard speed */
    194  1.1   tsubai #define	KEYB_INIT2	KEYB_INIT1	/* keyboard clock */
    195  1.1   tsubai #define	KEYB_BUZZ	0xbfd40001	/* keyboard buzzer (length) */
    196  1.1   tsubai #define	KEYB_BUZZF	0xbfd40000	/* keyboard buzzer frequency */
    197  1.1   tsubai #define	MOUSE_DATA	0xbfd00004	/* mouse data port */
    198  1.1   tsubai #define MOUSE_STAT	0xbfd00005	/* mouse status port */
    199  1.1   tsubai #define	MOUSE_INTE	INTEN0		/* mouse interrupt enable */
    200  1.1   tsubai #define	MOUSE_RESET	0xbfd00006	/* mouse reset port */
    201  1.1   tsubai #define	MOUSE_INIT1	0xbfd00007	/* mouse speed */
    202  1.1   tsubai #define	MOUSE_INIT2	MOUSE_INIT1	/* mouse clock */
    203  1.1   tsubai 
    204  1.1   tsubai #define	RX_MSINTE	0x04		/* Mouse Interrupt Enable */
    205  1.1   tsubai #define RX_KBINTE	0x08		/* Keyboard Intr. Enable */
    206  1.1   tsubai #define	RX_MSINT	0x04		/* Mouse Interrupted */
    207  1.1   tsubai #define	RX_KBINT	0x08		/* Keyboard Interrupted */
    208  1.1   tsubai #define	RX_MSBUF	0x01		/* Mouse data buffer Full */
    209  1.1   tsubai #define	RX_KBBUF	0x01		/* Keyboard data Full */
    210  1.1   tsubai #define	RX_MSRDY	0x02		/* Mouse data ready */
    211  1.1   tsubai #define	RX_KBRDY	0x02		/* Keyboard data ready */
    212  1.1   tsubai /*XXX: SHOULD BE FIX*/
    213  1.1   tsubai 
    214  1.1   tsubai #define	ABEINT_BADDR	0xbfdc0038
    215  1.1   tsubai 
    216  1.9  tsutsui /*----------------------------------------------------------------------
    217  1.9  tsutsui  *	news5000
    218  1.9  tsutsui  *----------------------------------------------------------------------*/
    219  1.3   tsubai #define	NEWS5000_DIP_SWITCH	0xbf3d0000
    220  1.3   tsubai #define	NEWS5000_IDROM		0xbf3c0000
    221  1.3   tsubai 
    222  1.3   tsubai #define	NEWS5000_TIMER0		0xbf800000
    223  1.5     onoe #define	NEWS5000_FREERUN	0xbf840000
    224  1.3   tsubai #define	NEWS5000_NVRAM		0xbf880000
    225  1.3   tsubai #define	NEWS5000_NVRAM_SIZE	0x07f8
    226  1.4   tsubai #define	NEWS5000_RTC_PORT	0xbf881fe0
    227  1.3   tsubai 
    228  1.3   tsubai #define	NEWS5000_INTCLR0	0xbf4e0000
    229  1.3   tsubai #define	NEWS5000_INTCLR1	0xbf4e0004
    230  1.3   tsubai #define	NEWS5000_INTCLR2	0xbf4e0008
    231  1.3   tsubai #define	NEWS5000_INTCLR3	0xbf4e000c
    232  1.3   tsubai #define	NEWS5000_INTCLR4	0xbf4e0010
    233  1.3   tsubai #define	NEWS5000_INTCLR5	0xbf4e0014
    234  1.3   tsubai 
    235  1.4   tsubai #define	NEWS5000_INTEN0		0xbfa00000
    236  1.4   tsubai #define	NEWS5000_INTEN1		0xbfa00004
    237  1.4   tsubai #define	NEWS5000_INTEN2		0xbfa00008
    238  1.4   tsubai #define	NEWS5000_INTEN3		0xbfa0000c
    239  1.4   tsubai #define	NEWS5000_INTEN4		0xbfa00010
    240  1.4   tsubai #define	NEWS5000_INTEN5		0xbfa00014
    241  1.4   tsubai 
    242  1.4   tsubai #define	NEWS5000_INTST0		0xbfa00020
    243  1.4   tsubai #define	NEWS5000_INTST1		0xbfa00024
    244  1.4   tsubai #define	NEWS5000_INTST2		0xbfa00028
    245  1.4   tsubai #define	NEWS5000_INTST3		0xbfa0002c
    246  1.4   tsubai #define	NEWS5000_INTST4		0xbfa00030
    247  1.4   tsubai #define	NEWS5000_INTST5		0xbfa00034
    248  1.3   tsubai 
    249  1.3   tsubai /*
    250  1.3   tsubai  * level0 intr (INTMASK0/INTSTAT0)
    251  1.3   tsubai  */
    252  1.4   tsubai #define	NEWS5000_INT0_DMAC	0x01
    253  1.4   tsubai #define	NEWS5000_INT0_SONIC	0x02
    254  1.4   tsubai #define	NEWS5000_INT0_FDC	0x10
    255  1.3   tsubai 
    256  1.3   tsubai /*
    257  1.3   tsubai  * level1 intr (INTMASK1/INTSTAT1)
    258  1.3   tsubai  */
    259  1.4   tsubai #define	NEWS5000_INT1_KBD	0x01
    260  1.4   tsubai #define	NEWS5000_INT1_SCC	0x02
    261  1.4   tsubai #define	NEWS5000_INT1_AUDIO0	0x04
    262  1.4   tsubai #define	NEWS5000_INT1_AUDIO1	0x08
    263  1.4   tsubai #define	NEWS5000_INT1_PARALLEL	0x20
    264  1.4   tsubai #define	NEWS5000_INT1_FB	0x80
    265  1.3   tsubai 
    266  1.3   tsubai /*
    267  1.3   tsubai  * level2 intr (INTMASK2/INTSTAT2)
    268  1.3   tsubai  */
    269  1.4   tsubai #define	NEWS5000_INT2_TIMER0	0x01
    270  1.4   tsubai #define	NEWS5000_INT2_TIMER1	0x02
    271  1.3   tsubai 
    272  1.5     onoe /*
    273  1.5     onoe  * level4 intr (INTMASK4/INTSTAT4)
    274  1.5     onoe  */
    275  1.5     onoe #define	NEWS5000_INT4_APBUS	0x01
    276  1.5     onoe 
    277  1.4   tsubai #define	NEWS5000_WBFLUSH	0xbf520004
    278  1.3   tsubai 
    279  1.4   tsubai #define	NEWS5000_LED_POWER	0xbf3f0000
    280  1.4   tsubai #define	NEWS5000_LED_DISK	0xbf3f0004
    281  1.4   tsubai #define	NEWS5000_LED_FLOPPY	0xbf3f0008
    282  1.4   tsubai #define	NEWS5000_LED_SEC	0xbf3f000c
    283  1.4   tsubai #define	NEWS5000_LED_NET	0xbf3f0010
    284  1.4   tsubai #define	NEWS5000_LED_CD		0xbf3f0014
    285  1.4   tsubai 
    286  1.5     onoe #define	NEWS5000_APBUS_INTMSK	0xb4c0000c	/* interrupt mask */
    287  1.5     onoe #define		NEWS5000_APBUS_INT_DMAADDR	0x0100
    288  1.5     onoe #define		NEWS5000_APBUS_INT_RDTIMEO	0x0004
    289  1.5     onoe #define		NEWS5000_APBUS_INT_WRTIMEO	0x0001
    290  1.5     onoe #define	NEWS5000_APBUS_INTST	0xb4c00014	/* interrupt status */
    291  1.5     onoe #define	NEWS5000_APBUS_BER_A	0xb4c0001c	/* Bus error address */
    292  1.5     onoe #define	NEWS5000_APBUS_CTRL	0xb4c00034	/* configuration control */
    293  1.5     onoe #define	NEWS5000_APBUS_DER_A	0xb400005c	/* DMA error address */
    294  1.5     onoe #define	NEWS5000_APBUS_DER_S	0xb4c0006c	/* DMA error slot */
    295  1.5     onoe #define	NEWS5000_APBUS_DMA	0xb4c00084	/* unmapped DMA coherency */
    296  1.6     onoe 
    297  1.6     onoe #define	NEWS5000_APBUS_DMAMAP	0xb4c20000	/* DMA mapping RAM */
    298  1.6     onoe #define		NEWS5000_APBUS_MAPSIZE	0x20000	/* size of mapping RAM */
    299  1.6     onoe #define		NEWS5000_APBUS_MAPENT	0x8	/* size of mapping entry */
    300  1.6     onoe #define		NEWS5000_APBUS_MAP_VALID	0x80000000
    301  1.6     onoe #define		NEWS5000_APBUS_MAP_COHERENT	0x40000000
    302  1.3   tsubai 
    303  1.4   tsubai #define	NEWS5000_SCCPORT0A	0xbe950000
    304  1.3   tsubai 
    305  1.9  tsutsui /*----------------------------------------------------------------------
    306  1.9  tsutsui  *	news4000
    307  1.9  tsutsui  *----------------------------------------------------------------------*/
    308  1.9  tsutsui #define	NEWS4000_IDROM_STATUS	0xbf880018
    309  1.9  tsutsui #define	NEWS4000_IDROM_DATA	0xbf88001c
    310  1.9  tsutsui 
    311  1.9  tsutsui #define	NEWS4000_TIMERCTL	0xbf90000c
    312  1.9  tsutsui #define	NEWS4000_TIMER		0xbf900014
    313  1.9  tsutsui 
    314  1.9  tsutsui #define	NEWS4000_NVRAM		0xbfb10000
    315  1.9  tsutsui #define	NEWS4000_NVRAM_SIZE	0x7f8
    316  1.9  tsutsui #define	NEWS4000_RTC_PORT	0xbfb17fe0
    317  1.9  tsutsui 
    318  1.9  tsutsui #define	NEWS4000_INTEN0		0xb6000010
    319  1.9  tsutsui #define	NEWS4000_INTEN1		0xb6000014
    320  1.9  tsutsui #define	NEWS4000_INTEN2		0xb6000018
    321  1.9  tsutsui #define	NEWS4000_INTEN3		0xb600001c
    322  1.9  tsutsui #define	NEWS4000_INTEN4		0xb6000020
    323  1.9  tsutsui #define	NEWS4000_INTEN5		0xb6000024
    324  1.9  tsutsui 
    325  1.9  tsutsui #define	NEWS4000_INTST0		0xb6000030
    326  1.9  tsutsui #define	NEWS4000_INTST1		0xb6000034
    327  1.9  tsutsui #define	NEWS4000_INTST2		0xbf900010
    328  1.9  tsutsui #define	NEWS4000_INTST3		0xb600003c
    329  1.9  tsutsui #define	NEWS4000_INTST4		0xb6000040
    330  1.9  tsutsui #define	NEWS4000_INTST5		0xb6000044
    331  1.9  tsutsui 
    332  1.9  tsutsui /*
    333  1.9  tsutsui  * level0 intr (INTMASK0/INTSTAT0)
    334  1.9  tsutsui  */
    335  1.9  tsutsui #define	NEWS4000_INT0_SONIC	0x0800
    336  1.9  tsutsui 
    337  1.9  tsutsui /*
    338  1.9  tsutsui  * level2 intr (INTMASK2/INTSTAT2)
    339  1.9  tsutsui  */
    340  1.9  tsutsui #define	NEWS4000_INT2_TIMER	0x01
    341  1.9  tsutsui 
    342  1.9  tsutsui #define	NEWS4000_WBFLUSH	0xbf880000
    343  1.9  tsutsui 
    344  1.9  tsutsui #define	NEWS4000_LED		0xbfb30004
    345  1.9  tsutsui #define		NEWS4000_LED0		0x01	/* POWER LED */
    346  1.9  tsutsui #define		NEWS4000_LED1		0x02	/* NETWORK LED */
    347  1.9  tsutsui #define		NEWS4000_LED2		0x04	/* FLOPPY LED */
    348  1.9  tsutsui #define		NEWS4000_LED3		0x08	/* DISK LED */
    349  1.9  tsutsui 
    350  1.9  tsutsui #define	NEWS4000_SONIC_MEMORY	0xbf3a0000
    351  1.9  tsutsui #define	NEWS4000_SONIC_BUFFER	0xbf380000
    352  1.9  tsutsui 
    353  1.9  tsutsui #define	NEWS4000_SCCPORT0A	0xbfb00008
    354  1.9  tsutsui 
    355  1.3   tsubai #endif /* !__MACHINE_ADRSMAP__ */
    356