adrsmap.h revision 1.3
1 /* $NetBSD: adrsmap.h,v 1.3 1999/12/22 05:55:26 tsubai Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: $Hdr: adrsmap.h,v 4.300 91/06/09 06:34:29 root Rel41 $ SONY 39 * 40 * @(#)adrsmap.h 8.1 (Berkeley) 6/11/93 41 */ 42 43 /* 44 * adrsmap.h 45 * 46 * Define all hardware address map. 47 */ 48 49 #ifndef __MACHINE_ADRSMAP__ 50 #define __MACHINE_ADRSMAP__ 51 52 /*---------------------------------------------------------------------- 53 * news3400 54 *----------------------------------------------------------------------*/ 55 /* 56 * timer 57 */ 58 #define RTC_PORT 0xbff407f8 59 #define DATA_PORT 0xbff407f9 60 61 #ifdef notdef 62 #define EN_ITIMER 0xb8000004 /*XXX:???*/ 63 #endif 64 65 #define INTEN0 0xbfc80000 66 #define INTEN0_PERR 0x80 67 #define INTEN0_ABORT 0x40 68 #define INTEN0_BERR 0x20 69 #define INTEN0_TIMINT 0x10 70 #define INTEN0_KBDINT 0x08 71 #define INTEN0_MSINT 0x04 72 #define INTEN0_CFLT 0x02 73 #define INTEN0_CBSY 0x01 74 75 #define INTEN1 0xbfc80001 76 #define INTEN1_BEEP 0x80 77 #define INTEN1_SCC 0x40 78 #define INTEN1_LANCE 0x20 79 #define INTEN1_DMA 0x10 80 #define INTEN1_SLOT1 0x08 81 #define INTEN1_SLOT3 0x04 82 #define INTEN1_EXT1 0x02 83 #define INTEN1_EXT3 0x01 84 85 #define INTST0 0xbfc80002 86 #define INTST0_PERR 0x80 87 #define INTST0_ABORT 0x40 88 #define INTST0_BERR 0x00 /* N/A */ 89 #define INTST0_TIMINT 0x10 90 #define INTST0_KBDINT 0x08 91 #define INTST0_MSINT 0x04 92 #define INTST0_CFLT 0x02 93 #define INTST0_CBSY 0x01 94 #define INTST0_PERR_BIT 7 95 #define INTST0_ABORT_BIT 6 96 #define INTST0_BERR_BIT 5 /* N/A */ 97 #define INTST0_TIMINT_BIT 4 98 #define INTST0_KBDINT_BIT 3 99 #define INTST0_MSINT_BIT 2 100 #define INTST0_CFLT_BIT 1 101 #define INTST0_CBSY_BIT 0 102 103 #define INTST1 0xbfc80003 104 #define INTST1_BEEP 0x80 105 #define INTST1_SCC 0x40 106 #define INTST1_LANCE 0x20 107 #define INTST1_DMA 0x10 108 #define INTST1_SLOT1 0x08 109 #define INTST1_SLOT3 0x04 110 #define INTST1_EXT1 0x02 111 #define INTST1_EXT3 0x01 112 #define INTST1_BEEP_BIT 7 113 #define INTST1_SCC_BIT 6 114 #define INTST1_LANCE_BIT 5 115 #define INTST1_DMA_BIT 4 116 #define INTST1_SLOT1_BIT 3 117 #define INTST1_SLOT3_BIT 2 118 #define INTST1_EXT1_BIT 1 119 #define INTST1_EXT3_BIT 0 120 121 #define INTCLR0 0xbfc80004 122 #define INTCLR0_PERR 0x80 123 #define INTCLR0_ABORT 0x40 124 #define INTCLR0_BERR 0x20 125 #define INTCLR0_TIMINT 0x10 126 #define INTCLR0_KBDINT 0x00 /* N/A */ 127 #define INTCLR0_MSINT 0x00 /* N/A */ 128 #define INTCLR0_CFLT 0x02 129 #define INTCLR0_CBSY 0x01 130 131 #define INTCLR1 0xbfc80005 132 #define INTCLR1_BEEP 0x80 133 #define INTCLR1_SCC 0x00 /* N/A */ 134 #define INTCLR1_LANCE 0x00 /* N/A */ 135 #define INTCLR1_DMA 0x00 /* N/A */ 136 #define INTCLR1_SLOT1 0x00 /* N/A */ 137 #define INTCLR1_SLOT3 0x00 /* N/A */ 138 #define INTCLR1_EXT1 0x00 /* N/A */ 139 #define INTCLR1_EXT3 0x00 /* N/A */ 140 141 #define ITIMER 0xbfc80006 142 #define IOCLOCK 4915200 143 144 #define DIP_SWITCH 0xbfe40000 145 #define IDROM 0xbfe80000 146 147 #define DEBUG_PORT 0xbfcc0003 148 #define DP_READ 0x00 149 #define DP_WRITE 0xf0 150 #define DP_LED0 0x01 151 #define DP_LED1 0x02 152 #define DP_LED2 0x04 153 #define DP_LED3 0x08 154 155 156 #define LANCE_PORT 0xbff80000 157 #define LANCE_MEMORY 0xbffc0000 158 #define ETHER_ID IDROM_PORT 159 160 #define LANCE_PORT1 0xb8c30000 /* expansion lance #1 */ 161 #define LANCE_MEMORY1 0xb8c20000 162 #define ETHER_ID1 0xb8c38000 163 164 #define LANCE_PORT2 0xb8c70000 /* expansion lance #2 */ 165 #define LANCE_MEMORY2 0xb8c60000 166 #define ETHER_ID2 0xb8c78000 167 168 #define IDROM_PORT 0xbfe80000 169 170 #define SCCPORT0B 0xbfec0000 171 #define SCCPORT0A 0xbfec0002 172 #define SCCPORT1B 0xb8c40100 173 #define SCCPORT1A 0xb8c40102 174 #define SCCPORT2B 0xb8c40104 175 #define SCCPORT2A 0xb8c40106 176 #define SCCPORT3B 0xb8c40110 177 #define SCCPORT3A 0xb8c40112 178 #define SCCPORT4B 0xb8c40114 179 #define SCCPORT4A 0xb8c40116 180 181 #define SCC_STATUS0 0xbfcc0002 182 #define SCC_STATUS1 0xb8c40108 183 #define SCC_STATUS2 0xb8c40118 184 185 #define SCCVECT (0x1fcc0007 | MIPS_KSEG1_START) 186 #define SCC_RECV 2 187 #define SCC_XMIT 0 188 #define SCC_CTRL 3 189 #define SCC_STAT 1 190 #define SCC_INT_MASK 0x6 191 192 /*XXX: SHOULD BE FIX*/ 193 #define KEYB_DATA 0xbfd00000 /* keyboard data port */ 194 #define KEYB_STAT 0xbfd00001 /* keyboard status port */ 195 #define KEYB_INTE INTEN0 /* keyboard interrupt enable */ 196 #define KEYB_RESET 0xbfd00002 /* keyboard reset port*/ 197 #define KEYB_INIT1 0xbfd00003 /* keyboard speed */ 198 #define KEYB_INIT2 KEYB_INIT1 /* keyboard clock */ 199 #define KEYB_BUZZ 0xbfd40001 /* keyboard buzzer (length) */ 200 #define KEYB_BUZZF 0xbfd40000 /* keyboard buzzer frequency */ 201 #define MOUSE_DATA 0xbfd00004 /* mouse data port */ 202 #define MOUSE_STAT 0xbfd00005 /* mouse status port */ 203 #define MOUSE_INTE INTEN0 /* mouse interrupt enable */ 204 #define MOUSE_RESET 0xbfd00006 /* mouse reset port */ 205 #define MOUSE_INIT1 0xbfd00007 /* mouse speed */ 206 #define MOUSE_INIT2 MOUSE_INIT1 /* mouse clock */ 207 208 #define RX_MSINTE 0x04 /* Mouse Interrupt Enable */ 209 #define RX_KBINTE 0x08 /* Keyboard Intr. Enable */ 210 #define RX_MSINT 0x04 /* Mouse Interrupted */ 211 #define RX_KBINT 0x08 /* Keyboard Interrupted */ 212 #define RX_MSBUF 0x01 /* Mouse data buffer Full */ 213 #define RX_KBBUF 0x01 /* Keyboard data Full */ 214 #define RX_MSRDY 0x02 /* Mouse data ready */ 215 #define RX_KBRDY 0x02 /* Keyboard data ready */ 216 /*XXX: SHOULD BE FIX*/ 217 218 #define ABEINT_BADDR 0xbfdc0038 219 220 #define NEWS5000_DIP_SWITCH 0xbf3d0000 221 #define NEWS5000_IDROM 0xbf3c0000 222 223 #define NEWS5000_TIMER0 0xbf800000 224 #define NEWS5000_TIMER1 0xbf800004 225 #define NEWS5000_TIMER1_PERIOD 0xbf80000c 226 #define NEWS5000_TIMER_COUNTER 0xbf840000 227 #define NEWS5000_TIMER_LOAD 0xbf840004 228 #define NEWS5000_NVRAM 0xbf880000 229 #define NEWS5000_NVRAM_SIZE 0x07f8 230 #define NEWS5000_RTC_ADDR 0xbf881fe0 231 232 #define NEWS5000_INTCLR0 0xbf4e0000 233 #define NEWS5000_INTCLR1 0xbf4e0004 234 #define NEWS5000_INTCLR2 0xbf4e0008 235 #define NEWS5000_INTCLR3 0xbf4e000c 236 #define NEWS5000_INTCLR4 0xbf4e0010 237 #define NEWS5000_INTCLR5 0xbf4e0014 238 #define NEWS5000_INTCLRNMI 0xbf4e0018 239 240 #define NEWS5000_INTMASK0 0xbfa00000 241 #define NEWS5000_INTMASK1 0xbfa00004 242 #define NEWS5000_INTMASK2 0xbfa00008 243 #define NEWS5000_INTMASK3 0xbfa0000c 244 #define NEWS5000_INTMASK4 0xbfa00010 245 #define NEWS5000_INTMASK5 0xbfa00014 246 #define NEWS5000_INTMASKNMI 0xbfa00018 247 248 #define NEWS5000_INTSTAT0 0xbfa00020 249 #define NEWS5000_INTSTAT1 0xbfa00024 250 #define NEWS5000_INTSTAT2 0xbfa00028 251 #define NEWS5000_INTSTAT3 0xbfa0002c 252 #define NEWS5000_INTSTAT4 0xbfa00030 253 #define NEWS5000_INTSTAT5 0xbfa00034 254 #define NEWS5000_INTSTATNMI 0xbfa00038 255 256 #define NEWS5000_INTSLOT0 0x00000100 257 #define NEWS5000_INTSLOT1 0x00000200 258 #define NEWS5000_INTSLOT2 0x00000400 259 #define NEWS5000_INTSLOT3 0x00000800 260 #define NEWS5000_INTSLOT4 0x00001000 261 #define NEWS5000_INTSLOT5 0x00002000 262 #define NEWS5000_INTSLOT_ALL 0x00003f00 263 264 265 /* 266 * level0 intr (INTMASK0/INTSTAT0) 267 */ 268 #define NEWS5000_INT0_DMAC 0x0001 269 #define NEWS5000_INT0_SONIC 0x0002 270 #define NEWS5000_INT0_FIFO0 0x0004 271 #define NEWS5000_INT0_FIFO1 0x0008 272 #define NEWS5000_INT0_FDC 0x0010 273 #define NEWS5000_INT0_ALL (NEWS5000_INT0_DMAC|NEWS5000_INT0_SONIC|NEWS5000_INT0_FIFO0|NEWS5000_INT0_FIFO1|NEWS5000_INT0_FDC) 274 275 /* 276 * level1 intr (INTMASK1/INTSTAT1) 277 */ 278 #define NEWS5000_INT1_KBD 0x0001 279 #define NEWS5000_INT1_SERIAL 0x0002 280 #define NEWS5000_INT1_AUDIO0 0x0004 281 #define NEWS5000_INT1_AUDIO1 0x0008 282 #define NEWS5000_INT1_PARALLEL 0x0020 283 #define NEWS5000_INT1_FB 0x0080 284 #define NEWS5000_INT1_ALL (NEWS5000_INT1_KBD|NEWS5000_INT1_SERIAL|NEWS5000_INT1_AUDIO0|NEWS5000_INT1_AUDIO1|NEWS5000_INT1_PARALLEL|NEWS5000_INT1_FB) 285 286 /* 287 * level2 intr (INTMASK2/INTSTAT2) 288 */ 289 #define NEWS5000_INT2_TIMER0 0x0001 290 #define NEWS5000_INT2_TIMER1 0x0002 291 #define NEWS5000_INT2_ALL (NEWS5000_INT2_TIMER0|NEWS5000_INT2_TIMER1) 292 293 /* 294 * level4 intr (INTMASK4/INTSTAT4) 295 */ 296 #define NEWS5000_INT4_ABIF 0x0001 297 #define NEWS5000_INT4_WBERR NEWS5000_INT4_ABIF 298 #define NEWS5000_INT4_MFBIF 0x0002 299 #define NEWS5000_INT4_SBIF 0x0004 300 #define NEWS5000_INT4_ALL (NEWS5000_INT4_ABIF|NEWS5000_INT4_MFBIF|NEWS5000_INT4_SBIF) 301 302 /* 303 * level5 intr (INTMASK5/INTSTAT5) 304 */ 305 #define NEWS5000_INT5_ABIF 0x0001 306 #define NEWS5000_INT5_MBIF 0x0002 307 #define NEWS5000_INT5_SBIF 0x0004 308 #define NEWS5000_INT5_POWER 0x0008 309 #define NEWS5000_INT5_TEMP 0x0010 310 #define NEWS5000_INT5_ABORT 0x0020 311 #define NEWS5000_INT5_EXTSENSE NEWS5000_INT5_ABORT 312 #define NEWS5000_INT5_ALL (NEWS5000_INT5_ABIF|NEWS5000_INT5_MBIF|NEWS5000_INT5_SBIF|NEWS5000_INT5_POWER|NEWS5000_INT5_TEMP|NEWS5000_INT5_ABORT) 313 314 /* 315 * NMI intr (INTMASKNMI/INTSTATNMI) 316 */ 317 #define NEWS5000_INTNMI_ABORT 0x0001 318 #define NEWS5000_INTNMI_ALL (NEWS5000_INTNMI_ABORT) 319 320 321 #define NEWS5000_WB 0xbf520004 /* I/O write buffer control */ 322 323 324 325 #define NEWS5000_LED0 0xbf3f0000 /* POWER LED */ 326 #define NEWS5000_LED1 0xbf3f0004 /* DISK LED */ 327 #define NEWS5000_LED2 0xbf3f0008 /* FLOPPY LED */ 328 #define NEWS5000_LED3 0xbf3f000c /* SECURITY LED */ 329 #define NEWS5000_LED4 0xbf3f0010 /* NETWORK LED */ 330 #define NEWS5000_LED5 0xbf3f0014 /* CDROM LED */ 331 332 333 334 #define NEWS5000_APBUS_INTMASK 0xb4c0000c 335 #define NEWS5000_APBUS_INTSTAT 0xb4c00014 336 #define NEWS5000_APBUS_CONFIG 0xb4c00034 337 #define NEWS5000_APBUS_DUMCOH 0xb4c00084 338 #define NEWS5000_APBUS_DEVICE_DMAC3 0x80000000 /* DMAC3 */ 339 #define NEWS5000_APBUS_DEVICE_SONIC 0x40000000 /* SONIC */ 340 #define NEWS5000_APBUS_DEVICE_SLOT6 0x00000020 /* slot #6 */ 341 #define NEWS5000_APBUS_DEVICE_SLOT5 0x00000010 /* slot #5 */ 342 #define NEWS5000_APBUS_DEVICE_SLOT4 0x00000008 /* slot #4 */ 343 #define NEWS5000_APBUS_DEVICE_SLOT3 0x00000004 /* slot #3 */ 344 #define NEWS5000_APBUS_DEVICE_SLOT2 0x00000002 /* slot #2 */ 345 #define NEWS5000_APBUS_DEVICE_SLOT1 0x00000001 /* slot #1 */ 346 #define NEWS5000_APBUS_DEVICE_ALLSLOT 0x0000003f /* slot #1-#6 */ 347 348 349 350 #define NEWS5000_INTAPBUS_DMADOUBLE 0x8000 /* DMA double error */ 351 #define NEWS5000_INTAPBUS_DMAPARITY 0x0200 /* DMA parity error */ 352 #define NEWS5000_INTAPBUS_DMAADDRESS 0x0100 /* DMA address error */ 353 #define NEWS5000_INTAPBUS_IODOUBLE 0x0080 /* I/O access double bus error */ 354 #define NEWS5000_INTAPBUS_IOPARITY 0x0010 /* I/O read parity error */ 355 #define NEWS5000_INTAPBUS_RDIOERR 0x0008 /* I/O read ioerr */ 356 #define NEWS5000_INTAPBUS_RDTIMEO 0x0004 /* I/O read time-out error */ 357 #define NEWS5000_INTAPBUS_WRIOERR 0x0002 /* I/O write ioerr */ 358 #define NEWS5000_INTAPBUS_WRTIMEO 0x0001 /* I/O write time-out error */ 359 #define NEWS5000_INTAPBUS_ALL (NEWS5000_INTAPBUS_DMADOUBLE|\ 360 NEWS5000_INTAPBUS_DMAPARITY|\ 361 NEWS5000_INTAPBUS_DMAADDRESS|\ 362 NEWS5000_INTAPBUS_IODOUBLE|\ 363 NEWS5000_INTAPBUS_IOPARITY|\ 364 NEWS5000_INTAPBUS_RDIOERR|\ 365 NEWS5000_INTAPBUS_RDTIMEO|\ 366 NEWS5000_INTAPBUS_WRIOERR|\ 367 NEWS5000_INTAPBUS_WRTIMEO) 368 369 #define NEWS5000_SCCPORT0A 0xbe950000 370 371 #endif /* !__MACHINE_ADRSMAP__ */ 372
Indexes created Wed Oct 22 13:09:56 GMT 2025