intr.h revision 1.2 1 1.2 tsubai /* $NetBSD: intr.h,v 1.2 1998/08/26 12:07:21 tsubai Exp $ */
2 1.1 tsubai
3 1.1 tsubai /*
4 1.1 tsubai * Copyright (c) 1998 Jonathan Stone. All rights reserved.
5 1.1 tsubai *
6 1.1 tsubai * Redistribution and use in source and binary forms, with or without
7 1.1 tsubai * modification, are permitted provided that the following conditions
8 1.1 tsubai * are met:
9 1.1 tsubai * 1. Redistributions of source code must retain the above copyright
10 1.1 tsubai * notice, this list of conditions and the following disclaimer.
11 1.1 tsubai * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 tsubai * notice, this list of conditions and the following disclaimer in the
13 1.1 tsubai * documentation and/or other materials provided with the distribution.
14 1.1 tsubai * 3. All advertising materials mentioning features or use of this software
15 1.1 tsubai * must display the following acknowledgement:
16 1.1 tsubai * This product includes software developed by Jonathan Stone for
17 1.1 tsubai * the NetBSD Project.
18 1.1 tsubai * 4. The name of the author may not be used to endorse or promote products
19 1.1 tsubai * derived from this software without specific prior written permission.
20 1.1 tsubai *
21 1.1 tsubai * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 1.1 tsubai * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 1.1 tsubai * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 1.1 tsubai * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 1.1 tsubai * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 1.1 tsubai * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 1.1 tsubai * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 1.1 tsubai * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 1.1 tsubai * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 1.1 tsubai * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 1.1 tsubai */
32 1.1 tsubai
33 1.1 tsubai #ifndef _MACHINE_INTR_H_
34 1.1 tsubai #define _MACHINE_INTR_H_
35 1.1 tsubai
36 1.1 tsubai #define IPL_NONE 0 /* disable only this interrupt */
37 1.1 tsubai #define IPL_BIO 1 /* disable block I/O interrupts */
38 1.1 tsubai #define IPL_NET 2 /* disable network interrupts */
39 1.1 tsubai #define IPL_TTY 3 /* disable terminal interrupts */
40 1.1 tsubai #define IPL_CLOCK 4 /* disable clock interrupts */
41 1.1 tsubai #define IPL_STATCLOCK 5 /* disable profiling interrupts */
42 1.1 tsubai #define IPL_SERIAL 6 /* disable serial hardware interrupts */
43 1.2 tsubai #define IPL_HIGH 7 /* disable all interrupts */
44 1.2 tsubai
45 1.2 tsubai #ifndef _LOCORE
46 1.2 tsubai
47 1.2 tsubai #define splbio cpu_spl0
48 1.2 tsubai #define splnet cpu_spl1
49 1.2 tsubai #define spltty cpu_spl1
50 1.2 tsubai #define splimp cpu_spl1
51 1.2 tsubai #define splclock cpu_spl2
52 1.2 tsubai #define splstatclock cpu_spl2
53 1.2 tsubai
54 1.2 tsubai extern void setsoftnet __P((void)), clearsoftnet __P((void));
55 1.2 tsubai extern void setsoftclock __P((void)), clearsoftclock __P((void));
56 1.2 tsubai
57 1.2 tsubai extern int splhigh __P((void));
58 1.2 tsubai extern int splclock __P((void));
59 1.2 tsubai extern int splstatclock __P((void));
60 1.2 tsubai extern int splimp __P((void));
61 1.2 tsubai extern int spltty __P((void));
62 1.2 tsubai extern int splnet __P((void));
63 1.2 tsubai extern int splbio __P((void));
64 1.2 tsubai extern int splsoftnet __P((void));
65 1.2 tsubai extern int splsoftclock __P((void));
66 1.2 tsubai extern int spl0 __P((void));
67 1.2 tsubai extern void splx __P((int));
68 1.2 tsubai
69 1.1 tsubai
70 1.1 tsubai /*
71 1.1 tsubai * Index into intrcnt[], which is defined in locore
72 1.1 tsubai */
73 1.2 tsubai #define SOFTCLOCK_INTR 0
74 1.2 tsubai #define SOFTNET_INTR 1
75 1.2 tsubai #define SERIAL0_INTR 2
76 1.2 tsubai #define SERIAL1_INTR 3
77 1.2 tsubai #define SERIAL2_INTR 4
78 1.2 tsubai #define LANCE_INTR 5
79 1.2 tsubai #define SCSI_INTR 6
80 1.2 tsubai #define ERROR_INTR 7
81 1.2 tsubai #define HARDCLOCK_INTR 8
82 1.2 tsubai #define FPU_INTR 9
83 1.2 tsubai #define SLOT1_INTR 10
84 1.2 tsubai #define SLOT2_INTR 11
85 1.2 tsubai #define SLOT3_INTR 12
86 1.2 tsubai #define FLOPPY_INTR 13
87 1.2 tsubai #define STRAY_INTR 14
88 1.1 tsubai
89 1.2 tsubai extern u_int intrcnt[];
90 1.1 tsubai
91 1.2 tsubai /* handle i/o device interrupts */
92 1.2 tsubai extern int (*mips_hardware_intr) __P((u_int, u_int, u_int, u_int));
93 1.2 tsubai extern int news3400_intr __P((u_int, u_int, u_int, u_int));
94 1.1 tsubai
95 1.2 tsubai #endif /* !_LOCORE */
96 1.1 tsubai #endif /* _MACHINE_INTR_H_ */
97