intr.h revision 1.3.2.1
1 1.3.2.1 wrstuden /* $NetBSD: intr.h,v 1.3.2.1 1999/12/27 18:33:09 wrstuden Exp $ */ 2 1.1 tsubai 3 1.1 tsubai /* 4 1.1 tsubai * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 1.1 tsubai * 6 1.1 tsubai * Redistribution and use in source and binary forms, with or without 7 1.1 tsubai * modification, are permitted provided that the following conditions 8 1.1 tsubai * are met: 9 1.1 tsubai * 1. Redistributions of source code must retain the above copyright 10 1.1 tsubai * notice, this list of conditions and the following disclaimer. 11 1.1 tsubai * 2. Redistributions in binary form must reproduce the above copyright 12 1.1 tsubai * notice, this list of conditions and the following disclaimer in the 13 1.1 tsubai * documentation and/or other materials provided with the distribution. 14 1.1 tsubai * 3. All advertising materials mentioning features or use of this software 15 1.1 tsubai * must display the following acknowledgement: 16 1.1 tsubai * This product includes software developed by Jonathan Stone for 17 1.1 tsubai * the NetBSD Project. 18 1.1 tsubai * 4. The name of the author may not be used to endorse or promote products 19 1.1 tsubai * derived from this software without specific prior written permission. 20 1.1 tsubai * 21 1.1 tsubai * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 1.1 tsubai * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 1.1 tsubai * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 1.1 tsubai * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 1.1 tsubai * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 1.1 tsubai * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 1.1 tsubai * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 1.1 tsubai * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 1.1 tsubai * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 1.1 tsubai * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 1.1 tsubai */ 32 1.1 tsubai 33 1.1 tsubai #ifndef _MACHINE_INTR_H_ 34 1.1 tsubai #define _MACHINE_INTR_H_ 35 1.1 tsubai 36 1.3.2.1 wrstuden #define IPL_NONE 0 /* disable only this interrupt */ 37 1.3.2.1 wrstuden #define IPL_BIO 1 /* disable block I/O interrupts */ 38 1.3.2.1 wrstuden #define IPL_NET 2 /* disable network interrupts */ 39 1.3.2.1 wrstuden #define IPL_TTY 3 /* disable terminal interrupts */ 40 1.3.2.1 wrstuden #define IPL_CLOCK 4 /* disable clock interrupts */ 41 1.3.2.1 wrstuden #define IPL_STATCLOCK 5 /* disable profiling interrupts */ 42 1.3.2.1 wrstuden #define IPL_SERIAL 6 /* disable serial hardware interrupts */ 43 1.3.2.1 wrstuden #define IPL_HIGH 7 /* disable all interrupts */ 44 1.2 tsubai 45 1.3.2.1 wrstuden #ifdef _KERNEL 46 1.2 tsubai #ifndef _LOCORE 47 1.3.2.1 wrstuden #include <mips/cpuregs.h> 48 1.2 tsubai 49 1.3.2.1 wrstuden extern int _splraise __P((int)); 50 1.3.2.1 wrstuden extern int _spllower __P((int)); 51 1.3.2.1 wrstuden extern int _splset __P((int)); 52 1.3.2.1 wrstuden extern int _splget __P((void)); 53 1.3.2.1 wrstuden extern void _splnone __P((void)); 54 1.3.2.1 wrstuden extern void _setsoftintr __P((int)); 55 1.3.2.1 wrstuden extern void _clrsoftintr __P((int)); 56 1.3.2.1 wrstuden 57 1.3.2.1 wrstuden #define setsoftclock() _setsoftintr(MIPS_SOFT_INT_MASK_0) 58 1.3.2.1 wrstuden #define setsoftnet() _setsoftintr(MIPS_SOFT_INT_MASK_1) 59 1.3.2.1 wrstuden #define clearsoftclock() _clrsoftintr(MIPS_SOFT_INT_MASK_0) 60 1.3.2.1 wrstuden #define clearsoftnet() _clrsoftintr(MIPS_SOFT_INT_MASK_1) 61 1.2 tsubai 62 1.3.2.1 wrstuden /* 63 1.3.2.1 wrstuden * nesting interrupt masks. 64 1.3.2.1 wrstuden */ 65 1.3.2.1 wrstuden #define MIPS_INT_MASK_SPL_SOFT0 MIPS_SOFT_INT_MASK_0 66 1.3.2.1 wrstuden #define MIPS_INT_MASK_SPL_SOFT1 (MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0) 67 1.3.2.1 wrstuden #define MIPS_INT_MASK_SPL0 (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1) 68 1.3.2.1 wrstuden #define MIPS_INT_MASK_SPL1 (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0) 69 1.3.2.1 wrstuden #define MIPS_INT_MASK_SPL2 (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1) 70 1.3.2.1 wrstuden #define MIPS_INT_MASK_SPL3 (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2) 71 1.3.2.1 wrstuden #define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3) 72 1.3.2.1 wrstuden #define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4) 73 1.3.2.1 wrstuden 74 1.3.2.1 wrstuden #define spl0() (void)_spllower(0) 75 1.3.2.1 wrstuden #define splx(s) (void)_splset(s) 76 1.3.2.1 wrstuden #define splbio() _splraise(MIPS_INT_MASK_SPL0) 77 1.3.2.1 wrstuden #define splnet() _splraise(MIPS_INT_MASK_SPL1) 78 1.3.2.1 wrstuden #define spltty() _splraise(MIPS_INT_MASK_SPL1) 79 1.3.2.1 wrstuden #define splimp() _splraise(MIPS_INT_MASK_SPL1) 80 1.3.2.1 wrstuden #define splclock() _splraise(MIPS_INT_MASK_SPL2) 81 1.3.2.1 wrstuden #define splstatclock() _splraise(MIPS_INT_MASK_SPL2) 82 1.3.2.1 wrstuden #define splhigh() _splraise(MIPS_INT_MASK_SPL2) 83 1.3.2.1 wrstuden 84 1.3.2.1 wrstuden #define splsoftclock() _splraise(MIPS_INT_MASK_SPL_SOFT0) 85 1.3.2.1 wrstuden #define splsoftnet() _splraise(MIPS_INT_MASK_SPL_SOFT1) 86 1.3.2.1 wrstuden #define spllowersoftclock() _spllower(MIPS_INT_MASK_SPL_SOFT0) 87 1.1 tsubai 88 1.1 tsubai /* 89 1.1 tsubai * Index into intrcnt[], which is defined in locore 90 1.1 tsubai */ 91 1.2 tsubai #define SOFTCLOCK_INTR 0 92 1.2 tsubai #define SOFTNET_INTR 1 93 1.2 tsubai #define SERIAL0_INTR 2 94 1.2 tsubai #define SERIAL1_INTR 3 95 1.2 tsubai #define SERIAL2_INTR 4 96 1.2 tsubai #define LANCE_INTR 5 97 1.2 tsubai #define SCSI_INTR 6 98 1.2 tsubai #define ERROR_INTR 7 99 1.2 tsubai #define HARDCLOCK_INTR 8 100 1.2 tsubai #define FPU_INTR 9 101 1.2 tsubai #define SLOT1_INTR 10 102 1.2 tsubai #define SLOT2_INTR 11 103 1.2 tsubai #define SLOT3_INTR 12 104 1.2 tsubai #define FLOPPY_INTR 13 105 1.2 tsubai #define STRAY_INTR 14 106 1.1 tsubai 107 1.2 tsubai extern u_int intrcnt[]; 108 1.1 tsubai 109 1.2 tsubai /* handle i/o device interrupts */ 110 1.2 tsubai extern int (*mips_hardware_intr) __P((u_int, u_int, u_int, u_int)); 111 1.2 tsubai extern int news3400_intr __P((u_int, u_int, u_int, u_int)); 112 1.1 tsubai 113 1.3.2.1 wrstuden /* handle software interrupts */ 114 1.3.2.1 wrstuden extern void (*mips_software_intr) __P((int)); 115 1.3.2.1 wrstuden extern void news3400_softintr __P((int)); 116 1.3.2.1 wrstuden 117 1.2 tsubai #endif /* !_LOCORE */ 118 1.3.2.1 wrstuden #endif /* _KERNEL */ 119 1.1 tsubai #endif /* _MACHINE_INTR_H_ */ 120
Indexes created Mon Oct 27 08:10:08 GMT 2025