intr.h revision 1.12
1 /* $NetBSD: intr.h,v 1.12 2003/05/10 09:46:25 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _MACHINE_INTR_H_ 34 #define _MACHINE_INTR_H_ 35 36 #define IPL_NONE 0 /* disable only this interrupt */ 37 #define IPL_BIO 1 /* disable block I/O interrupts */ 38 #define IPL_NET 2 /* disable network interrupts */ 39 #define IPL_TTY 3 /* disable terminal interrupts */ 40 #define IPL_CLOCK 4 /* disable clock interrupts */ 41 #define IPL_STATCLOCK 5 /* disable profiling interrupts */ 42 #define IPL_SERIAL 6 /* disable serial hardware interrupts */ 43 #define IPL_HIGH 7 /* disable all interrupts */ 44 45 #ifdef _KERNEL 46 #ifndef _LOCORE 47 #include <sys/device.h> 48 #include <mips/cpuregs.h> 49 50 extern int _splraise __P((int)); 51 extern int _spllower __P((int)); 52 extern int _splset __P((int)); 53 extern int _splget __P((void)); 54 extern void _splnone __P((void)); 55 extern void _setsoftintr __P((int)); 56 extern void _clrsoftintr __P((int)); 57 58 /* 59 * software simulated interrupt 60 */ 61 #define SIR_NET 0x01 62 #define SIR_SERIAL 0x02 63 64 #define setsoft(x) do { \ 65 extern u_int ssir; \ 66 int s; \ 67 \ 68 s = splhigh(); \ 69 ssir |= (x); \ 70 _setsoftintr(MIPS_SOFT_INT_MASK_1); \ 71 splx(s); \ 72 } while (0) 73 74 #define setsoftclock() _setsoftintr(MIPS_SOFT_INT_MASK_0) 75 #define setsoftnet() setsoft(SIR_NET) 76 #define setsoftserial() setsoft(SIR_SERIAL) 77 78 /* 79 * nesting interrupt masks. 80 */ 81 #define MIPS_INT_MASK_SPL_SOFT0 MIPS_SOFT_INT_MASK_0 82 #define MIPS_INT_MASK_SPL_SOFT1 (MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0) 83 #define MIPS_INT_MASK_SPL0 (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1) 84 #define MIPS_INT_MASK_SPL1 (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0) 85 #define MIPS_INT_MASK_SPL2 (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1) 86 #define MIPS_INT_MASK_SPL3 (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2) 87 #define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3) 88 #define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4) 89 90 #define spl0() (void)_spllower(0) 91 #define splx(s) (void)_splset(s) 92 #define splbio() _splraise(MIPS_INT_MASK_SPL0) 93 #define splnet() _splraise(MIPS_INT_MASK_SPL1) 94 #define spltty() _splraise(MIPS_INT_MASK_SPL1) 95 #define splvm() _splraise(MIPS_INT_MASK_SPL1) 96 #define splclock() _splraise(MIPS_INT_MASK_SPL2) 97 #define splstatclock() _splraise(MIPS_INT_MASK_SPL2) 98 #define splhigh() _splraise(MIPS_INT_MASK_SPL2) 99 #define splsched() splhigh() 100 #define spllock() splhigh() 101 102 #define splsoftclock() _splraise(MIPS_INT_MASK_SPL_SOFT0) 103 #define splsoftnet() _splraise(MIPS_INT_MASK_SPL_SOFT1) 104 #define spllowersoftclock() _spllower(MIPS_INT_MASK_SPL_SOFT0) 105 106 struct newsmips_intrhand { 107 LIST_ENTRY(newsmips_intrhand) ih_q; 108 struct evcnt intr_count; 109 int (*ih_func)(void *); 110 void *ih_arg; 111 u_int ih_level; 112 u_int ih_mask; 113 u_int ih_priority; 114 }; 115 116 struct newsmips_intr { 117 LIST_HEAD(,newsmips_intrhand) intr_q; 118 }; 119 120 /* 121 * Index into intrcnt[], which is defined in locore 122 */ 123 #define SOFTCLOCK_INTR 0 124 #define SOFTNET_INTR 1 125 #define SERIAL0_INTR 2 126 #define SERIAL1_INTR 3 127 #define SERIAL2_INTR 4 128 #define LANCE_INTR 5 129 #define SCSI_INTR 6 130 #define ERROR_INTR 7 131 #define HARDCLOCK_INTR 8 132 #define FPU_INTR 9 133 #define SLOT1_INTR 10 134 #define SLOT2_INTR 11 135 #define SLOT3_INTR 12 136 #define FLOPPY_INTR 13 137 #define STRAY_INTR 14 138 139 extern u_int intrcnt[]; 140 141 /* handle i/o device interrupts */ 142 extern void news3400_intr __P((u_int, u_int, u_int, u_int)); 143 extern void news5000_intr __P((u_int, u_int, u_int, u_int)); 144 145 extern void (*enable_intr) __P((void)); 146 extern void (*disable_intr) __P((void)); 147 148 #endif /* !_LOCORE */ 149 #endif /* _KERNEL */ 150 #endif /* _MACHINE_INTR_H_ */ 151
Indexes created Mon Oct 27 08:10:08 GMT 2025