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intr.h revision 1.8 
      1 /*	$NetBSD: intr.h,v 1.8 2000/08/21 02:06:33 thorpej Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1998 Jonathan Stone.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Jonathan Stone for
     17  *      the NetBSD Project.
     18  * 4. The name of the author may not be used to endorse or promote products
     19  *    derived from this software without specific prior written permission.
     20  *
     21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31  */
     32 
     33 #ifndef _MACHINE_INTR_H_
     34 #define _MACHINE_INTR_H_
     35 
     36 #define IPL_NONE	0	/* disable only this interrupt */
     37 #define IPL_BIO		1	/* disable block I/O interrupts */
     38 #define IPL_NET		2	/* disable network interrupts */
     39 #define IPL_TTY		3	/* disable terminal interrupts */
     40 #define IPL_CLOCK	4	/* disable clock interrupts */
     41 #define IPL_STATCLOCK	5	/* disable profiling interrupts */
     42 #define IPL_SERIAL	6	/* disable serial hardware interrupts */
     43 #define IPL_HIGH	7	/* disable all interrupts */
     44 
     45 #ifdef _KERNEL
     46 #ifndef _LOCORE
     47 #include <mips/cpuregs.h>
     48 
     49 extern int _splraise __P((int));
     50 extern int _spllower __P((int));
     51 extern int _splset __P((int));
     52 extern int _splget __P((void));
     53 extern void _splnone __P((void));
     54 extern void _setsoftintr __P((int));
     55 extern void _clrsoftintr __P((int));
     56 
     57 /*
     58  * software simulated interrupt
     59  */
     60 #define SIR_NET		0x01
     61 #define SIR_SERIAL	0x02
     62 
     63 #define setsoft(x)	do {			\
     64 	extern u_int ssir;			\
     65 	int s;					\
     66 						\
     67 	s = splhigh();				\
     68 	ssir |= (x);				\
     69 	_setsoftintr(MIPS_SOFT_INT_MASK_1);	\
     70 	splx(s);				\
     71 } while (0)
     72 
     73 #define setsoftclock()	_setsoftintr(MIPS_SOFT_INT_MASK_0)
     74 #define setsoftnet()	setsoft(SIR_NET)
     75 #define setsoftserial()	setsoft(SIR_SERIAL)
     76 
     77 /*
     78  * nesting interrupt masks.
     79  */
     80 #define MIPS_INT_MASK_SPL_SOFT0	MIPS_SOFT_INT_MASK_0
     81 #define MIPS_INT_MASK_SPL_SOFT1	(MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0)
     82 #define MIPS_INT_MASK_SPL0	(MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1)
     83 #define MIPS_INT_MASK_SPL1	(MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0)
     84 #define MIPS_INT_MASK_SPL2	(MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1)
     85 #define MIPS_INT_MASK_SPL3	(MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2)
     86 #define MIPS_INT_MASK_SPL4	(MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3)
     87 #define MIPS_INT_MASK_SPL5	(MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4)
     88 
     89 #define spl0()		(void)_spllower(0)
     90 #define splx(s)		(void)_splset(s)
     91 #define splbio()	_splraise(MIPS_INT_MASK_SPL0)
     92 #define splnet()	_splraise(MIPS_INT_MASK_SPL1)
     93 #define spltty()	_splraise(MIPS_INT_MASK_SPL1)
     94 #define splimp()	_splraise(MIPS_INT_MASK_SPL1)
     95 #define splclock()	_splraise(MIPS_INT_MASK_SPL2)
     96 #define splstatclock()	_splraise(MIPS_INT_MASK_SPL2)
     97 #define splhigh()	_splraise(MIPS_INT_MASK_SPL2)
     98 #define	splsched()	splhigh()
     99 
    100 #define splsoftclock()	_splraise(MIPS_INT_MASK_SPL_SOFT0)
    101 #define splsoftnet()	_splraise(MIPS_INT_MASK_SPL_SOFT1)
    102 #define spllowersoftclock() _spllower(MIPS_INT_MASK_SPL_SOFT0)
    103 
    104 /*
    105  * Index into intrcnt[], which is defined in locore
    106  */
    107 #define SOFTCLOCK_INTR	0
    108 #define SOFTNET_INTR	1
    109 #define SERIAL0_INTR	2
    110 #define SERIAL1_INTR	3
    111 #define SERIAL2_INTR	4
    112 #define LANCE_INTR	5
    113 #define SCSI_INTR	6
    114 #define ERROR_INTR	7
    115 #define HARDCLOCK_INTR	8
    116 #define FPU_INTR	9
    117 #define SLOT1_INTR	10
    118 #define SLOT2_INTR	11
    119 #define SLOT3_INTR	12
    120 #define FLOPPY_INTR	13
    121 #define STRAY_INTR	14
    122 
    123 extern u_int intrcnt[];
    124 
    125 /* handle i/o device interrupts */
    126 extern void news3400_intr __P((u_int, u_int, u_int, u_int));
    127 extern void news5000_intr __P((u_int, u_int, u_int, u_int));
    128 
    129 extern void (*enable_intr) __P((void));
    130 extern void (*disable_intr) __P((void));
    131 
    132 #endif /* !_LOCORE */
    133 #endif /* _KERNEL */
    134 #endif /* _MACHINE_INTR_H_ */
    135