1 1.2 tsubai /* $NetBSD: locore.S,v 1.2 1999/12/22 05:54:41 tsubai Exp $ */ 2 1.1 tsubai 3 1.1 tsubai /*- 4 1.1 tsubai * Copyright (C) 1999 Tsubai Masanari. All rights reserved. 5 1.1 tsubai * 6 1.1 tsubai * Redistribution and use in source and binary forms, with or without 7 1.1 tsubai * modification, are permitted provided that the following conditions 8 1.1 tsubai * are met: 9 1.1 tsubai * 1. Redistributions of source code must retain the above copyright 10 1.1 tsubai * notice, this list of conditions and the following disclaimer. 11 1.1 tsubai * 2. Redistributions in binary form must reproduce the above copyright 12 1.1 tsubai * notice, this list of conditions and the following disclaimer in the 13 1.1 tsubai * documentation and/or other materials provided with the distribution. 14 1.1 tsubai * 3. The name of the author may not be used to endorse or promote products 15 1.1 tsubai * derived from this software without specific prior written permission. 16 1.1 tsubai * 17 1.1 tsubai * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 1.1 tsubai * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 1.1 tsubai * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 1.1 tsubai * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 1.1 tsubai * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 1.1 tsubai * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 1.1 tsubai * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 1.1 tsubai * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 1.1 tsubai * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 1.1 tsubai * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 1.1 tsubai */ 28 1.1 tsubai 29 1.1 tsubai #include <mips/asm.h> 30 1.1 tsubai #include <mips/cpuregs.h> 31 1.1 tsubai 32 1.1 tsubai .set noreorder 33 1.1 tsubai .text 34 1.1 tsubai .align 2 35 1.1 tsubai 36 1.1 tsubai .globl _start 37 1.1 tsubai _start: 38 1.2 tsubai bal 1f 39 1.2 tsubai nop 40 1.2 tsubai 1: 41 1.2 tsubai la t0, 1b 42 1.2 tsubai beq t0, ra, skip 43 1.2 tsubai nop 44 1.2 tsubai 45 1.2 tsubai /* relocate myself */ 46 1.2 tsubai subu t0, ra, (1b - _start) # load address 47 1.2 tsubai la t1, _start 48 1.2 tsubai la t2, _edata 49 1.2 tsubai 2: 50 1.2 tsubai lw t3, 0(t0) 51 1.2 tsubai nop 52 1.2 tsubai sw t3, 0(t1) 53 1.2 tsubai addu t0, t0, 4 54 1.2 tsubai addu t1, t1, 4 55 1.2 tsubai bne t1, t2, 2b 56 1.2 tsubai nop 57 1.2 tsubai 58 1.2 tsubai skip: 59 1.1 tsubai j boot 60 1.1 tsubai nop 61 1.1 tsubai 62 1.2 tsubai /* 63 1.2 tsubai * void mips1_flushicache(addr, len) 64 1.2 tsubai */ 65 1.2 tsubai .globl mips1_flushicache 66 1.1 tsubai 67 1.2 tsubai mips1_flushicache: 68 1.1 tsubai mfc0 v0, MIPS_COP_0_STATUS # save SR 69 1.1 tsubai mtc0 zero, MIPS_COP_0_STATUS # disable interrupts 70 1.1 tsubai 71 1.1 tsubai la v1, 1f 72 1.1 tsubai or v1, MIPS_KSEG1_START # run uncached 73 1.1 tsubai j v1 74 1.1 tsubai nop 75 1.1 tsubai 1: 76 1.1 tsubai li v1, MIPS_SR_ISOL_CACHES | MIPS_SR_SWAP_CACHES 77 1.1 tsubai mtc0 v1, MIPS_COP_0_STATUS 78 1.1 tsubai nop 79 1.1 tsubai addu a1, a1, a0 # compute ending address 80 1.1 tsubai 2: 81 1.1 tsubai sb zero, -4(a0) 82 1.1 tsubai bne a0, a1, 2b 83 1.1 tsubai addu a0, a0, 4 84 1.1 tsubai 85 1.1 tsubai mtc0 v0, MIPS_COP_0_STATUS # enable interrupts 86 1.1 tsubai j ra # return and run cached 87 1.1 tsubai nop 88
Indexes created Mon Oct 13 01:09:56 GMT 2025