locore.S revision 1.1 1 /* $NetBSD: locore.S,v 1.1 1999/07/08 11:48:05 tsubai Exp $ */
2
3 /*-
4 * Copyright (C) 1999 Tsubai Masanari. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <mips/asm.h>
30 #include <mips/cpuregs.h>
31
32 .set noreorder
33 .text
34 .align 2
35
36 .globl _start
37 _start:
38 j boot
39 nop
40
41 /* void flushicache(addr, len); */
42
43 .globl flushicache
44 flushicache:
45 mfc0 v0, MIPS_COP_0_STATUS # save SR
46 mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
47
48 la v1, 1f
49 or v1, MIPS_KSEG1_START # run uncached
50 j v1
51 nop
52 1:
53 li v1, MIPS_SR_ISOL_CACHES | MIPS_SR_SWAP_CACHES
54 mtc0 v1, MIPS_COP_0_STATUS
55 nop
56 addu a1, a1, a0 # compute ending address
57 2:
58 sb zero, -4(a0)
59 bne a0, a1, 2b
60 addu a0, a0, 4
61
62 mtc0 v0, MIPS_COP_0_STATUS # enable interrupts
63 j ra # return and run cached
64 nop
65