locore.S revision 1.1.2.1 1 /* $NetBSD: locore.S,v 1.1.2.1 2000/11/20 20:17:33 bouyer Exp $ */
2
3 /*-
4 * Copyright (C) 1999 Tsubai Masanari. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <mips/asm.h>
30 #include <mips/cpuregs.h>
31
32 .set noreorder
33 .text
34 .align 2
35
36 .globl _start
37 _start:
38 bal 1f
39 nop
40 1:
41 la t0, 1b
42 beq t0, ra, skip
43 nop
44
45 /* relocate myself */
46 subu t0, ra, (1b - _start) # load address
47 la t1, _start
48 la t2, _edata
49 2:
50 lw t3, 0(t0)
51 nop
52 sw t3, 0(t1)
53 addu t0, t0, 4
54 addu t1, t1, 4
55 bne t1, t2, 2b
56 nop
57
58 skip:
59 j boot
60 nop
61
62 /*
63 * void mips1_flushicache(addr, len)
64 */
65 .globl mips1_flushicache
66
67 mips1_flushicache:
68 mfc0 v0, MIPS_COP_0_STATUS # save SR
69 mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
70
71 la v1, 1f
72 or v1, MIPS_KSEG1_START # run uncached
73 j v1
74 nop
75 1:
76 li v1, MIPS_SR_ISOL_CACHES | MIPS_SR_SWAP_CACHES
77 mtc0 v1, MIPS_COP_0_STATUS
78 nop
79 addu a1, a1, a0 # compute ending address
80 2:
81 sb zero, -4(a0)
82 bne a0, a1, 2b
83 addu a0, a0, 4
84
85 mtc0 v0, MIPS_COP_0_STATUS # enable interrupts
86 j ra # return and run cached
87 nop
88