esp.c revision 1.1
1 /* $NetBSD: esp.c,v 1.1 1998/07/05 07:53:45 dbj Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Charles M. Hannum. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * Copyright (c) 1994 Peter Galbavy 71 * Copyright (c) 1995 Paul Kranenburg 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 3. All advertising materials mentioning features or use of this software 83 * must display the following acknowledgement: 84 * This product includes software developed by Peter Galbavy 85 * 4. The name of the author may not be used to endorse or promote products 86 * derived from this software without specific prior written permission. 87 * 88 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 89 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 90 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 91 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 92 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 93 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 94 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 95 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 96 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 97 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 98 * POSSIBILITY OF SUCH DAMAGE. 99 */ 100 101 /* 102 * Based on aic6360 by Jarle Greipsland 103 * 104 * Acknowledgements: Many of the algorithms used in this driver are 105 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 106 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 107 */ 108 109 /* 110 * Grabbed from the sparc port at revision 1.73 for the NeXT. 111 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 112 */ 113 114 #include <sys/types.h> 115 #include <sys/param.h> 116 #include <sys/systm.h> 117 #include <sys/kernel.h> 118 #include <sys/errno.h> 119 #include <sys/ioctl.h> 120 #include <sys/device.h> 121 #include <sys/buf.h> 122 #include <sys/proc.h> 123 #include <sys/user.h> 124 #include <sys/queue.h> 125 126 #include <dev/scsipi/scsi_all.h> 127 #include <dev/scsipi/scsipi_all.h> 128 #include <dev/scsipi/scsiconf.h> 129 #include <dev/scsipi/scsi_message.h> 130 131 #include <machine/bus.h> 132 #include <machine/autoconf.h> 133 #include <machine/cpu.h> 134 135 #include <dev/ic/ncr53c9xreg.h> 136 #include <dev/ic/ncr53c9xvar.h> 137 138 #include <next68k/next68k/isr.h> 139 140 #include <next68k/dev/nextdmareg.h> 141 #include <next68k/dev/nextdmavar.h> 142 143 #include "espreg.h" 144 #include "espvar.h" 145 146 void espattach_intio __P((struct device *, struct device *, void *)); 147 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 148 149 void espattach __P((struct esp_softc *)); 150 151 /* Linkup to the rest of the kernel */ 152 struct cfattach esp_ca = { 153 sizeof(struct esp_softc), espmatch_intio, espattach_intio 154 }; 155 156 struct scsipi_adapter esp_switch = { 157 ncr53c9x_scsi_cmd, 158 minphys, /* no max at this level; handled by DMA code */ 159 NULL, 160 NULL, 161 }; 162 163 struct scsipi_device esp_dev = { 164 NULL, /* Use default error handler */ 165 NULL, /* have a queue, served by this */ 166 NULL, /* have no async handler */ 167 NULL, /* Use default 'done' routine */ 168 }; 169 170 /* 171 * Functions and the switch for the MI code. 172 */ 173 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 174 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 175 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 176 void esp_dma_reset __P((struct ncr53c9x_softc *)); 177 int esp_dma_intr __P((struct ncr53c9x_softc *)); 178 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 179 size_t *, int, size_t *)); 180 void esp_dma_go __P((struct ncr53c9x_softc *)); 181 void esp_dma_stop __P((struct ncr53c9x_softc *)); 182 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 183 184 struct ncr53c9x_glue esp_glue = { 185 esp_read_reg, 186 esp_write_reg, 187 esp_dma_isintr, 188 esp_dma_reset, 189 esp_dma_intr, 190 esp_dma_setup, 191 esp_dma_go, 192 esp_dma_stop, 193 esp_dma_isactive, 194 NULL, /* gl_clear_latched_intr */ 195 }; 196 197 int 198 espmatch_intio(parent, cf, aux) 199 struct device *parent; 200 struct cfdata *cf; 201 void *aux; 202 { 203 /* should probably probe here */ 204 /* Should also probably set up data from config */ 205 206 /* this code isn't working yet, don't match on it */ 207 return(0); 208 } 209 210 void 211 espattach_intio(parent, self, aux) 212 struct device *parent, *self; 213 void *aux; 214 { 215 struct esp_softc *esc = (void *)self; 216 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 217 218 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 219 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 220 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 221 panic("\n%s: can't map ncr53c90 registers\n", 222 sc->sc_dev.dv_xname); 223 } 224 225 sc->sc_id = 7; 226 sc->sc_freq = 20; /* Mhz */ 227 228 /* @@@ Some ESP_DCTL bits probably need setting */ 229 230 /* Set up SCSI DMA */ 231 { 232 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 233 234 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 235 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 236 panic("\n%s: can't map scsi DMA registers\n", 237 sc->sc_dev.dv_xname); 238 } 239 240 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 241 esc->sc_scsi_dma.nd_chaining_flag = 0; 242 esc->sc_scsi_dma.nd_shutdown_cb = NULL; 243 esc->sc_scsi_dma.nd_continue_cb = NULL; 244 esc->sc_scsi_dma.nd_completed_cb = NULL; 245 esc->sc_scsi_dma.nd_cb_arg = NULL; 246 nextdma_config(&esc->sc_scsi_dma); 247 248 } 249 250 espattach(esc); 251 } 252 /* 253 * Attach this instance, and then all the sub-devices 254 */ 255 void 256 espattach(esc) 257 struct esp_softc *esc; 258 { 259 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 260 261 /* 262 * Set up glue for MI code early; we use some of it here. 263 */ 264 sc->sc_glue = &esp_glue; 265 266 /* 267 * XXX More of this should be in ncr53c9x_attach(), but 268 * XXX should we really poke around the chip that much in 269 * XXX the MI code? Think about this more... 270 */ 271 272 /* 273 * It is necessary to try to load the 2nd config register here, 274 * to find out what rev the esp chip is, else the ncr53c9x_reset 275 * will not set up the defaults correctly. 276 */ 277 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 278 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 279 sc->sc_cfg3 = NCRCFG3_CDB; 280 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 281 282 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 283 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 284 sc->sc_rev = NCR_VARIANT_ESP100; 285 } else { 286 sc->sc_cfg2 = NCRCFG2_SCSI2; 287 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 288 sc->sc_cfg3 = 0; 289 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 290 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 291 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 292 if (NCR_READ_REG(sc, NCR_CFG3) != 293 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 294 sc->sc_rev = NCR_VARIANT_ESP100A; 295 } else { 296 /* NCRCFG2_FE enables > 64K transfers */ 297 sc->sc_cfg2 |= NCRCFG2_FE; 298 sc->sc_cfg3 = 0; 299 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 300 sc->sc_rev = NCR_VARIANT_ESP200; 301 } 302 } 303 304 /* 305 * XXX minsync and maxxfer _should_ be set up in MI code, 306 * XXX but it appears to have some dependency on what sort 307 * XXX of DMA we're hooked up to, etc. 308 */ 309 310 /* 311 * This is the value used to start sync negotiations 312 * Note that the NCR register "SYNCTP" is programmed 313 * in "clocks per byte", and has a minimum value of 4. 314 * The SCSI period used in negotiation is one-fourth 315 * of the time (in nanoseconds) needed to transfer one byte. 316 * Since the chip's clock is given in MHz, we have the following 317 * formula: 4 * period = (1000 / freq) * 4 318 */ 319 sc->sc_minsync = 1000 / sc->sc_freq; 320 321 /* 322 * Alas, we must now modify the value a bit, because it's 323 * only valid when can switch on FASTCLK and FASTSCSI bits 324 * in config register 3... 325 */ 326 switch (sc->sc_rev) { 327 case NCR_VARIANT_ESP100: 328 sc->sc_maxxfer = 64 * 1024; 329 sc->sc_minsync = 0; /* No synch on old chip? */ 330 break; 331 332 case NCR_VARIANT_ESP100A: 333 sc->sc_maxxfer = 64 * 1024; 334 /* Min clocks/byte is 5 */ 335 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 336 break; 337 338 case NCR_VARIANT_ESP200: 339 sc->sc_maxxfer = 16 * 1024 * 1024; 340 /* XXX - do actually set FAST* bits */ 341 break; 342 } 343 344 /* Establish interrupt channel */ 345 isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc, 346 NEXT_I_IPL(NEXT_I_SCSI), 0); 347 INTR_ENABLE(NEXT_I_SCSI); 348 349 /* register interrupt stats */ 350 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 351 352 /* Do the common parts of attachment. */ 353 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 354 355 #if 0 356 /* Turn on target selection using the `dma' method */ 357 ncr53c9x_dmaselect = 1; 358 359 bootpath_store(1, NULL); 360 #endif 361 362 } 363 364 /* 365 * Glue functions. 366 */ 367 368 u_char 369 esp_read_reg(sc, reg) 370 struct ncr53c9x_softc *sc; 371 int reg; 372 { 373 struct esp_softc *esc = (struct esp_softc *)sc; 374 375 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 376 } 377 378 void 379 esp_write_reg(sc, reg, val) 380 struct ncr53c9x_softc *sc; 381 int reg; 382 u_char val; 383 { 384 struct esp_softc *esc = (struct esp_softc *)sc; 385 386 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 387 } 388 389 int 390 esp_dma_isintr(sc) 391 struct ncr53c9x_softc *sc; 392 { 393 struct esp_softc *esc = (struct esp_softc *)sc; 394 panic("Not yet implemented"); 395 return (0); 396 } 397 398 void 399 esp_dma_reset(sc) 400 struct ncr53c9x_softc *sc; 401 { 402 struct esp_softc *esc = (struct esp_softc *)sc; 403 panic("Not yet implemented"); 404 } 405 406 int 407 esp_dma_intr(sc) 408 struct ncr53c9x_softc *sc; 409 { 410 struct esp_softc *esc = (struct esp_softc *)sc; 411 panic("Not yet implemented"); 412 return (0); 413 } 414 415 int 416 esp_dma_setup(sc, addr, len, datain, dmasize) 417 struct ncr53c9x_softc *sc; 418 caddr_t *addr; 419 size_t *len; 420 int datain; 421 size_t *dmasize; 422 { 423 struct esp_softc *esc = (struct esp_softc *)sc; 424 panic("Not yet implemented"); 425 return (0); 426 } 427 428 void 429 esp_dma_go(sc) 430 struct ncr53c9x_softc *sc; 431 { 432 struct esp_softc *esc = (struct esp_softc *)sc; 433 panic("Not yet implemented"); 434 } 435 436 void 437 esp_dma_stop(sc) 438 struct ncr53c9x_softc *sc; 439 { 440 struct esp_softc *esc = (struct esp_softc *)sc; 441 panic("Not yet implemented"); 442 } 443 444 int 445 esp_dma_isactive(sc) 446 struct ncr53c9x_softc *sc; 447 { 448 struct esp_softc *esc = (struct esp_softc *)sc; 449 panic("Not yet implemented"); 450 return(0); 451 } 452
Indexes created Wed Sep 24 05:09:52 GMT 2025