esp.c revision 1.10
1 /* $NetBSD: esp.c,v 1.10 1998/12/19 09:31:44 dbj Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Grabbed from the sparc port at revision 1.73 for the NeXT. 81 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 82 */ 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/device.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 #include <sys/user.h> 94 #include <sys/queue.h> 95 96 #include <dev/scsipi/scsi_all.h> 97 #include <dev/scsipi/scsipi_all.h> 98 #include <dev/scsipi/scsiconf.h> 99 #include <dev/scsipi/scsi_message.h> 100 101 #include <machine/bus.h> 102 #include <machine/autoconf.h> 103 #include <machine/cpu.h> 104 105 #include <dev/ic/ncr53c9xreg.h> 106 #include <dev/ic/ncr53c9xvar.h> 107 108 #include <next68k/next68k/isr.h> 109 110 #include <next68k/dev/nextdmareg.h> 111 #include <next68k/dev/nextdmavar.h> 112 113 #include "espreg.h" 114 #include "espvar.h" 115 116 #if 1 117 #define ESP_DEBUG 118 #endif 119 120 #ifdef ESP_DEBUG 121 int esp_debug = 0; 122 #define DPRINTF(x) if (esp_debug) printf x; 123 #else 124 #define DPRINTF(x) 125 #endif 126 127 128 void espattach_intio __P((struct device *, struct device *, void *)); 129 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 130 131 /* DMA callbacks */ 132 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 133 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 134 void esp_dmacb_shutdown __P((void *arg)); 135 136 /* Linkup to the rest of the kernel */ 137 struct cfattach esp_ca = { 138 sizeof(struct esp_softc), espmatch_intio, espattach_intio 139 }; 140 141 struct scsipi_device esp_dev = { 142 NULL, /* Use default error handler */ 143 NULL, /* have a queue, served by this */ 144 NULL, /* have no async handler */ 145 NULL, /* Use default 'done' routine */ 146 }; 147 148 /* 149 * Functions and the switch for the MI code. 150 */ 151 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 152 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 153 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 154 void esp_dma_reset __P((struct ncr53c9x_softc *)); 155 int esp_dma_intr __P((struct ncr53c9x_softc *)); 156 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 157 size_t *, int, size_t *)); 158 void esp_dma_go __P((struct ncr53c9x_softc *)); 159 void esp_dma_stop __P((struct ncr53c9x_softc *)); 160 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 161 162 struct ncr53c9x_glue esp_glue = { 163 esp_read_reg, 164 esp_write_reg, 165 esp_dma_isintr, 166 esp_dma_reset, 167 esp_dma_intr, 168 esp_dma_setup, 169 esp_dma_go, 170 esp_dma_stop, 171 esp_dma_isactive, 172 NULL, /* gl_clear_latched_intr */ 173 }; 174 175 int 176 espmatch_intio(parent, cf, aux) 177 struct device *parent; 178 struct cfdata *cf; 179 void *aux; 180 { 181 /* should probably probe here */ 182 /* Should also probably set up data from config */ 183 184 #if 1 185 /* this code isn't working yet, don't match on it */ 186 return(0); 187 #else 188 return(1); 189 #endif 190 } 191 192 void 193 espattach_intio(parent, self, aux) 194 struct device *parent, *self; 195 void *aux; 196 { 197 struct esp_softc *esc = (void *)self; 198 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 199 200 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 201 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 202 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 203 panic("\n%s: can't map ncr53c90 registers", 204 sc->sc_dev.dv_xname); 205 } 206 207 sc->sc_id = 7; 208 sc->sc_freq = 20; /* Mhz */ 209 210 /* 211 * Set up glue for MI code early; we use some of it here. 212 */ 213 sc->sc_glue = &esp_glue; 214 215 /* 216 * XXX More of this should be in ncr53c9x_attach(), but 217 * XXX should we really poke around the chip that much in 218 * XXX the MI code? Think about this more... 219 */ 220 221 /* 222 * It is necessary to try to load the 2nd config register here, 223 * to find out what rev the esp chip is, else the ncr53c9x_reset 224 * will not set up the defaults correctly. 225 */ 226 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 227 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 228 sc->sc_cfg3 = NCRCFG3_CDB; 229 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 230 231 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 232 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 233 sc->sc_rev = NCR_VARIANT_ESP100; 234 } else { 235 sc->sc_cfg2 = NCRCFG2_SCSI2; 236 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 237 sc->sc_cfg3 = 0; 238 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 239 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 240 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 241 if (NCR_READ_REG(sc, NCR_CFG3) != 242 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 243 sc->sc_rev = NCR_VARIANT_ESP100A; 244 } else { 245 /* NCRCFG2_FE enables > 64K transfers */ 246 sc->sc_cfg2 |= NCRCFG2_FE; 247 sc->sc_cfg3 = 0; 248 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 249 sc->sc_rev = NCR_VARIANT_ESP200; 250 } 251 } 252 253 /* 254 * XXX minsync and maxxfer _should_ be set up in MI code, 255 * XXX but it appears to have some dependency on what sort 256 * XXX of DMA we're hooked up to, etc. 257 */ 258 259 /* 260 * This is the value used to start sync negotiations 261 * Note that the NCR register "SYNCTP" is programmed 262 * in "clocks per byte", and has a minimum value of 4. 263 * The SCSI period used in negotiation is one-fourth 264 * of the time (in nanoseconds) needed to transfer one byte. 265 * Since the chip's clock is given in MHz, we have the following 266 * formula: 4 * period = (1000 / freq) * 4 267 */ 268 sc->sc_minsync = 1000 / sc->sc_freq; 269 270 /* 271 * Alas, we must now modify the value a bit, because it's 272 * only valid when can switch on FASTCLK and FASTSCSI bits 273 * in config register 3... 274 */ 275 switch (sc->sc_rev) { 276 case NCR_VARIANT_ESP100: 277 sc->sc_maxxfer = 64 * 1024; 278 sc->sc_minsync = 0; /* No synch on old chip? */ 279 break; 280 281 case NCR_VARIANT_ESP100A: 282 sc->sc_maxxfer = 64 * 1024; 283 /* Min clocks/byte is 5 */ 284 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 285 break; 286 287 case NCR_VARIANT_ESP200: 288 sc->sc_maxxfer = 16 * 1024 * 1024; 289 /* XXX - do actually set FAST* bits */ 290 break; 291 } 292 293 /* @@@ Some ESP_DCTL bits probably need setting */ 294 NCR_WRITE_REG(sc, ESP_DCTL, 295 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 296 DELAY(10); 297 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 298 DELAY(10); 299 300 /* Set up SCSI DMA */ 301 { 302 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 303 304 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 305 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 306 panic("\n%s: can't map scsi DMA registers", 307 sc->sc_dev.dv_xname); 308 } 309 310 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 311 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 312 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 313 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 314 esc->sc_scsi_dma.nd_cb_arg = sc; 315 nextdma_config(&esc->sc_scsi_dma); 316 nextdma_init(&esc->sc_scsi_dma); 317 318 { 319 int error; 320 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 321 sc->sc_maxxfer, 1, sc->sc_maxxfer, 322 0, BUS_DMA_ALLOCNOW, &esc->sc_dmamap)) != 0) { 323 panic("%s: can't create i/o DMA map, error = %d", 324 sc->sc_dev.dv_xname,error); 325 } 326 } 327 } 328 329 #if 0 330 /* Turn on target selection using the `dma' method */ 331 ncr53c9x_dmaselect = 1; 332 #else 333 ncr53c9x_dmaselect = 0; 334 #endif 335 336 esc->sc_slop_bgn_addr = 0; 337 esc->sc_slop_bgn_size = 0; 338 esc->sc_slop_end_addr = 0; 339 esc->sc_slop_end_size = 0; 340 esc->sc_datain = -1; 341 esc->sc_dmamap_loaded = 0; 342 343 /* Establish interrupt channel */ 344 isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc, 345 NEXT_I_IPL(NEXT_I_SCSI), 0); 346 INTR_ENABLE(NEXT_I_SCSI); 347 348 /* register interrupt stats */ 349 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 350 351 /* Do the common parts of attachment. */ 352 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 353 sc->sc_adapter.scsipi_minphys = minphys; 354 ncr53c9x_attach(sc, &esp_dev); 355 } 356 357 /* 358 * Glue functions. 359 */ 360 361 u_char 362 esp_read_reg(sc, reg) 363 struct ncr53c9x_softc *sc; 364 int reg; 365 { 366 struct esp_softc *esc = (struct esp_softc *)sc; 367 368 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 369 } 370 371 void 372 esp_write_reg(sc, reg, val) 373 struct ncr53c9x_softc *sc; 374 int reg; 375 u_char val; 376 { 377 struct esp_softc *esc = (struct esp_softc *)sc; 378 379 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 380 } 381 382 int 383 esp_dma_isintr(sc) 384 struct ncr53c9x_softc *sc; 385 { 386 struct esp_softc *esc = (struct esp_softc *)sc; 387 388 int r = (INTR_OCCURRED(NEXT_I_SCSI)); 389 390 if (r) { 391 DPRINTF(("esp_dma_isintr = 0x%b\n",r,NEXT_INTR_BITS)); 392 393 if (esc->sc_datain) { 394 NCR_WRITE_REG(sc, ESP_DCTL, 395 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 396 } else { 397 NCR_WRITE_REG(sc, ESP_DCTL, 398 ESPDCTL_20MHZ | ESPDCTL_INTENB); 399 } 400 } 401 402 return (r); 403 } 404 405 void 406 esp_dma_reset(sc) 407 struct ncr53c9x_softc *sc; 408 { 409 struct esp_softc *esc = (struct esp_softc *)sc; 410 411 nextdma_reset(&esc->sc_scsi_dma); 412 413 if (esc->sc_dmamap->dm_mapsize != 0) { 414 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap); 415 } 416 417 esc->sc_slop_bgn_addr = 0; 418 esc->sc_slop_bgn_size = 0; 419 esc->sc_slop_end_addr = 0; 420 esc->sc_slop_end_size = 0; 421 esc->sc_datain = -1; 422 esc->sc_dmamap_loaded = 0; 423 } 424 425 int 426 esp_dma_intr(sc) 427 struct ncr53c9x_softc *sc; 428 { 429 int trans; 430 int resid; 431 int datain; 432 struct esp_softc *esc = (struct esp_softc *)sc; 433 434 datain = esc->sc_datain; 435 436 DPRINTF(("esp_dma_intr resetting dma\n")); 437 438 /* If the dma hasn't finished when we are in a scsi 439 * interrupt. Then, "Houston, we have a problem." 440 * Stop DMA and figure out how many bytes were transferred 441 */ 442 esp_dma_reset(sc); 443 444 resid = 0; 445 446 /* 447 * If a transfer onto the SCSI bus gets interrupted by the device 448 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 449 * as residual since the ESP counter registers get decremented as 450 * bytes are clocked into the FIFO. 451 */ 452 453 if (! datain) { 454 resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 455 if (resid) { 456 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 457 NCRCMD(sc, NCRCMD_FLUSH); 458 DELAY(1); 459 } 460 } 461 462 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 463 /* 464 * `Terminal count' is off, so read the residue 465 * out of the ESP counter registers. 466 */ 467 resid += (NCR_READ_REG(sc, NCR_TCL) | 468 (NCR_READ_REG(sc, NCR_TCM) << 8) | 469 ((sc->sc_cfg2 & NCRCFG2_FE) 470 ? (NCR_READ_REG(sc, NCR_TCH) << 16) 471 : 0)); 472 473 if (resid == 0 && esc->sc_dmasize == 65536 && 474 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 475 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 476 resid = 65536; 477 } 478 479 trans = esc->sc_dmasize - resid; 480 if (trans < 0) { /* transferred < 0 ? */ 481 #if 0 482 /* 483 * This situation can happen in perfectly normal operation 484 * if the ESP is reselected while using DMA to select 485 * another target. As such, don't print the warning. 486 */ 487 printf("%s: xfer (%d) > req (%d)\n", 488 esc->sc_dev.dv_xname, trans, esc->sc_dmasize); 489 #endif 490 trans = esc->sc_dmasize; 491 } 492 493 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 494 NCR_READ_REG(sc, NCR_TCL), 495 NCR_READ_REG(sc, NCR_TCM), 496 (sc->sc_cfg2 & NCRCFG2_FE) 497 ? NCR_READ_REG(sc, NCR_TCH) : 0, 498 trans, resid)); 499 500 *esc->sc_dmalen -= trans; 501 *esc->sc_dmaaddr += trans; 502 503 return 0; 504 } 505 506 int 507 esp_dma_setup(sc, addr, len, datain, dmasize) 508 struct ncr53c9x_softc *sc; 509 caddr_t *addr; 510 size_t *len; 511 int datain; 512 size_t *dmasize; 513 { 514 struct esp_softc *esc = (struct esp_softc *)sc; 515 516 /* Save these in case we have to abort DMA */ 517 esc->sc_dmaaddr = addr; 518 esc->sc_dmalen = len; 519 esc->sc_dmasize = *dmasize; 520 521 DPRINTF(("esp_dma_setup(0x%08lx,0x%08lx)\n",*addr,*dmasize)); 522 523 #ifdef DIAGNOSTIC 524 if ((esc->sc_datain != -1) || 525 (esc->sc_dmamap->dm_mapsize != 0) || 526 (esc->sc_dmamap_loaded != 0)) { 527 panic("%s: map already loaded in esp_dma_setup\n" 528 "\tdatain = %d\n\tmapsize=%d\n\tloaed = %d", 529 sc->sc_dev.dv_xname,esc->sc_datain,esc->sc_dmamap->dm_mapsize, 530 esc->sc_dmamap_loaded); 531 } 532 #endif 533 534 /* Deal with DMA alignment issues, by stuffing the FIFO. 535 * This assumes that if bus_dmamap_load is given an aligned 536 * buffer, then it will generate aligned hardware addresses 537 * to give to the device. Perhaps that is not a good assumption, 538 * but it is probably true. [dbj (at) netbsd.org:19980719.0135EDT] 539 */ 540 { 541 int slop_bgn_size; /* # bytes to be fifo'd at beginning */ 542 int slop_end_size; /* # bytes to be fifo'd at end */ 543 544 { 545 u_long bgn = (u_long)(*addr); 546 u_long end = (u_long)(*addr+*dmasize); 547 548 slop_bgn_size = DMA_BEGINALIGNMENT-(bgn % DMA_BEGINALIGNMENT); 549 if (slop_bgn_size == DMA_BEGINALIGNMENT) slop_bgn_size = 0; 550 slop_end_size = end % DMA_ENDALIGNMENT; 551 } 552 553 /* Check to make sure we haven't counted extra slop 554 * as would happen for a very short dma buffer */ 555 if (slop_bgn_size+slop_end_size >= *dmasize) { 556 slop_bgn_size = *dmasize; 557 slop_end_size = 0; 558 559 } else { 560 int error; 561 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 562 esc->sc_dmamap, 563 *addr+slop_bgn_size, 564 *dmasize-(slop_bgn_size+slop_end_size), 565 NULL, BUS_DMA_NOWAIT); 566 if (error) { 567 panic("%s: can't load dma map. error = %d", 568 sc->sc_dev.dv_xname, error); 569 } 570 571 } 572 573 esc->sc_slop_bgn_addr = *addr; 574 esc->sc_slop_bgn_size = slop_bgn_size; 575 esc->sc_slop_end_addr = (*addr+*dmasize)-slop_end_size; 576 esc->sc_slop_end_size = slop_end_size; 577 } 578 579 esc->sc_datain = datain; 580 581 return (0); 582 } 583 584 void 585 esp_dma_go(sc) 586 struct ncr53c9x_softc *sc; 587 { 588 struct esp_softc *esc = (struct esp_softc *)sc; 589 590 DPRINTF(("esp_dma_go(datain = %d)\n",esc->sc_datain)); 591 592 DPRINTF(("\tbgn slop = %d\n\tend slop = %d\n\tmapsize = %d\n", 593 esc->sc_slop_bgn_size,esc->sc_slop_end_size, 594 esc->sc_dmamap->dm_mapsize)); 595 596 DPRINTF(("esp fifo size = %d\n", 597 (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF))); 598 599 if (esc->sc_datain) { 600 NCR_WRITE_REG(sc, ESP_DCTL, 601 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 602 } else { 603 NCR_WRITE_REG(sc, ESP_DCTL, 604 ESPDCTL_20MHZ | ESPDCTL_INTENB); 605 } 606 607 if (esc->sc_datain) { 608 int i; 609 #ifdef DIAGNOSTIC 610 #if 0 /* This is a fine thing to happen */ 611 int n = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 612 if (n != esc->sc_slop_bgn_size) { 613 panic("%s: Unexpected data in fifo n = %d, expecting %d ", 614 sc->sc_dev.dv_xname, n, esc->sc_slop_bgn_size); 615 } 616 #endif 617 #endif 618 for(i=0;i<esc->sc_slop_bgn_size;i++) { 619 esc->sc_slop_bgn_addr[i]=NCR_READ_REG(sc, NCR_FIFO); 620 } 621 622 } else { 623 int i; 624 for(i=0;i<esc->sc_slop_bgn_size;i++) { 625 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_slop_bgn_addr[i]); 626 } 627 628 DPRINTF(("esp fifo size = %d\n", 629 (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF))); 630 } 631 632 if (esc->sc_dmamap->dm_mapsize != 0) { 633 if (esc->sc_datain) { 634 NCR_WRITE_REG(sc, ESP_DCTL, 635 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 636 } else { 637 NCR_WRITE_REG(sc, ESP_DCTL, 638 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 639 } 640 641 642 nextdma_start(&esc->sc_scsi_dma, 643 (esc->sc_datain ? DMACSR_READ : DMACSR_WRITE)); 644 } else { 645 #if defined(DIAGNOSTIC) 646 /* verify that end slop is 0, since the shutdown 647 * callback will not be called. 648 */ 649 if (esc->sc_slop_end_size != 0) { 650 panic("%s: Unexpected end slop with no DMA, slop = %d", 651 sc->sc_dev.dv_xname, esc->sc_slop_end_size); 652 } 653 #endif 654 #if 0 655 if (esc->sc_datain) { 656 NCR_WRITE_REG(sc, ESP_DCTL, 657 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD | ESPDCTL_FLUSH); 658 } else { 659 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 660 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_FLUSH); 661 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 662 } 663 #endif 664 665 esc->sc_datain = -1; 666 esc->sc_slop_bgn_addr = 0; 667 esc->sc_slop_bgn_size = 0; 668 esc->sc_slop_end_addr = 0; 669 esc->sc_slop_end_size = 0; 670 671 DPRINTF(("esp fifo size = %d\n", 672 (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF))); 673 } 674 } 675 676 void 677 esp_dma_stop(sc) 678 struct ncr53c9x_softc *sc; 679 { 680 panic("Not yet implemented"); 681 } 682 683 int 684 esp_dma_isactive(sc) 685 struct ncr53c9x_softc *sc; 686 { 687 struct esp_softc *esc = (struct esp_softc *)sc; 688 return( !nextdma_finished(&esc->sc_scsi_dma)); 689 } 690 691 /****************************************************************/ 692 693 /* Internal dma callback routines */ 694 bus_dmamap_t 695 esp_dmacb_continue(arg) 696 void *arg; 697 { 698 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 699 struct esp_softc *esc = (struct esp_softc *)sc; 700 701 DPRINTF(("esp dma continue\n")); 702 703 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap, 704 0, esc->sc_dmamap->dm_mapsize, 705 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 706 707 #ifdef DIAGNOSTIC 708 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 709 panic("%s: map not loaded in dma continue callback, datain = %d", 710 sc->sc_dev.dv_xname,esc->sc_datain); 711 } 712 #endif 713 714 if (esc->sc_dmamap_loaded == 0) { 715 esc->sc_dmamap_loaded++; 716 return(esc->sc_dmamap); 717 } else { 718 #ifdef DIAGNOSTIC 719 if (esc->sc_dmamap_loaded != 1) { 720 panic("%s: Unexpected sc_dmamap_loaded (%d) != 1 in continue_cb", 721 sc->sc_dev.dv_xname,esc->sc_dmamap_loaded); 722 } 723 #endif 724 return(0); 725 } 726 } 727 728 void 729 esp_dmacb_completed(map, arg) 730 bus_dmamap_t map; 731 void *arg; 732 { 733 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 734 struct esp_softc *esc = (struct esp_softc *)sc; 735 736 DPRINTF(("esp dma completed\n")); 737 738 #ifdef DIAGNOSTIC 739 if ((esc->sc_datain < 0) || 740 (esc->sc_datain > 1) || 741 (esc->sc_dmamap_loaded != 1)) { 742 panic("%s: map not loaded in dma completed callback, datain = %d, loaded = %d", 743 sc->sc_dev.dv_xname,esc->sc_datain,esc->sc_dmamap_loaded); 744 } 745 if (map != esc->sc_dmamap) { 746 panic("%s: unexpected tx completed map", sc->sc_dev.dv_xname); 747 } 748 #endif 749 750 /* @@@ Flush the fifo? */ 751 752 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap, 753 0, esc->sc_dmamap->dm_mapsize, 754 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 755 } 756 757 void 758 esp_dmacb_shutdown(arg) 759 void *arg; 760 { 761 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 762 struct esp_softc *esc = (struct esp_softc *)sc; 763 764 DPRINTF(("esp dma shutdown\n")); 765 766 #ifdef DIAGNOSTIC 767 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 768 panic("%s: map not loaded in dma shutdown callback, datain = %d", 769 sc->sc_dev.dv_xname,esc->sc_datain); 770 } 771 #endif 772 773 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap); 774 775 /* Stuff the end slop into fifo */ 776 777 { 778 if (esc->sc_datain) { 779 NCR_WRITE_REG(sc, ESP_DCTL, 780 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 781 } else { 782 NCR_WRITE_REG(sc, ESP_DCTL, 783 ESPDCTL_20MHZ | ESPDCTL_INTENB); 784 } 785 786 if (esc->sc_datain) { 787 int i; 788 #ifdef DIAGNOSTIC 789 #if 0 /* This is a fine thing to happen. */ 790 int n = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 791 if (n != esc->sc_slop_end_size) { 792 panic("%s: Unexpected data in fifo n = %d, expecting %d at end", 793 sc->sc_dev.dv_xname, n, esc->sc_slop_end_size); 794 } 795 #endif 796 #endif 797 for(i=0;i<esc->sc_slop_end_size;i++) { 798 esc->sc_slop_end_addr[i]=NCR_READ_REG(sc, NCR_FIFO); 799 } 800 801 } else { 802 int i; 803 for(i=0;i<esc->sc_slop_end_size;i++) { 804 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_slop_end_addr[i]); 805 } 806 } 807 } 808 809 810 esc->sc_datain = -1; 811 esc->sc_slop_bgn_addr = 0; 812 esc->sc_slop_bgn_size = 0; 813 esc->sc_slop_end_addr = 0; 814 esc->sc_slop_end_size = 0; 815 esc->sc_dmamap_loaded--; 816 #ifdef DIAGNOSTIC 817 if (esc->sc_dmamap_loaded != 0) { 818 panic("%s: Unexpected sc_dmamap_loaded (%d) != 0 in shutdown_cb", 819 sc->sc_dev.dv_xname,esc->sc_dmamap_loaded); 820 } 821 #endif 822 } 823
Indexes created Fri Sep 26 20:09:58 GMT 2025