esp.c revision 1.13
1 /* $NetBSD: esp.c,v 1.13 1998/12/30 12:02:03 dbj Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Grabbed from the sparc port at revision 1.73 for the NeXT. 81 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 82 */ 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/device.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 #include <sys/user.h> 94 #include <sys/queue.h> 95 96 #include <dev/scsipi/scsi_all.h> 97 #include <dev/scsipi/scsipi_all.h> 98 #include <dev/scsipi/scsiconf.h> 99 #include <dev/scsipi/scsi_message.h> 100 101 #include <machine/bus.h> 102 #include <machine/autoconf.h> 103 #include <machine/cpu.h> 104 105 #include <dev/ic/ncr53c9xreg.h> 106 #include <dev/ic/ncr53c9xvar.h> 107 108 #include <next68k/next68k/isr.h> 109 110 #include <next68k/dev/nextdmareg.h> 111 #include <next68k/dev/nextdmavar.h> 112 113 #include "espreg.h" 114 #include "espvar.h" 115 116 #if 1 117 #define ESP_DEBUG 118 #endif 119 120 #ifdef ESP_DEBUG 121 int esp_debug = 0; 122 #define DPRINTF(x) if (esp_debug) printf x; 123 #else 124 #define DPRINTF(x) 125 #endif 126 127 128 void espattach_intio __P((struct device *, struct device *, void *)); 129 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 130 131 /* DMA callbacks */ 132 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 133 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 134 void esp_dmacb_shutdown __P((void *arg)); 135 136 /* Linkup to the rest of the kernel */ 137 struct cfattach esp_ca = { 138 sizeof(struct esp_softc), espmatch_intio, espattach_intio 139 }; 140 141 struct scsipi_device esp_dev = { 142 NULL, /* Use default error handler */ 143 NULL, /* have a queue, served by this */ 144 NULL, /* have no async handler */ 145 NULL, /* Use default 'done' routine */ 146 }; 147 148 /* 149 * Functions and the switch for the MI code. 150 */ 151 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 152 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 153 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 154 void esp_dma_reset __P((struct ncr53c9x_softc *)); 155 int esp_dma_intr __P((struct ncr53c9x_softc *)); 156 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 157 size_t *, int, size_t *)); 158 void esp_dma_go __P((struct ncr53c9x_softc *)); 159 void esp_dma_stop __P((struct ncr53c9x_softc *)); 160 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 161 162 struct ncr53c9x_glue esp_glue = { 163 esp_read_reg, 164 esp_write_reg, 165 esp_dma_isintr, 166 esp_dma_reset, 167 esp_dma_intr, 168 esp_dma_setup, 169 esp_dma_go, 170 esp_dma_stop, 171 esp_dma_isactive, 172 NULL, /* gl_clear_latched_intr */ 173 }; 174 175 #ifdef ESP_DEBUG 176 #define XCHR(x) "0123456789abcdef"[(x) & 0xf] 177 static void 178 esp_hex_dump(unsigned char *pkt, size_t len) 179 { 180 size_t i, j; 181 182 printf("0000: "); 183 for(i=0; i<len; i++) { 184 printf("%c%c ", XCHR(pkt[i]>>4), XCHR(pkt[i])); 185 if ((i+1) % 16 == 0) { 186 printf(" %c", '"'); 187 for(j=0; j<16; j++) 188 printf("%c", pkt[i-15+j]>=32 && pkt[i-15+j]<127?pkt[i-15+j]:'.'); 189 printf("%c\n%c%c%c%c: ", '"', XCHR((i+1)>>12), 190 XCHR((i+1)>>8), XCHR((i+1)>>4), XCHR(i+1)); 191 } 192 } 193 printf("\n"); 194 } 195 #endif 196 197 int 198 espmatch_intio(parent, cf, aux) 199 struct device *parent; 200 struct cfdata *cf; 201 void *aux; 202 { 203 /* should probably probe here */ 204 /* Should also probably set up data from config */ 205 206 #if 1 207 /* this code isn't working yet, don't match on it */ 208 return(0); 209 #else 210 return(1); 211 #endif 212 } 213 214 void 215 espattach_intio(parent, self, aux) 216 struct device *parent, *self; 217 void *aux; 218 { 219 struct esp_softc *esc = (void *)self; 220 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 221 222 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 223 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 224 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 225 panic("\n%s: can't map ncr53c90 registers", 226 sc->sc_dev.dv_xname); 227 } 228 229 sc->sc_id = 7; 230 sc->sc_freq = 20; /* Mhz */ 231 232 /* 233 * Set up glue for MI code early; we use some of it here. 234 */ 235 sc->sc_glue = &esp_glue; 236 237 /* 238 * XXX More of this should be in ncr53c9x_attach(), but 239 * XXX should we really poke around the chip that much in 240 * XXX the MI code? Think about this more... 241 */ 242 243 /* 244 * It is necessary to try to load the 2nd config register here, 245 * to find out what rev the esp chip is, else the ncr53c9x_reset 246 * will not set up the defaults correctly. 247 */ 248 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 249 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 250 sc->sc_cfg3 = NCRCFG3_CDB; 251 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 252 253 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 254 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 255 sc->sc_rev = NCR_VARIANT_ESP100; 256 } else { 257 sc->sc_cfg2 = NCRCFG2_SCSI2; 258 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 259 sc->sc_cfg3 = 0; 260 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 261 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 262 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 263 if (NCR_READ_REG(sc, NCR_CFG3) != 264 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 265 sc->sc_rev = NCR_VARIANT_ESP100A; 266 } else { 267 /* NCRCFG2_FE enables > 64K transfers */ 268 sc->sc_cfg2 |= NCRCFG2_FE; 269 sc->sc_cfg3 = 0; 270 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 271 sc->sc_rev = NCR_VARIANT_ESP200; 272 } 273 } 274 275 /* 276 * XXX minsync and maxxfer _should_ be set up in MI code, 277 * XXX but it appears to have some dependency on what sort 278 * XXX of DMA we're hooked up to, etc. 279 */ 280 281 /* 282 * This is the value used to start sync negotiations 283 * Note that the NCR register "SYNCTP" is programmed 284 * in "clocks per byte", and has a minimum value of 4. 285 * The SCSI period used in negotiation is one-fourth 286 * of the time (in nanoseconds) needed to transfer one byte. 287 * Since the chip's clock is given in MHz, we have the following 288 * formula: 4 * period = (1000 / freq) * 4 289 */ 290 sc->sc_minsync = 1000 / sc->sc_freq; 291 292 /* 293 * Alas, we must now modify the value a bit, because it's 294 * only valid when can switch on FASTCLK and FASTSCSI bits 295 * in config register 3... 296 */ 297 switch (sc->sc_rev) { 298 case NCR_VARIANT_ESP100: 299 sc->sc_maxxfer = 64 * 1024; 300 sc->sc_minsync = 0; /* No synch on old chip? */ 301 break; 302 303 case NCR_VARIANT_ESP100A: 304 sc->sc_maxxfer = 64 * 1024; 305 /* Min clocks/byte is 5 */ 306 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 307 break; 308 309 case NCR_VARIANT_ESP200: 310 sc->sc_maxxfer = 16 * 1024 * 1024; 311 /* XXX - do actually set FAST* bits */ 312 break; 313 } 314 315 /* @@@ Some ESP_DCTL bits probably need setting */ 316 NCR_WRITE_REG(sc, ESP_DCTL, 317 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 318 DELAY(10); 319 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 320 DELAY(10); 321 322 /* Set up SCSI DMA */ 323 { 324 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 325 326 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 327 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 328 panic("\n%s: can't map scsi DMA registers", 329 sc->sc_dev.dv_xname); 330 } 331 332 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 333 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 334 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 335 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 336 esc->sc_scsi_dma.nd_cb_arg = sc; 337 nextdma_config(&esc->sc_scsi_dma); 338 nextdma_init(&esc->sc_scsi_dma); 339 340 { 341 int error; 342 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 343 sc->sc_maxxfer, 1, sc->sc_maxxfer, 344 0, BUS_DMA_ALLOCNOW, &esc->sc_dmamap)) != 0) { 345 panic("%s: can't create i/o DMA map, error = %d", 346 sc->sc_dev.dv_xname,error); 347 } 348 } 349 } 350 351 #if 0 352 /* Turn on target selection using the `dma' method */ 353 ncr53c9x_dmaselect = 1; 354 #else 355 ncr53c9x_dmaselect = 0; 356 #endif 357 358 esc->sc_slop_bgn_addr = 0; 359 esc->sc_slop_bgn_size = 0; 360 esc->sc_slop_end_addr = 0; 361 esc->sc_slop_end_size = 0; 362 esc->sc_datain = -1; 363 esc->sc_dmamap_loaded = 0; 364 365 /* Establish interrupt channel */ 366 isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc, 367 NEXT_I_IPL(NEXT_I_SCSI), 0); 368 INTR_ENABLE(NEXT_I_SCSI); 369 370 /* register interrupt stats */ 371 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 372 373 /* Do the common parts of attachment. */ 374 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 375 sc->sc_adapter.scsipi_minphys = minphys; 376 ncr53c9x_attach(sc, &esp_dev); 377 } 378 379 /* 380 * Glue functions. 381 */ 382 383 u_char 384 esp_read_reg(sc, reg) 385 struct ncr53c9x_softc *sc; 386 int reg; 387 { 388 struct esp_softc *esc = (struct esp_softc *)sc; 389 390 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 391 } 392 393 void 394 esp_write_reg(sc, reg, val) 395 struct ncr53c9x_softc *sc; 396 int reg; 397 u_char val; 398 { 399 struct esp_softc *esc = (struct esp_softc *)sc; 400 401 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 402 } 403 404 int 405 esp_dma_isintr(sc) 406 struct ncr53c9x_softc *sc; 407 { 408 struct esp_softc *esc = (struct esp_softc *)sc; 409 410 int r = (INTR_OCCURRED(NEXT_I_SCSI)); 411 412 if (r) { 413 int handled; 414 415 DPRINTF(("esp_dma_isintr = 0x%b\n", 416 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS)); 417 418 if (esp_dma_isactive(sc)) { 419 if (esc->sc_datain) { 420 NCR_WRITE_REG(sc, ESP_DCTL, 421 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD | ESPDCTL_FLUSH); 422 NCR_WRITE_REG(sc, ESP_DCTL, 423 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 424 } else { 425 NCR_WRITE_REG(sc, ESP_DCTL, 426 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_FLUSH); 427 NCR_WRITE_REG(sc, ESP_DCTL, 428 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 429 } 430 nextdma_intr(&esc->sc_scsi_dma); 431 return 0; 432 } 433 434 /* Clear the DMAMOD bit in the DCTL register, since if this 435 * routine returns true, then the ncr53c9x_intr handler will 436 * be called and needs access to the scsi registers. 437 */ 438 if (esc->sc_datain) { 439 NCR_WRITE_REG(sc, ESP_DCTL, 440 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 441 } else { 442 NCR_WRITE_REG(sc, ESP_DCTL, 443 ESPDCTL_20MHZ | ESPDCTL_INTENB); 444 } 445 446 } 447 448 return (r); 449 } 450 451 void 452 esp_dma_reset(sc) 453 struct ncr53c9x_softc *sc; 454 { 455 struct esp_softc *esc = (struct esp_softc *)sc; 456 457 DPRINTF(("esp dma reset\n")); 458 459 #ifdef ESP_DEBUG 460 if (esp_debug) { 461 printf(" *intrstat = 0x%b\n", 462 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS); 463 printf(" *intrmask = 0x%b\n", 464 (*(volatile u_long *)IIOV(NEXT_P_INTRMASK)),NEXT_INTR_BITS); 465 } 466 #endif 467 468 469 /* Clear the DMAMOD bit in the DCTL register: */ 470 if (esc->sc_datain) { 471 NCR_WRITE_REG(sc, ESP_DCTL, 472 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 473 } else { 474 NCR_WRITE_REG(sc, ESP_DCTL, 475 ESPDCTL_20MHZ | ESPDCTL_INTENB); 476 } 477 478 nextdma_reset(&esc->sc_scsi_dma); 479 480 #if 0 481 482 if (esc->sc_dmamap->dm_mapsize != 0) { 483 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap); 484 } 485 486 #else 487 488 if (esc->sc_dmamap_loaded) { 489 esp_dmacb_completed(esc->sc_dmamap,sc); 490 esp_dmacb_shutdown(sc); 491 } 492 493 #endif 494 495 esc->sc_slop_bgn_addr = 0; 496 esc->sc_slop_bgn_size = 0; 497 esc->sc_slop_end_addr = 0; 498 esc->sc_slop_end_size = 0; 499 esc->sc_datain = -1; 500 esc->sc_dmamap_loaded = 0; 501 502 } 503 504 int 505 esp_dma_intr(sc) 506 struct ncr53c9x_softc *sc; 507 { 508 int trans; 509 int resid; 510 int datain; 511 struct esp_softc *esc = (struct esp_softc *)sc; 512 513 datain = esc->sc_datain; 514 515 DPRINTF(("esp_dma_intr resetting dma\n")); 516 517 /* If the dma hasn't finished when we are in a scsi 518 * interrupt. Then, "Houston, we have a problem." 519 * Stop DMA and figure out how many bytes were transferred 520 */ 521 esp_dma_reset(sc); 522 523 resid = 0; 524 525 /* 526 * If a transfer onto the SCSI bus gets interrupted by the device 527 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 528 * as residual since the ESP counter registers get decremented as 529 * bytes are clocked into the FIFO. 530 */ 531 532 if (! datain) { 533 resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 534 if (resid) { 535 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 536 NCRCMD(sc, NCRCMD_FLUSH); 537 DELAY(1); 538 } 539 } 540 541 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 542 /* 543 * `Terminal count' is off, so read the residue 544 * out of the ESP counter registers. 545 */ 546 resid += (NCR_READ_REG(sc, NCR_TCL) | 547 (NCR_READ_REG(sc, NCR_TCM) << 8) | 548 ((sc->sc_cfg2 & NCRCFG2_FE) 549 ? (NCR_READ_REG(sc, NCR_TCH) << 16) 550 : 0)); 551 552 if (resid == 0 && esc->sc_dmasize == 65536 && 553 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 554 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 555 resid = 65536; 556 } 557 558 trans = esc->sc_dmasize - resid; 559 if (trans < 0) { /* transferred < 0 ? */ 560 #if 0 561 /* 562 * This situation can happen in perfectly normal operation 563 * if the ESP is reselected while using DMA to select 564 * another target. As such, don't print the warning. 565 */ 566 printf("%s: xfer (%d) > req (%d)\n", 567 esc->sc_dev.dv_xname, trans, esc->sc_dmasize); 568 #endif 569 trans = esc->sc_dmasize; 570 } 571 572 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 573 NCR_READ_REG(sc, NCR_TCL), 574 NCR_READ_REG(sc, NCR_TCM), 575 (sc->sc_cfg2 & NCRCFG2_FE) 576 ? NCR_READ_REG(sc, NCR_TCH) : 0, 577 trans, resid)); 578 579 #ifdef ESP_DEBUG 580 if (esp_debug) esp_hex_dump(*(esc->sc_dmaaddr),esc->sc_dmasize); 581 #endif 582 583 *esc->sc_dmalen -= trans; 584 *esc->sc_dmaaddr += trans; 585 586 return 0; 587 } 588 589 int 590 esp_dma_setup(sc, addr, len, datain, dmasize) 591 struct ncr53c9x_softc *sc; 592 caddr_t *addr; 593 size_t *len; 594 int datain; 595 size_t *dmasize; 596 { 597 struct esp_softc *esc = (struct esp_softc *)sc; 598 599 /* Save these in case we have to abort DMA */ 600 esc->sc_dmaaddr = addr; 601 esc->sc_dmalen = len; 602 #if 1 603 esc->sc_dmasize = DMA_ENDALIGN(caddr_t,*addr+*len)-*addr; 604 #else 605 esc->sc_dmasize = *dmasize; 606 #endif 607 608 #ifdef DIAGNOSTIC 609 /* if this is a read DMA, pre-fill the buffer with 0xdeadbeef 610 * to identify bogus reads 611 */ 612 if (datain) { 613 int *v = (int *)(*esc->sc_dmaaddr); 614 int i; 615 for(i=0;i<((*esc->sc_dmalen)/4);i++) v[i] = 0xdeadbeef; 616 } 617 #endif 618 619 DPRINTF(("esp_dma_setup(0x%08lx,0x%08lx,0x%08lx)\n",*esc->sc_dmaaddr,*esc->sc_dmalen,esc->sc_dmasize)); 620 621 #if 0 622 #ifdef DIAGNOSTIC /* @@@ this is ok sometimes. verify that we handle it ok 623 * and then remove this check 624 */ 625 if (*(esc->sc_dmalen) != esc->sc_dmasize) { 626 panic("esp dmalen != size"); 627 } 628 #endif 629 #endif 630 631 #ifdef DIAGNOSTIC 632 if ((esc->sc_datain != -1) || 633 (esc->sc_dmamap->dm_mapsize != 0) || 634 (esc->sc_dmamap_loaded != 0)) { 635 panic("%s: map already loaded in esp_dma_setup\n" 636 "\tdatain = %d\n\tmapsize=%d\n\tloaed = %d", 637 sc->sc_dev.dv_xname,esc->sc_datain,esc->sc_dmamap->dm_mapsize, 638 esc->sc_dmamap_loaded); 639 } 640 #endif 641 642 /* Deal with DMA alignment issues, by stuffing the FIFO. 643 * This assumes that if bus_dmamap_load is given an aligned 644 * buffer, then it will generate aligned hardware addresses 645 * to give to the device. Perhaps that is not a good assumption, 646 * but it is probably true. [dbj (at) netbsd.org:19980719.0135EDT] 647 */ 648 { 649 int slop_bgn_size; /* # bytes to be fifo'd at beginning */ 650 int slop_end_size; /* # bytes to be fifo'd at end */ 651 652 { 653 u_long bgn = (u_long)(*esc->sc_dmaaddr); 654 u_long end = (u_long)(*esc->sc_dmaaddr+esc->sc_dmasize); 655 656 slop_bgn_size = DMA_BEGINALIGNMENT-(bgn % DMA_BEGINALIGNMENT); 657 if (slop_bgn_size == DMA_BEGINALIGNMENT) slop_bgn_size = 0; 658 slop_end_size = end % DMA_ENDALIGNMENT; 659 } 660 661 /* Check to make sure we haven't counted extra slop 662 * as would happen for a very short dma buffer */ 663 if (slop_bgn_size+slop_end_size >= esc->sc_dmasize) { 664 665 slop_bgn_size = esc->sc_dmasize; 666 slop_end_size = 0; 667 668 } else { 669 int error; 670 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 671 esc->sc_dmamap, 672 *esc->sc_dmaaddr+slop_bgn_size, 673 esc->sc_dmasize-(slop_bgn_size+slop_end_size), 674 NULL, BUS_DMA_NOWAIT); 675 if (error) { 676 panic("%s: can't load dma map. error = %d", 677 sc->sc_dev.dv_xname, error); 678 } 679 680 } 681 682 esc->sc_slop_bgn_addr = *esc->sc_dmaaddr; 683 esc->sc_slop_bgn_size = slop_bgn_size; 684 esc->sc_slop_end_addr = (*esc->sc_dmaaddr+esc->sc_dmasize)-slop_end_size; 685 esc->sc_slop_end_size = slop_end_size; 686 } 687 688 esc->sc_datain = datain; 689 690 return (0); 691 } 692 693 void 694 esp_dma_go(sc) 695 struct ncr53c9x_softc *sc; 696 { 697 struct esp_softc *esc = (struct esp_softc *)sc; 698 699 DPRINTF(("esp_dma_go(datain = %d)\n",esc->sc_datain)); 700 701 DPRINTF(("\tbgn slop = %d\n\tend slop = %d\n\tmapsize = %d\n", 702 esc->sc_slop_bgn_size,esc->sc_slop_end_size, 703 esc->sc_dmamap->dm_mapsize)); 704 705 #ifdef DIAGNOSTIC 706 { 707 int n = NCR_READ_REG(sc, NCR_FFLAG); 708 DPRINTF(("esp fifo size = %d, seq = 0x%x\n",n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 709 } 710 #endif 711 712 if (esc->sc_datain) { 713 int i; 714 for(i=0;i<esc->sc_slop_bgn_size;i++) { 715 esc->sc_slop_bgn_addr[i]=NCR_READ_REG(sc, NCR_FIFO); 716 } 717 } else { 718 int i; 719 for(i=0;i<esc->sc_slop_bgn_size;i++) { 720 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_slop_bgn_addr[i]); 721 } 722 } 723 724 #ifdef DIAGNOSTIC 725 { 726 int n = NCR_READ_REG(sc, NCR_FFLAG); 727 DPRINTF(("esp fifo size = %d, seq = 0x%x\n",n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 728 } 729 #endif 730 731 if (esc->sc_dmamap->dm_mapsize != 0) { 732 733 nextdma_start(&esc->sc_scsi_dma, 734 (esc->sc_datain ? DMACSR_READ : DMACSR_WRITE)); 735 736 if (esc->sc_datain) { 737 NCR_WRITE_REG(sc, ESP_DCTL, 738 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 739 } else { 740 NCR_WRITE_REG(sc, ESP_DCTL, 741 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 742 } 743 744 745 } else { 746 747 panic("FIFO emulated DMA sequences not yet supported\n"); /* @@@ */ 748 749 #if defined(DIAGNOSTIC) 750 /* verify that end slop is 0, since the shutdown 751 * callback will not be called. 752 */ 753 if (esc->sc_slop_end_size != 0) { 754 panic("%s: Unexpected end slop with no DMA, slop = %d", 755 sc->sc_dev.dv_xname, esc->sc_slop_end_size); 756 } 757 #endif 758 759 esc->sc_datain = -1; 760 esc->sc_slop_bgn_addr = 0; 761 esc->sc_slop_bgn_size = 0; 762 esc->sc_slop_end_addr = 0; 763 esc->sc_slop_end_size = 0; 764 765 DPRINTF(("esp fifo size = %d\n", 766 (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF))); 767 } 768 } 769 770 void 771 esp_dma_stop(sc) 772 struct ncr53c9x_softc *sc; 773 { 774 panic("Not yet implemented"); 775 } 776 777 int 778 esp_dma_isactive(sc) 779 struct ncr53c9x_softc *sc; 780 { 781 struct esp_softc *esc = (struct esp_softc *)sc; 782 int r = !nextdma_finished(&esc->sc_scsi_dma); 783 DPRINTF(("esp_dma_isactive = %d\n",r)); 784 return(r); 785 } 786 787 /****************************************************************/ 788 789 /* Internal dma callback routines */ 790 bus_dmamap_t 791 esp_dmacb_continue(arg) 792 void *arg; 793 { 794 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 795 struct esp_softc *esc = (struct esp_softc *)sc; 796 797 DPRINTF(("esp dma continue\n")); 798 799 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap, 800 0, esc->sc_dmamap->dm_mapsize, 801 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 802 803 #ifdef DIAGNOSTIC 804 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 805 panic("%s: map not loaded in dma continue callback, datain = %d", 806 sc->sc_dev.dv_xname,esc->sc_datain); 807 } 808 #endif 809 810 if (esc->sc_dmamap_loaded == 0) { 811 esc->sc_dmamap_loaded++; 812 return(esc->sc_dmamap); 813 } else { 814 #ifdef DIAGNOSTIC 815 if (esc->sc_dmamap_loaded != 1) { 816 panic("%s: Unexpected sc_dmamap_loaded (%d) != 1 in continue_cb", 817 sc->sc_dev.dv_xname,esc->sc_dmamap_loaded); 818 } 819 #endif 820 return(0); 821 } 822 } 823 824 void 825 esp_dmacb_completed(map, arg) 826 bus_dmamap_t map; 827 void *arg; 828 { 829 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 830 struct esp_softc *esc = (struct esp_softc *)sc; 831 832 DPRINTF(("esp dma completed\n")); 833 834 #ifdef DIAGNOSTIC 835 if ((esc->sc_datain < 0) || 836 (esc->sc_datain > 1) || 837 (esc->sc_dmamap_loaded != 1)) { 838 panic("%s: map not loaded in dma completed callback, datain = %d, loaded = %d", 839 sc->sc_dev.dv_xname,esc->sc_datain,esc->sc_dmamap_loaded); 840 } 841 if (map != esc->sc_dmamap) { 842 panic("%s: unexpected tx completed map", sc->sc_dev.dv_xname); 843 } 844 #endif 845 846 /* @@@ Flush the fifo? */ 847 848 if (esc->sc_datain) { 849 NCR_WRITE_REG(sc, ESP_DCTL, 850 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 851 } else { 852 NCR_WRITE_REG(sc, ESP_DCTL, 853 ESPDCTL_20MHZ | ESPDCTL_INTENB); 854 } 855 856 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap, 857 0, esc->sc_dmamap->dm_mapsize, 858 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 859 860 if (esc->sc_datain) { 861 NCR_WRITE_REG(sc, ESP_DCTL, 862 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 863 } else { 864 NCR_WRITE_REG(sc, ESP_DCTL, 865 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 866 } 867 868 } 869 870 void 871 esp_dmacb_shutdown(arg) 872 void *arg; 873 { 874 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 875 struct esp_softc *esc = (struct esp_softc *)sc; 876 877 DPRINTF(("esp dma shutdown\n")); 878 879 #ifdef DIAGNOSTIC 880 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 881 panic("%s: map not loaded in dma shutdown callback, datain = %d", 882 sc->sc_dev.dv_xname,esc->sc_datain); 883 } 884 #endif 885 886 /* Stuff the end slop into fifo */ 887 888 #ifdef DIAGNOSTIC 889 { 890 int n = NCR_READ_REG(sc, NCR_FFLAG); 891 DPRINTF(("esp fifo size = %d, seq = 0x%x\n",n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 892 } 893 894 if (esp_debug) { 895 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d\n", 896 NCR_READ_REG(sc, NCR_TCL), 897 NCR_READ_REG(sc, NCR_TCM), 898 (sc->sc_cfg2 & NCRCFG2_FE) 899 ? NCR_READ_REG(sc, NCR_TCH) : 0)); 900 } 901 #endif 902 903 904 if (esc->sc_datain) { 905 NCR_WRITE_REG(sc, ESP_DCTL, 906 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 907 } else { 908 NCR_WRITE_REG(sc, ESP_DCTL, 909 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 910 } 911 912 { 913 914 if (esc->sc_datain) { 915 int i; 916 int r = NCR_READ_REG(sc, NCR_FFLAG); 917 int n = r & NCRFIFO_FF; 918 #ifdef DIAGNOSTIC 919 #if 0 /* 920 * This condition is ok. 921 * For example, scsi sense requests as much as might be available. 922 */ 923 int s = (r & NCRFIFO_SS) >> 5; 924 if (n != esc->sc_slop_end_size) { 925 panic("%s: Unexpected data in fifo n = %d, expecting %d at end. (seq = 0x%x)\n", 926 sc->sc_dev.dv_xname, n , esc->sc_slop_end_size, s); 927 } 928 #endif 929 #endif 930 for(i=0;i<esc->sc_slop_end_size;i++) { 931 esc->sc_slop_end_addr[i]=NCR_READ_REG(sc, NCR_FIFO); 932 } 933 934 } else { 935 int i; 936 for(i=0;i<esc->sc_slop_end_size;i++) { 937 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_slop_end_addr[i]); 938 } 939 } 940 } 941 942 if (esc->sc_datain) { 943 NCR_WRITE_REG(sc, ESP_DCTL, 944 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 945 } else { 946 NCR_WRITE_REG(sc, ESP_DCTL, 947 ESPDCTL_20MHZ | ESPDCTL_INTENB); 948 } 949 950 #ifdef DIAGNOSTIC 951 { 952 int n = NCR_READ_REG(sc, NCR_FFLAG); 953 DPRINTF(("esp fifo size = %d, seq = 0x%x\n",n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 954 } 955 #endif 956 957 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap); 958 959 #ifdef ESP_DEBUG 960 if (esp_debug) esp_hex_dump(*(esc->sc_dmaaddr),esc->sc_dmasize); 961 #endif 962 963 esc->sc_datain = -1; 964 esc->sc_slop_bgn_addr = 0; 965 esc->sc_slop_bgn_size = 0; 966 esc->sc_slop_end_addr = 0; 967 esc->sc_slop_end_size = 0; 968 esc->sc_dmamap_loaded--; 969 #ifdef DIAGNOSTIC 970 if (esc->sc_dmamap_loaded != 0) { 971 panic("%s: Unexpected sc_dmamap_loaded (%d) != 0 in shutdown_cb", 972 sc->sc_dev.dv_xname,esc->sc_dmamap_loaded); 973 } 974 #endif 975 } 976
Indexes created Tue Sep 23 22:09:46 GMT 2025