esp.c revision 1.18
1 /* $NetBSD: esp.c,v 1.18 1999/02/03 20:44:43 dbj Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Grabbed from the sparc port at revision 1.73 for the NeXT. 81 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 82 */ 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/device.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 #include <sys/user.h> 94 #include <sys/queue.h> 95 96 #include <dev/scsipi/scsi_all.h> 97 #include <dev/scsipi/scsipi_all.h> 98 #include <dev/scsipi/scsiconf.h> 99 #include <dev/scsipi/scsi_message.h> 100 101 #include <machine/bus.h> 102 #include <machine/autoconf.h> 103 #include <machine/cpu.h> 104 105 #include <dev/ic/ncr53c9xreg.h> 106 #include <dev/ic/ncr53c9xvar.h> 107 108 #include <next68k/next68k/isr.h> 109 110 #include <next68k/dev/nextdmareg.h> 111 #include <next68k/dev/nextdmavar.h> 112 113 #include "espreg.h" 114 #include "espvar.h" 115 116 #if 1 117 #define ESP_DEBUG 118 #endif 119 120 #ifdef ESP_DEBUG 121 int esp_debug = 0; 122 #define DPRINTF(x) if (esp_debug) printf x; 123 #else 124 #define DPRINTF(x) 125 #endif 126 127 128 void espattach_intio __P((struct device *, struct device *, void *)); 129 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 130 131 /* DMA callbacks */ 132 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 133 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 134 void esp_dmacb_shutdown __P((void *arg)); 135 136 /* Linkup to the rest of the kernel */ 137 struct cfattach esp_ca = { 138 sizeof(struct esp_softc), espmatch_intio, espattach_intio 139 }; 140 141 struct scsipi_device esp_dev = { 142 NULL, /* Use default error handler */ 143 NULL, /* have a queue, served by this */ 144 NULL, /* have no async handler */ 145 NULL, /* Use default 'done' routine */ 146 }; 147 148 /* 149 * Functions and the switch for the MI code. 150 */ 151 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 152 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 153 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 154 void esp_dma_reset __P((struct ncr53c9x_softc *)); 155 int esp_dma_intr __P((struct ncr53c9x_softc *)); 156 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 157 size_t *, int, size_t *)); 158 void esp_dma_go __P((struct ncr53c9x_softc *)); 159 void esp_dma_stop __P((struct ncr53c9x_softc *)); 160 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 161 162 struct ncr53c9x_glue esp_glue = { 163 esp_read_reg, 164 esp_write_reg, 165 esp_dma_isintr, 166 esp_dma_reset, 167 esp_dma_intr, 168 esp_dma_setup, 169 esp_dma_go, 170 esp_dma_stop, 171 esp_dma_isactive, 172 NULL, /* gl_clear_latched_intr */ 173 }; 174 175 #ifdef ESP_DEBUG 176 #define XCHR(x) "0123456789abcdef"[(x) & 0xf] 177 static void 178 esp_hex_dump(unsigned char *pkt, size_t len) 179 { 180 size_t i, j; 181 182 printf("0000: "); 183 for(i=0; i<len; i++) { 184 printf("%c%c ", XCHR(pkt[i]>>4), XCHR(pkt[i])); 185 if ((i+1) % 16 == 0) { 186 printf(" %c", '"'); 187 for(j=0; j<16; j++) 188 printf("%c", pkt[i-15+j]>=32 && pkt[i-15+j]<127?pkt[i-15+j]:'.'); 189 printf("%c\n%c%c%c%c: ", '"', XCHR((i+1)>>12), 190 XCHR((i+1)>>8), XCHR((i+1)>>4), XCHR(i+1)); 191 } 192 } 193 printf("\n"); 194 } 195 #endif 196 197 int 198 espmatch_intio(parent, cf, aux) 199 struct device *parent; 200 struct cfdata *cf; 201 void *aux; 202 { 203 /* should probably probe here */ 204 /* Should also probably set up data from config */ 205 206 return(1); 207 } 208 209 void 210 espattach_intio(parent, self, aux) 211 struct device *parent, *self; 212 void *aux; 213 { 214 struct esp_softc *esc = (void *)self; 215 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 216 217 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 218 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 219 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 220 panic("\n%s: can't map ncr53c90 registers", 221 sc->sc_dev.dv_xname); 222 } 223 224 sc->sc_id = 7; 225 sc->sc_freq = 20; /* Mhz */ 226 227 /* 228 * Set up glue for MI code early; we use some of it here. 229 */ 230 sc->sc_glue = &esp_glue; 231 232 /* 233 * XXX More of this should be in ncr53c9x_attach(), but 234 * XXX should we really poke around the chip that much in 235 * XXX the MI code? Think about this more... 236 */ 237 238 /* 239 * It is necessary to try to load the 2nd config register here, 240 * to find out what rev the esp chip is, else the ncr53c9x_reset 241 * will not set up the defaults correctly. 242 */ 243 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 244 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 245 sc->sc_cfg3 = NCRCFG3_CDB; 246 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 247 248 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 249 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 250 sc->sc_rev = NCR_VARIANT_ESP100; 251 } else { 252 sc->sc_cfg2 = NCRCFG2_SCSI2; 253 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 254 sc->sc_cfg3 = 0; 255 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 256 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 257 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 258 if (NCR_READ_REG(sc, NCR_CFG3) != 259 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 260 sc->sc_rev = NCR_VARIANT_ESP100A; 261 } else { 262 /* NCRCFG2_FE enables > 64K transfers */ 263 sc->sc_cfg2 |= NCRCFG2_FE; 264 sc->sc_cfg3 = 0; 265 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 266 sc->sc_rev = NCR_VARIANT_ESP200; 267 } 268 } 269 270 /* 271 * XXX minsync and maxxfer _should_ be set up in MI code, 272 * XXX but it appears to have some dependency on what sort 273 * XXX of DMA we're hooked up to, etc. 274 */ 275 276 /* 277 * This is the value used to start sync negotiations 278 * Note that the NCR register "SYNCTP" is programmed 279 * in "clocks per byte", and has a minimum value of 4. 280 * The SCSI period used in negotiation is one-fourth 281 * of the time (in nanoseconds) needed to transfer one byte. 282 * Since the chip's clock is given in MHz, we have the following 283 * formula: 4 * period = (1000 / freq) * 4 284 */ 285 sc->sc_minsync = 1000 / sc->sc_freq; 286 287 /* 288 * Alas, we must now modify the value a bit, because it's 289 * only valid when can switch on FASTCLK and FASTSCSI bits 290 * in config register 3... 291 */ 292 switch (sc->sc_rev) { 293 case NCR_VARIANT_ESP100: 294 sc->sc_maxxfer = 64 * 1024; 295 sc->sc_minsync = 0; /* No synch on old chip? */ 296 break; 297 298 case NCR_VARIANT_ESP100A: 299 sc->sc_maxxfer = 64 * 1024; 300 /* Min clocks/byte is 5 */ 301 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 302 break; 303 304 case NCR_VARIANT_ESP200: 305 sc->sc_maxxfer = 16 * 1024 * 1024; 306 /* XXX - do actually set FAST* bits */ 307 break; 308 } 309 310 /* @@@ Some ESP_DCTL bits probably need setting */ 311 NCR_WRITE_REG(sc, ESP_DCTL, 312 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 313 DELAY(10); 314 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 315 DELAY(10); 316 317 /* Set up SCSI DMA */ 318 { 319 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 320 321 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 322 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 323 panic("\n%s: can't map scsi DMA registers", 324 sc->sc_dev.dv_xname); 325 } 326 327 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 328 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 329 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 330 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 331 esc->sc_scsi_dma.nd_cb_arg = sc; 332 nextdma_config(&esc->sc_scsi_dma); 333 nextdma_init(&esc->sc_scsi_dma); 334 335 #if 0 336 /* Turn on target selection using the `dma' method */ 337 ncr53c9x_dmaselect = 1; 338 #else 339 ncr53c9x_dmaselect = 0; 340 #endif 341 342 esc->sc_datain = -1; 343 esc->sc_dmaaddr = 0; 344 esc->sc_dmalen = 0; 345 esc->sc_dmasize = -1; 346 347 esc->sc_loaded = 0; 348 349 esc->sc_begin = 0; 350 esc->sc_begin_size = 0; 351 352 { 353 int error; 354 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 355 sc->sc_maxxfer, 1, sc->sc_maxxfer, 356 0, BUS_DMA_ALLOCNOW, &esc->sc_main_dmamap)) != 0) { 357 panic("%s: can't create main i/o DMA map, error = %d", 358 sc->sc_dev.dv_xname,error); 359 } 360 } 361 esc->sc_main = 0; 362 esc->sc_main_size = 0; 363 364 { 365 int error; 366 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 367 ESP_DMA_MAXTAIL, 1, ESP_DMA_MAXTAIL, 368 0, BUS_DMA_ALLOCNOW, &esc->sc_tail_dmamap)) != 0) { 369 panic("%s: can't create tail i/o DMA map, error = %d", 370 sc->sc_dev.dv_xname,error); 371 } 372 } 373 esc->sc_tail = 0; 374 esc->sc_tail_size = 0; 375 376 } 377 378 /* Establish interrupt channel */ 379 isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc, 380 NEXT_I_IPL(NEXT_I_SCSI), 0); 381 INTR_ENABLE(NEXT_I_SCSI); 382 383 /* register interrupt stats */ 384 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 385 386 /* Do the common parts of attachment. */ 387 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 388 sc->sc_adapter.scsipi_minphys = minphys; 389 ncr53c9x_attach(sc, &esp_dev); 390 } 391 392 /* 393 * Glue functions. 394 */ 395 396 u_char 397 esp_read_reg(sc, reg) 398 struct ncr53c9x_softc *sc; 399 int reg; 400 { 401 struct esp_softc *esc = (struct esp_softc *)sc; 402 403 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 404 } 405 406 void 407 esp_write_reg(sc, reg, val) 408 struct ncr53c9x_softc *sc; 409 int reg; 410 u_char val; 411 { 412 struct esp_softc *esc = (struct esp_softc *)sc; 413 414 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 415 } 416 417 int 418 esp_dma_isintr(sc) 419 struct ncr53c9x_softc *sc; 420 { 421 struct esp_softc *esc = (struct esp_softc *)sc; 422 423 int r = (INTR_OCCURRED(NEXT_I_SCSI)); 424 425 if (r) { 426 DPRINTF(("esp_dma_isintr = 0x%b\n", 427 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS)); 428 429 while (esp_dma_isactive(sc)) { 430 431 #ifdef DIAGNOSTIC 432 r = (INTR_OCCURRED(NEXT_I_SCSI)); 433 if (!r) panic("esp dma enabled but failed to flush"); 434 #endif 435 436 if (esc->sc_datain) { 437 NCR_WRITE_REG(sc, ESP_DCTL, 438 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD | ESPDCTL_FLUSH); 439 NCR_WRITE_REG(sc, ESP_DCTL, 440 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 441 } else { 442 NCR_WRITE_REG(sc, ESP_DCTL, 443 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_FLUSH); 444 NCR_WRITE_REG(sc, ESP_DCTL, 445 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 446 } 447 { 448 int nr; 449 nr = nextdma_intr(&esc->sc_scsi_dma); 450 if (nr) { 451 DPRINTF(("nextma_intr = %d\n",nr)); 452 } 453 } 454 } 455 456 /* Clear the DMAMOD bit in the DCTL register, since if this 457 * routine returns true, then the ncr53c9x_intr handler will 458 * be called and needs access to the scsi registers. 459 */ 460 if (esc->sc_datain) { 461 NCR_WRITE_REG(sc, ESP_DCTL, 462 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 463 } else { 464 NCR_WRITE_REG(sc, ESP_DCTL, 465 ESPDCTL_20MHZ | ESPDCTL_INTENB); 466 } 467 468 } 469 470 return (r); 471 } 472 473 void 474 esp_dma_reset(sc) 475 struct ncr53c9x_softc *sc; 476 { 477 struct esp_softc *esc = (struct esp_softc *)sc; 478 479 DPRINTF(("esp dma reset\n")); 480 481 #ifdef ESP_DEBUG 482 if (esp_debug) { 483 printf(" *intrstat = 0x%b\n", 484 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS); 485 printf(" *intrmask = 0x%b\n", 486 (*(volatile u_long *)IIOV(NEXT_P_INTRMASK)),NEXT_INTR_BITS); 487 } 488 #endif 489 490 /* Clear the DMAMOD bit in the DCTL register: */ 491 NCR_WRITE_REG(sc, ESP_DCTL, 492 ESPDCTL_20MHZ | ESPDCTL_INTENB); 493 494 nextdma_reset(&esc->sc_scsi_dma); 495 496 esc->sc_datain = -1; 497 esc->sc_dmaaddr = 0; 498 esc->sc_dmalen = 0; 499 esc->sc_dmasize = -1; 500 501 esc->sc_loaded = 0; 502 503 esc->sc_begin = 0; 504 esc->sc_begin_size = 0; 505 506 if (esc->sc_main_dmamap->dm_mapsize) { 507 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 508 } 509 esc->sc_main = 0; 510 esc->sc_main_size = 0; 511 512 if (esc->sc_tail_dmamap->dm_mapsize) { 513 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 514 } 515 esc->sc_tail = 0; 516 esc->sc_tail_size = 0; 517 } 518 519 int 520 esp_dma_intr(sc) 521 struct ncr53c9x_softc *sc; 522 { 523 #ifdef DIAGNOSTIC 524 panic("%s: esp_dma_intr shouldn't be invoked.\n", sc->sc_dev.dv_xname); 525 #endif 526 527 return -1; 528 } 529 530 int 531 esp_dma_setup(sc, addr, len, datain, dmasize) 532 struct ncr53c9x_softc *sc; 533 caddr_t *addr; 534 size_t *len; 535 int datain; 536 size_t *dmasize; 537 { 538 struct esp_softc *esc = (struct esp_softc *)sc; 539 540 #ifdef DIAGNOSTIC 541 /* if this is a read DMA, pre-fill the buffer with 0xdeadbeef 542 * to identify bogus reads 543 */ 544 if (datain) { 545 int *v = (int *)(*addr); 546 int i; 547 for(i=0;i<((*len)/4);i++) v[i] = 0xdeadbeef; 548 v = (int *)(&(esc->sc_tailbuf[0])); 549 for(i=0;i<((sizeof(esc->sc_tailbuf)/4));i++) v[i] = 0xdeaffeed; 550 } 551 552 #endif 553 554 DPRINTF(("esp_dma_setup(0x%08lx,0x%08lx,0x%08lx)\n",*addr,*len,*dmasize)); 555 556 #ifdef DIAGNOSTIC /* @@@ this is ok sometimes. verify that we handle it ok 557 * and then remove this check 558 */ 559 if (*len != *dmasize) { 560 panic("esp dmalen != size"); 561 } 562 #endif 563 564 #ifdef DIAGNOSTIC 565 if ((esc->sc_datain != -1) || 566 (esc->sc_main_dmamap->dm_mapsize != 0) || 567 (esc->sc_tail_dmamap->dm_mapsize != 0)) { 568 panic("%s: map already loaded in esp_dma_setup\n" 569 "\tdatain = %d\n\tmain_mapsize=%d\n\tail_mapsize=%d", 570 sc->sc_dev.dv_xname, esc->sc_datain, 571 esc->sc_main_dmamap->dm_mapsize,esc->sc_tail_dmamap->dm_mapsize); 572 } 573 #endif 574 575 /* Save these in case we have to abort DMA */ 576 esc->sc_datain = datain; 577 esc->sc_dmaaddr = addr; 578 esc->sc_dmalen = len; 579 esc->sc_dmasize = *dmasize; 580 581 esc->sc_loaded = 0; 582 583 { 584 size_t slop_bgn_size; /* # bytes to be fifo'd at beginning */ 585 size_t slop_end_size; /* # bytes to be transferred in tail buffer */ 586 587 { 588 u_long bgn = (u_long)(*esc->sc_dmaaddr); 589 u_long end = (u_long)(*esc->sc_dmaaddr+esc->sc_dmasize); 590 591 slop_bgn_size = DMA_BEGINALIGNMENT-(bgn % DMA_BEGINALIGNMENT); 592 if (slop_bgn_size == DMA_BEGINALIGNMENT) slop_bgn_size = 0; 593 slop_end_size = end % DMA_ENDALIGNMENT; 594 } 595 596 /* Check to make sure we haven't counted extra slop 597 * as would happen for a very short dma buffer, also 598 * for short buffers, just stuff the entire thing in the tail 599 */ 600 if ((slop_bgn_size+slop_end_size >= esc->sc_dmasize) 601 #if 1 602 || (esc->sc_dmasize <= ESP_DMA_MAXTAIL) 603 #endif 604 ) 605 { 606 slop_bgn_size = 0; 607 slop_end_size = esc->sc_dmasize; 608 } 609 610 /* initialize the fifo buffer */ 611 if (slop_bgn_size) { 612 esc->sc_begin = *esc->sc_dmaaddr; 613 esc->sc_begin_size = slop_bgn_size; 614 } else { 615 esc->sc_begin = 0; 616 esc->sc_begin_size = 0; 617 } 618 619 /* Load the normal DMA map */ 620 { 621 esc->sc_main = *esc->sc_dmaaddr+slop_bgn_size; 622 esc->sc_main_size = (esc->sc_dmasize)-(slop_end_size+slop_bgn_size); 623 624 if (esc->sc_main_size) { 625 int error; 626 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 627 esc->sc_main_dmamap, 628 esc->sc_main, esc->sc_main_size, 629 NULL, BUS_DMA_NOWAIT); 630 if (error) { 631 panic("%s: can't load main dma map. error = %d, addr=0x%08x, size=0x%08x", 632 sc->sc_dev.dv_xname, error,esc->sc_main,esc->sc_main_size); 633 } 634 } else { 635 esc->sc_main = 0; 636 } 637 } 638 639 /* Load the tail DMA map */ 640 if (slop_end_size) { 641 esc->sc_tail = DMA_ENDALIGN(caddr_t,esc->sc_tailbuf+slop_end_size)-slop_end_size; 642 /* If the beginning of the tail is not correctly aligned, 643 * we have no choice but to align the start, which might then unalign the end. 644 */ 645 esc->sc_tail = DMA_ALIGN(caddr_t,esc->sc_tail); 646 /* So therefore, we change the tail size to be end aligned again. */ 647 esc->sc_tail_size = DMA_ENDALIGN(caddr_t,esc->sc_tail+slop_end_size)-esc->sc_tail; 648 649 { 650 int error; 651 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 652 esc->sc_tail_dmamap, 653 esc->sc_tail, esc->sc_tail_size, 654 NULL, BUS_DMA_NOWAIT); 655 if (error) { 656 panic("%s: can't load tail dma map. error = %d, addr=0x%08x, size=0x%08x", 657 sc->sc_dev.dv_xname, error,esc->sc_tail,esc->sc_tail_size); 658 } 659 } 660 } 661 } 662 663 return (0); 664 } 665 666 void 667 esp_dma_go(sc) 668 struct ncr53c9x_softc *sc; 669 { 670 struct esp_softc *esc = (struct esp_softc *)sc; 671 672 DPRINTF(("%s: esp_dma_go(datain = %d)\n", 673 sc->sc_dev.dv_xname, esc->sc_datain)); 674 675 DPRINTF(("%s: dma_shutdown: addr=0x%08lx,len=0x%08lx,size=0x%08lx\n", 676 sc->sc_dev.dv_xname, 677 *esc->sc_dmaaddr, *esc->sc_dmalen, esc->sc_dmasize)); 678 679 DPRINTF(("%s: begin = 0x%08x, size = 0x%08x\n", 680 sc->sc_dev.dv_xname, esc->sc_begin, esc->sc_begin_size)); 681 DPRINTF(("%s: main = 0x%08x, size = 0x%08x\n", 682 sc->sc_dev.dv_xname, esc->sc_main, esc->sc_main_size)); 683 DPRINTF(("%s: tail = 0x%08x, size = 0x%08x\n", 684 sc->sc_dev.dv_xname, esc->sc_tail, esc->sc_tail_size)); 685 686 #ifdef DIAGNOSTIC 687 { 688 int n = NCR_READ_REG(sc, NCR_FFLAG); 689 DPRINTF(("esp fifo size = %d, seq = 0x%x\n",n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 690 } 691 #endif 692 693 #if defined(DIAGNOSTIC) 694 if ((esc->sc_begin_size == 0) && 695 (esc->sc_main_dmamap->dm_mapsize == 0) && 696 (esc->sc_tail_dmamap->dm_mapsize == 0)) { 697 panic("%s: No DMA requested!",sc->sc_dev.dv_xname); 698 } 699 #endif 700 701 /* Stuff the fifo with the begin buffer */ 702 if (esc->sc_datain) { 703 int i; 704 for(i=0;i<esc->sc_begin_size;i++) { 705 esc->sc_begin[i]=NCR_READ_REG(sc, NCR_FIFO); 706 } 707 } else { 708 int i; 709 for(i=0;i<esc->sc_begin_size;i++) { 710 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_begin[i]); 711 } 712 } 713 714 /* if we are a dma write cycle, copy the end slop */ 715 if (esc->sc_datain == 0) { 716 memcpy(esc->sc_tail, 717 (*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size), 718 (esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size))); 719 } 720 721 nextdma_start(&esc->sc_scsi_dma, 722 (esc->sc_datain ? DMACSR_READ : DMACSR_WRITE)); 723 724 if (esc->sc_datain) { 725 NCR_WRITE_REG(sc, ESP_DCTL, 726 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 727 } else { 728 NCR_WRITE_REG(sc, ESP_DCTL, 729 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 730 } 731 732 } 733 734 void 735 esp_dma_stop(sc) 736 struct ncr53c9x_softc *sc; 737 { 738 panic("Not yet implemented"); 739 } 740 741 int 742 esp_dma_isactive(sc) 743 struct ncr53c9x_softc *sc; 744 { 745 struct esp_softc *esc = (struct esp_softc *)sc; 746 int r = !nextdma_finished(&esc->sc_scsi_dma); 747 DPRINTF(("esp_dma_isactive = %d\n",r)); 748 return(r); 749 } 750 751 /****************************************************************/ 752 753 /* Internal dma callback routines */ 754 bus_dmamap_t 755 esp_dmacb_continue(arg) 756 void *arg; 757 { 758 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 759 struct esp_softc *esc = (struct esp_softc *)sc; 760 761 DPRINTF(("%s: dma continue\n",sc->sc_dev.dv_xname)); 762 763 #ifdef DIAGNOSTIC 764 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 765 panic("%s: map not loaded in dma continue callback, datain = %d", 766 sc->sc_dev.dv_xname,esc->sc_datain); 767 } 768 #endif 769 770 if ((!(esc->sc_loaded & ESP_LOADED_MAIN)) && 771 (esc->sc_main_dmamap->dm_mapsize)) { 772 DPRINTF(("%s: Loading main map\n",sc->sc_dev.dv_xname)); 773 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 774 0, esc->sc_main_dmamap->dm_mapsize, 775 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 776 esc->sc_loaded |= ESP_LOADED_MAIN; 777 return(esc->sc_main_dmamap); 778 } 779 780 if ((!(esc->sc_loaded & ESP_LOADED_TAIL)) && 781 (esc->sc_tail_dmamap->dm_mapsize)) { 782 DPRINTF(("%s: Loading tail map\n",sc->sc_dev.dv_xname)); 783 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 784 0, esc->sc_tail_dmamap->dm_mapsize, 785 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 786 esc->sc_loaded |= ESP_LOADED_TAIL; 787 return(esc->sc_tail_dmamap); 788 } 789 790 DPRINTF(("%s: not loading map\n",sc->sc_dev.dv_xname)); 791 return(0); 792 } 793 794 795 void 796 esp_dmacb_completed(map, arg) 797 bus_dmamap_t map; 798 void *arg; 799 { 800 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 801 struct esp_softc *esc = (struct esp_softc *)sc; 802 803 DPRINTF(("esp dma completed\n")); 804 805 #ifdef DIAGNOSTIC 806 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 807 panic("%s: invalid dma direction in completed callback, datain = %d", 808 sc->sc_dev.dv_xname,esc->sc_datain); 809 } 810 if ((map != esc->sc_main_dmamap) && (map != esc->sc_tail_dmamap)) { 811 panic("%s: unexpected completed map", sc->sc_dev.dv_xname); 812 } 813 #endif 814 815 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, map, 816 0, map->dm_mapsize, 817 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 818 819 } 820 821 void 822 esp_dmacb_shutdown(arg) 823 void *arg; 824 { 825 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 826 struct esp_softc *esc = (struct esp_softc *)sc; 827 828 DPRINTF(("esp dma shutdown\n")); 829 830 /* Stuff the end slop into fifo */ 831 832 #ifdef ESP_DEBUG 833 if (esp_debug) { 834 835 int n = NCR_READ_REG(sc, NCR_FFLAG); 836 DPRINTF(("esp fifo size = %d, seq = 0x%x\n",n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 837 838 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d\n", 839 NCR_READ_REG(sc, NCR_TCL), 840 NCR_READ_REG(sc, NCR_TCM), 841 (sc->sc_cfg2 & NCRCFG2_FE) 842 ? NCR_READ_REG(sc, NCR_TCH) : 0)); 843 } 844 #endif 845 846 /* First copy the tail dma buffer data for read transfers */ 847 if (esc->sc_datain == 1) { 848 memcpy((*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size), 849 esc->sc_tail, 850 (esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size))); 851 } 852 853 #ifdef ESP_DEBUG 854 if (esp_debug) { 855 printf("%s: dma_shutdown: addr=0x%08lx,len=0x%08lx,size=0x%08lx\n", 856 sc->sc_dev.dv_xname, 857 *esc->sc_dmaaddr, *esc->sc_dmalen, esc->sc_dmasize); 858 esp_hex_dump(*(esc->sc_dmaaddr),esc->sc_dmasize); 859 printf("%s: tail=0x%08lx,tailbuf=0x%08lx,tail_size=0x%08lx\n", 860 sc->sc_dev.dv_xname, 861 esc->sc_tail, &(esc->sc_tailbuf[0]), esc->sc_tail_size); 862 esp_hex_dump(&(esc->sc_tailbuf[0]),sizeof(esc->sc_tailbuf)); 863 } 864 #endif 865 866 esc->sc_datain = -1; 867 esc->sc_dmaaddr = 0; 868 esc->sc_dmalen = 0; 869 esc->sc_dmasize = -1; 870 871 esc->sc_loaded = 0; 872 873 esc->sc_begin = 0; 874 esc->sc_begin_size = 0; 875 876 if (esc->sc_main_dmamap->dm_mapsize) { 877 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 878 } 879 esc->sc_main = 0; 880 esc->sc_main_size = 0; 881 882 if (esc->sc_tail_dmamap->dm_mapsize) { 883 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 884 } 885 esc->sc_tail = 0; 886 esc->sc_tail_size = 0; 887 888 } 889
Indexes created Wed Sep 24 02:09:48 GMT 2025