esp.c revision 1.19
1 /* $NetBSD: esp.c,v 1.19 1999/02/13 09:44:50 dbj Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Grabbed from the sparc port at revision 1.73 for the NeXT. 81 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 82 */ 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/device.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 #include <sys/user.h> 94 #include <sys/queue.h> 95 96 #include <dev/scsipi/scsi_all.h> 97 #include <dev/scsipi/scsipi_all.h> 98 #include <dev/scsipi/scsiconf.h> 99 #include <dev/scsipi/scsi_message.h> 100 101 #include <machine/bus.h> 102 #include <machine/autoconf.h> 103 #include <machine/cpu.h> 104 105 #include <dev/ic/ncr53c9xreg.h> 106 #include <dev/ic/ncr53c9xvar.h> 107 108 #include <next68k/next68k/isr.h> 109 110 #include <next68k/dev/nextdmareg.h> 111 #include <next68k/dev/nextdmavar.h> 112 113 #include "espreg.h" 114 #include "espvar.h" 115 116 #if 1 117 #define ESP_DEBUG 118 #endif 119 120 #ifdef ESP_DEBUG 121 int esp_debug = 0; 122 #define DPRINTF(x) if (esp_debug) printf x; 123 #else 124 #define DPRINTF(x) 125 #endif 126 127 128 void espattach_intio __P((struct device *, struct device *, void *)); 129 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 130 131 /* DMA callbacks */ 132 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 133 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 134 void esp_dmacb_shutdown __P((void *arg)); 135 136 /* Linkup to the rest of the kernel */ 137 struct cfattach esp_ca = { 138 sizeof(struct esp_softc), espmatch_intio, espattach_intio 139 }; 140 141 struct scsipi_device esp_dev = { 142 NULL, /* Use default error handler */ 143 NULL, /* have a queue, served by this */ 144 NULL, /* have no async handler */ 145 NULL, /* Use default 'done' routine */ 146 }; 147 148 /* 149 * Functions and the switch for the MI code. 150 */ 151 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 152 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 153 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 154 void esp_dma_reset __P((struct ncr53c9x_softc *)); 155 int esp_dma_intr __P((struct ncr53c9x_softc *)); 156 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 157 size_t *, int, size_t *)); 158 void esp_dma_go __P((struct ncr53c9x_softc *)); 159 void esp_dma_stop __P((struct ncr53c9x_softc *)); 160 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 161 162 struct ncr53c9x_glue esp_glue = { 163 esp_read_reg, 164 esp_write_reg, 165 esp_dma_isintr, 166 esp_dma_reset, 167 esp_dma_intr, 168 esp_dma_setup, 169 esp_dma_go, 170 esp_dma_stop, 171 esp_dma_isactive, 172 NULL, /* gl_clear_latched_intr */ 173 }; 174 175 #ifdef ESP_DEBUG 176 #define XCHR(x) "0123456789abcdef"[(x) & 0xf] 177 static void 178 esp_hex_dump(unsigned char *pkt, size_t len) 179 { 180 size_t i, j; 181 182 printf("0000: "); 183 for(i=0; i<len; i++) { 184 printf("%c%c ", XCHR(pkt[i]>>4), XCHR(pkt[i])); 185 if ((i+1) % 16 == 0) { 186 printf(" %c", '"'); 187 for(j=0; j<16; j++) 188 printf("%c", pkt[i-15+j]>=32 && pkt[i-15+j]<127?pkt[i-15+j]:'.'); 189 printf("%c\n%c%c%c%c: ", '"', XCHR((i+1)>>12), 190 XCHR((i+1)>>8), XCHR((i+1)>>4), XCHR(i+1)); 191 } 192 } 193 printf("\n"); 194 } 195 #endif 196 197 int 198 espmatch_intio(parent, cf, aux) 199 struct device *parent; 200 struct cfdata *cf; 201 void *aux; 202 { 203 /* should probably probe here */ 204 /* Should also probably set up data from config */ 205 206 return(1); 207 } 208 209 void 210 espattach_intio(parent, self, aux) 211 struct device *parent, *self; 212 void *aux; 213 { 214 struct esp_softc *esc = (void *)self; 215 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 216 217 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 218 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 219 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 220 panic("\n%s: can't map ncr53c90 registers", 221 sc->sc_dev.dv_xname); 222 } 223 224 sc->sc_id = 7; 225 sc->sc_freq = 20; /* Mhz */ 226 227 /* 228 * Set up glue for MI code early; we use some of it here. 229 */ 230 sc->sc_glue = &esp_glue; 231 232 /* 233 * XXX More of this should be in ncr53c9x_attach(), but 234 * XXX should we really poke around the chip that much in 235 * XXX the MI code? Think about this more... 236 */ 237 238 /* 239 * It is necessary to try to load the 2nd config register here, 240 * to find out what rev the esp chip is, else the ncr53c9x_reset 241 * will not set up the defaults correctly. 242 */ 243 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 244 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 245 sc->sc_cfg3 = NCRCFG3_CDB; 246 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 247 248 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 249 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 250 sc->sc_rev = NCR_VARIANT_ESP100; 251 } else { 252 sc->sc_cfg2 = NCRCFG2_SCSI2; 253 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 254 sc->sc_cfg3 = 0; 255 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 256 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 257 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 258 if (NCR_READ_REG(sc, NCR_CFG3) != 259 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 260 sc->sc_rev = NCR_VARIANT_ESP100A; 261 } else { 262 /* NCRCFG2_FE enables > 64K transfers */ 263 sc->sc_cfg2 |= NCRCFG2_FE; 264 sc->sc_cfg3 = 0; 265 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 266 sc->sc_rev = NCR_VARIANT_ESP200; 267 } 268 } 269 270 /* 271 * XXX minsync and maxxfer _should_ be set up in MI code, 272 * XXX but it appears to have some dependency on what sort 273 * XXX of DMA we're hooked up to, etc. 274 */ 275 276 /* 277 * This is the value used to start sync negotiations 278 * Note that the NCR register "SYNCTP" is programmed 279 * in "clocks per byte", and has a minimum value of 4. 280 * The SCSI period used in negotiation is one-fourth 281 * of the time (in nanoseconds) needed to transfer one byte. 282 * Since the chip's clock is given in MHz, we have the following 283 * formula: 4 * period = (1000 / freq) * 4 284 */ 285 sc->sc_minsync = 1000 / sc->sc_freq; 286 287 /* 288 * Alas, we must now modify the value a bit, because it's 289 * only valid when can switch on FASTCLK and FASTSCSI bits 290 * in config register 3... 291 */ 292 switch (sc->sc_rev) { 293 case NCR_VARIANT_ESP100: 294 sc->sc_maxxfer = 64 * 1024; 295 sc->sc_minsync = 0; /* No synch on old chip? */ 296 break; 297 298 case NCR_VARIANT_ESP100A: 299 sc->sc_maxxfer = 64 * 1024; 300 /* Min clocks/byte is 5 */ 301 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 302 break; 303 304 case NCR_VARIANT_ESP200: 305 sc->sc_maxxfer = 16 * 1024 * 1024; 306 /* XXX - do actually set FAST* bits */ 307 break; 308 } 309 310 /* @@@ Some ESP_DCTL bits probably need setting */ 311 NCR_WRITE_REG(sc, ESP_DCTL, 312 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 313 DELAY(10); 314 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 315 DELAY(10); 316 317 /* Set up SCSI DMA */ 318 { 319 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 320 321 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 322 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 323 panic("\n%s: can't map scsi DMA registers", 324 sc->sc_dev.dv_xname); 325 } 326 327 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 328 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 329 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 330 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 331 esc->sc_scsi_dma.nd_cb_arg = sc; 332 nextdma_config(&esc->sc_scsi_dma); 333 nextdma_init(&esc->sc_scsi_dma); 334 335 #if 0 336 /* Turn on target selection using the `dma' method */ 337 ncr53c9x_dmaselect = 1; 338 #else 339 ncr53c9x_dmaselect = 0; 340 #endif 341 342 esc->sc_datain = -1; 343 esc->sc_dmaaddr = 0; 344 esc->sc_dmalen = 0; 345 esc->sc_dmasize = -1; 346 347 esc->sc_loaded = 0; 348 349 esc->sc_begin = 0; 350 esc->sc_begin_size = 0; 351 352 { 353 int error; 354 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 355 sc->sc_maxxfer, sc->sc_maxxfer/NBPG, sc->sc_maxxfer, 356 0, BUS_DMA_ALLOCNOW, &esc->sc_main_dmamap)) != 0) { 357 panic("%s: can't create main i/o DMA map, error = %d", 358 sc->sc_dev.dv_xname,error); 359 } 360 } 361 esc->sc_main = 0; 362 esc->sc_main_size = 0; 363 364 { 365 int error; 366 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 367 ESP_DMA_TAILBUFSIZE, 368 1, ESP_DMA_TAILBUFSIZE, 369 0, BUS_DMA_ALLOCNOW, &esc->sc_tail_dmamap)) != 0) { 370 panic("%s: can't create tail i/o DMA map, error = %d", 371 sc->sc_dev.dv_xname,error); 372 } 373 } 374 esc->sc_tail = 0; 375 esc->sc_tail_size = 0; 376 377 } 378 379 /* Establish interrupt channel */ 380 isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc, 381 NEXT_I_IPL(NEXT_I_SCSI), -1); 382 INTR_ENABLE(NEXT_I_SCSI); 383 384 /* register interrupt stats */ 385 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 386 387 /* Do the common parts of attachment. */ 388 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 389 sc->sc_adapter.scsipi_minphys = minphys; 390 ncr53c9x_attach(sc, &esp_dev); 391 } 392 393 /* 394 * Glue functions. 395 */ 396 397 u_char 398 esp_read_reg(sc, reg) 399 struct ncr53c9x_softc *sc; 400 int reg; 401 { 402 struct esp_softc *esc = (struct esp_softc *)sc; 403 404 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 405 } 406 407 void 408 esp_write_reg(sc, reg, val) 409 struct ncr53c9x_softc *sc; 410 int reg; 411 u_char val; 412 { 413 struct esp_softc *esc = (struct esp_softc *)sc; 414 415 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 416 } 417 418 int 419 esp_dma_isintr(sc) 420 struct ncr53c9x_softc *sc; 421 { 422 struct esp_softc *esc = (struct esp_softc *)sc; 423 424 int r = (INTR_OCCURRED(NEXT_I_SCSI)); 425 426 if (r) { 427 DPRINTF(("esp_dma_isintr = 0x%b\n", 428 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS)); 429 430 while (esp_dma_isactive(sc)) { 431 432 #ifdef DIAGNOSTIC 433 r = (INTR_OCCURRED(NEXT_I_SCSI)); 434 if (!r) panic("esp dma enabled but failed to flush"); 435 #endif 436 437 if (esc->sc_datain) { 438 NCR_WRITE_REG(sc, ESP_DCTL, 439 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD | ESPDCTL_FLUSH); 440 NCR_WRITE_REG(sc, ESP_DCTL, 441 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 442 } else { 443 NCR_WRITE_REG(sc, ESP_DCTL, 444 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_FLUSH); 445 NCR_WRITE_REG(sc, ESP_DCTL, 446 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 447 } 448 { 449 int nr; 450 nr = nextdma_intr(&esc->sc_scsi_dma); 451 if (nr) { 452 DPRINTF(("nextma_intr = %d\n",nr)); 453 } 454 } 455 } 456 457 /* Clear the DMAMOD bit in the DCTL register, since if this 458 * routine returns true, then the ncr53c9x_intr handler will 459 * be called and needs access to the scsi registers. 460 */ 461 if (esc->sc_datain) { 462 NCR_WRITE_REG(sc, ESP_DCTL, 463 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 464 } else { 465 NCR_WRITE_REG(sc, ESP_DCTL, 466 ESPDCTL_20MHZ | ESPDCTL_INTENB); 467 } 468 469 } 470 471 return (r); 472 } 473 474 void 475 esp_dma_reset(sc) 476 struct ncr53c9x_softc *sc; 477 { 478 struct esp_softc *esc = (struct esp_softc *)sc; 479 480 DPRINTF(("esp dma reset\n")); 481 482 #ifdef ESP_DEBUG 483 if (esp_debug) { 484 printf(" *intrstat = 0x%b\n", 485 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS); 486 printf(" *intrmask = 0x%b\n", 487 (*(volatile u_long *)IIOV(NEXT_P_INTRMASK)),NEXT_INTR_BITS); 488 } 489 #endif 490 491 /* Clear the DMAMOD bit in the DCTL register: */ 492 NCR_WRITE_REG(sc, ESP_DCTL, 493 ESPDCTL_20MHZ | ESPDCTL_INTENB); 494 495 nextdma_reset(&esc->sc_scsi_dma); 496 497 esc->sc_datain = -1; 498 esc->sc_dmaaddr = 0; 499 esc->sc_dmalen = 0; 500 esc->sc_dmasize = -1; 501 502 esc->sc_loaded = 0; 503 504 esc->sc_begin = 0; 505 esc->sc_begin_size = 0; 506 507 if (esc->sc_main_dmamap->dm_mapsize) { 508 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 509 } 510 esc->sc_main = 0; 511 esc->sc_main_size = 0; 512 513 if (esc->sc_tail_dmamap->dm_mapsize) { 514 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 515 } 516 esc->sc_tail = 0; 517 esc->sc_tail_size = 0; 518 } 519 520 int 521 esp_dma_intr(sc) 522 struct ncr53c9x_softc *sc; 523 { 524 #ifdef DIAGNOSTIC 525 panic("%s: esp_dma_intr shouldn't be invoked.\n", sc->sc_dev.dv_xname); 526 #endif 527 528 return -1; 529 } 530 531 /* it appears that: 532 * addr and len arguments to this need to be kept up to date 533 * with the status of the transfter. 534 * the dmasize of this is the actual length of the transfer 535 * request, which is guaranteed to be less than maxxfer. 536 * (len may be > maxxfer) 537 */ 538 539 int 540 esp_dma_setup(sc, addr, len, datain, dmasize) 541 struct ncr53c9x_softc *sc; 542 caddr_t *addr; 543 size_t *len; 544 int datain; 545 size_t *dmasize; 546 { 547 struct esp_softc *esc = (struct esp_softc *)sc; 548 549 #ifdef DIAGNOSTIC 550 /* if this is a read DMA, pre-fill the buffer with 0xdeadbeef 551 * to identify bogus reads 552 */ 553 if (datain) { 554 int *v = (int *)(*addr); 555 int i; 556 for(i=0;i<((*len)/4);i++) v[i] = 0xdeadbeef; 557 v = (int *)(&(esc->sc_tailbuf[0])); 558 for(i=0;i<((sizeof(esc->sc_tailbuf)/4));i++) v[i] = 0xdeaffeed; 559 } 560 561 #endif 562 563 DPRINTF(("esp_dma_setup(0x%08lx,0x%08lx,0x%08lx)\n",*addr,*len,*dmasize)); 564 565 #ifdef DIAGNOSTIC /* @@@ this is ok sometimes. verify that we handle it ok 566 * and then remove this check 567 */ 568 if (*len != *dmasize) { 569 panic("esp dmalen != size"); 570 } 571 #endif 572 573 #ifdef DIAGNOSTIC 574 if ((esc->sc_datain != -1) || 575 (esc->sc_main_dmamap->dm_mapsize != 0) || 576 (esc->sc_tail_dmamap->dm_mapsize != 0)) { 577 panic("%s: map already loaded in esp_dma_setup\n" 578 "\tdatain = %d\n\tmain_mapsize=%d\n\tail_mapsize=%d", 579 sc->sc_dev.dv_xname, esc->sc_datain, 580 esc->sc_main_dmamap->dm_mapsize,esc->sc_tail_dmamap->dm_mapsize); 581 } 582 #endif 583 584 /* Save these in case we have to abort DMA */ 585 esc->sc_datain = datain; 586 esc->sc_dmaaddr = addr; 587 esc->sc_dmalen = len; 588 esc->sc_dmasize = *dmasize; 589 590 esc->sc_loaded = 0; 591 592 { 593 size_t slop_bgn_size; /* # bytes to be fifo'd at beginning */ 594 size_t slop_end_size; /* # bytes to be transferred in tail buffer */ 595 596 { 597 u_long bgn = (u_long)(*esc->sc_dmaaddr); 598 u_long end = (u_long)(*esc->sc_dmaaddr+esc->sc_dmasize); 599 600 slop_bgn_size = DMA_BEGINALIGNMENT-(bgn % DMA_BEGINALIGNMENT); 601 if (slop_bgn_size == DMA_BEGINALIGNMENT) slop_bgn_size = 0; 602 slop_end_size = (end % DMA_ENDALIGNMENT); 603 } 604 605 /* Force a minimum slop end size to guarantee correct use of tailbuf 606 * and provide for dma overrun 607 */ 608 slop_end_size += ESP_DMA_MAXTAIL; 609 610 611 /* Check to make sure we haven't counted extra slop 612 * as would happen for a very short dma buffer, also 613 * for short buffers, just stuff the entire thing in the tail 614 */ 615 if ((slop_bgn_size+slop_end_size >= esc->sc_dmasize) 616 #if 1 617 || (esc->sc_dmasize <= ESP_DMA_MAXTAIL) 618 #endif 619 ) 620 { 621 slop_bgn_size = 0; 622 slop_end_size = esc->sc_dmasize; 623 } 624 625 /* initialize the fifo buffer */ 626 if (slop_bgn_size) { 627 esc->sc_begin = *esc->sc_dmaaddr; 628 esc->sc_begin_size = slop_bgn_size; 629 } else { 630 esc->sc_begin = 0; 631 esc->sc_begin_size = 0; 632 } 633 634 /* Load the normal DMA map */ 635 { 636 esc->sc_main = *esc->sc_dmaaddr+slop_bgn_size; 637 esc->sc_main_size = (esc->sc_dmasize)-(slop_end_size+slop_bgn_size); 638 639 if (esc->sc_main_size) { 640 int error; 641 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 642 esc->sc_main_dmamap, 643 esc->sc_main, esc->sc_main_size, 644 NULL, BUS_DMA_NOWAIT); 645 if (error) { 646 panic("%s: can't load main dma map. error = %d, addr=0x%08x, size=0x%08x", 647 sc->sc_dev.dv_xname, error,esc->sc_main,esc->sc_main_size); 648 } 649 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 650 0, esc->sc_main_dmamap->dm_mapsize, 651 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 652 } else { 653 esc->sc_main = 0; 654 } 655 } 656 657 /* Load the tail DMA map */ 658 if (slop_end_size) { 659 esc->sc_tail = DMA_ENDALIGN(caddr_t,esc->sc_tailbuf+slop_end_size)-slop_end_size; 660 /* If the beginning of the tail is not correctly aligned, 661 * we have no choice but to align the start, which might then unalign the end. 662 */ 663 esc->sc_tail = DMA_ALIGN(caddr_t,esc->sc_tail); 664 /* So therefore, we change the tail size to be end aligned again. */ 665 esc->sc_tail_size = DMA_ENDALIGN(caddr_t,esc->sc_tail+slop_end_size)-esc->sc_tail; 666 667 /* @@@ next dma overrun lossage */ 668 if (!esc->sc_datain) esc->sc_tail_size += ESP_DMA_OVERRUN; 669 670 { 671 int error; 672 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 673 esc->sc_tail_dmamap, 674 esc->sc_tail, esc->sc_tail_size, 675 NULL, BUS_DMA_NOWAIT); 676 if (error) { 677 panic("%s: can't load tail dma map. error = %d, addr=0x%08x, size=0x%08x", 678 sc->sc_dev.dv_xname, error,esc->sc_tail,esc->sc_tail_size); 679 } 680 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 681 0, esc->sc_tail_dmamap->dm_mapsize, 682 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 683 } 684 } 685 } 686 687 return (0); 688 } 689 690 void 691 esp_dma_go(sc) 692 struct ncr53c9x_softc *sc; 693 { 694 struct esp_softc *esc = (struct esp_softc *)sc; 695 696 #ifdef DEBUG 697 698 DPRINTF(("%s: esp_dma_go(datain = %d)\n", 699 sc->sc_dev.dv_xname, esc->sc_datain)); 700 701 DPRINTF(("%s: dma_shutdown: addr=0x%08lx,len=0x%08lx,size=0x%08lx\n", 702 sc->sc_dev.dv_xname, 703 *esc->sc_dmaaddr, *esc->sc_dmalen, esc->sc_dmasize)); 704 705 DPRINTF(("%s: begin = 0x%08x, size = 0x%08x\n", 706 sc->sc_dev.dv_xname, esc->sc_begin, esc->sc_begin_size)); 707 DPRINTF(("%s: main = 0x%08x, size = 0x%08x\n", 708 sc->sc_dev.dv_xname, esc->sc_main, esc->sc_main_size)); 709 { 710 int i; 711 bus_dmamap_t map = esc->sc_main_dmamap; 712 DPRINTF(("%s: main map. mapsize = 0x%08x, nsegs = %d\n", 713 sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs)); 714 for(i=0;i<map->dm_nsegs;i++) { 715 DPRINTF(("%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n", 716 sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len)); 717 } 718 } 719 DPRINTF(("%s: tail = 0x%08x, size = 0x%08x\n", 720 sc->sc_dev.dv_xname, esc->sc_tail, esc->sc_tail_size)); 721 { 722 int i; 723 bus_dmamap_t map = esc->sc_tail_dmamap; 724 DPRINTF(("%s: tail map. mapsize = 0x%08x, nsegs = %d\n", 725 sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs)); 726 for(i=0;i<map->dm_nsegs;i++) { 727 DPRINTF(("%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n", 728 sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len)); 729 } 730 } 731 #endif 732 733 #ifdef DIAGNOSTIC 734 { 735 int n = NCR_READ_REG(sc, NCR_FFLAG); 736 DPRINTF(("esp fifo size = %d, seq = 0x%x\n",n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 737 } 738 #endif 739 740 #if defined(DIAGNOSTIC) 741 if ((esc->sc_begin_size == 0) && 742 (esc->sc_main_dmamap->dm_mapsize == 0) && 743 (esc->sc_tail_dmamap->dm_mapsize == 0)) { 744 panic("%s: No DMA requested!",sc->sc_dev.dv_xname); 745 } 746 #endif 747 748 /* Stuff the fifo with the begin buffer */ 749 if (esc->sc_datain) { 750 int i; 751 for(i=0;i<esc->sc_begin_size;i++) { 752 esc->sc_begin[i]=NCR_READ_REG(sc, NCR_FIFO); 753 } 754 } else { 755 int i; 756 for(i=0;i<esc->sc_begin_size;i++) { 757 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_begin[i]); 758 } 759 } 760 761 /* if we are a dma write cycle, copy the end slop */ 762 if (esc->sc_datain == 0) { 763 memcpy(esc->sc_tail, 764 (*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size), 765 (esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size))); 766 } 767 768 nextdma_start(&esc->sc_scsi_dma, 769 (esc->sc_datain ? DMACSR_READ : DMACSR_WRITE)); 770 771 if (esc->sc_datain) { 772 NCR_WRITE_REG(sc, ESP_DCTL, 773 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 774 } else { 775 NCR_WRITE_REG(sc, ESP_DCTL, 776 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 777 } 778 779 } 780 781 void 782 esp_dma_stop(sc) 783 struct ncr53c9x_softc *sc; 784 { 785 panic("Not yet implemented"); 786 } 787 788 int 789 esp_dma_isactive(sc) 790 struct ncr53c9x_softc *sc; 791 { 792 struct esp_softc *esc = (struct esp_softc *)sc; 793 int r = !nextdma_finished(&esc->sc_scsi_dma); 794 DPRINTF(("esp_dma_isactive = %d\n",r)); 795 return(r); 796 } 797 798 /****************************************************************/ 799 800 /* Internal dma callback routines */ 801 bus_dmamap_t 802 esp_dmacb_continue(arg) 803 void *arg; 804 { 805 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 806 struct esp_softc *esc = (struct esp_softc *)sc; 807 808 DPRINTF(("%s: dma continue\n",sc->sc_dev.dv_xname)); 809 810 #ifdef DIAGNOSTIC 811 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 812 panic("%s: map not loaded in dma continue callback, datain = %d", 813 sc->sc_dev.dv_xname,esc->sc_datain); 814 } 815 #endif 816 817 if ((!(esc->sc_loaded & ESP_LOADED_MAIN)) && 818 (esc->sc_main_dmamap->dm_mapsize)) { 819 DPRINTF(("%s: Loading main map\n",sc->sc_dev.dv_xname)); 820 #if 0 821 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 822 0, esc->sc_main_dmamap->dm_mapsize, 823 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 824 #endif 825 esc->sc_loaded |= ESP_LOADED_MAIN; 826 return(esc->sc_main_dmamap); 827 } 828 829 if ((!(esc->sc_loaded & ESP_LOADED_TAIL)) && 830 (esc->sc_tail_dmamap->dm_mapsize)) { 831 DPRINTF(("%s: Loading tail map\n",sc->sc_dev.dv_xname)); 832 #if 0 833 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 834 0, esc->sc_tail_dmamap->dm_mapsize, 835 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 836 #endif 837 esc->sc_loaded |= ESP_LOADED_TAIL; 838 return(esc->sc_tail_dmamap); 839 } 840 841 DPRINTF(("%s: not loading map\n",sc->sc_dev.dv_xname)); 842 return(0); 843 } 844 845 846 void 847 esp_dmacb_completed(map, arg) 848 bus_dmamap_t map; 849 void *arg; 850 { 851 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 852 struct esp_softc *esc = (struct esp_softc *)sc; 853 854 DPRINTF(("esp dma completed\n")); 855 856 #ifdef DIAGNOSTIC 857 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 858 panic("%s: invalid dma direction in completed callback, datain = %d", 859 sc->sc_dev.dv_xname,esc->sc_datain); 860 } 861 if ((map != esc->sc_main_dmamap) && (map != esc->sc_tail_dmamap)) { 862 panic("%s: unexpected completed map", sc->sc_dev.dv_xname); 863 } 864 #endif 865 866 #if 0 867 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, map, 868 0, map->dm_mapsize, 869 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 870 #endif 871 872 } 873 874 void 875 esp_dmacb_shutdown(arg) 876 void *arg; 877 { 878 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 879 struct esp_softc *esc = (struct esp_softc *)sc; 880 881 DPRINTF(("esp dma shutdown\n")); 882 883 /* Stuff the end slop into fifo */ 884 885 #ifdef ESP_DEBUG 886 if (esp_debug) { 887 888 int n = NCR_READ_REG(sc, NCR_FFLAG); 889 DPRINTF(("esp fifo size = %d, seq = 0x%x\n",n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 890 891 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d\n", 892 NCR_READ_REG(sc, NCR_TCL), 893 NCR_READ_REG(sc, NCR_TCM), 894 (sc->sc_cfg2 & NCRCFG2_FE) 895 ? NCR_READ_REG(sc, NCR_TCH) : 0)); 896 } 897 #endif 898 899 /* First copy the tail dma buffer data for read transfers */ 900 if (esc->sc_datain == 1) { 901 memcpy((*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size), 902 esc->sc_tail, 903 (esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size))); 904 } 905 906 *(esc->sc_dmaaddr) += esc->sc_dmasize; 907 *(esc->sc_dmalen) -= esc->sc_dmasize; 908 909 #ifdef ESP_DEBUG 910 if (esp_debug) { 911 printf("%s: dma_shutdown: addr=0x%08lx,len=0x%08lx,size=0x%08lx\n", 912 sc->sc_dev.dv_xname, 913 *esc->sc_dmaaddr, *esc->sc_dmalen, esc->sc_dmasize); 914 esp_hex_dump(*(esc->sc_dmaaddr),esc->sc_dmasize); 915 printf("%s: tail=0x%08lx,tailbuf=0x%08lx,tail_size=0x%08lx\n", 916 sc->sc_dev.dv_xname, 917 esc->sc_tail, &(esc->sc_tailbuf[0]), esc->sc_tail_size); 918 esp_hex_dump(&(esc->sc_tailbuf[0]),sizeof(esc->sc_tailbuf)); 919 } 920 #endif 921 922 if (esc->sc_main_dmamap->dm_mapsize) { 923 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 924 0, esc->sc_main_dmamap->dm_mapsize, 925 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 926 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 927 } 928 esc->sc_main = 0; 929 esc->sc_main_size = 0; 930 931 if (esc->sc_tail_dmamap->dm_mapsize) { 932 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 933 0, esc->sc_tail_dmamap->dm_mapsize, 934 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 935 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 936 } 937 esc->sc_tail = 0; 938 esc->sc_tail_size = 0; 939 940 esc->sc_datain = -1; 941 esc->sc_dmaaddr = 0; 942 esc->sc_dmalen = 0; 943 esc->sc_dmasize = -1; 944 945 esc->sc_loaded = 0; 946 947 esc->sc_begin = 0; 948 esc->sc_begin_size = 0; 949 950 } 951
Indexes created Fri Sep 26 20:09:58 GMT 2025