esp.c revision 1.2
1 /* $NetBSD: esp.c,v 1.2 1998/07/13 04:01:39 dbj Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Charles M. Hannum. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * Copyright (c) 1994 Peter Galbavy 71 * Copyright (c) 1995 Paul Kranenburg 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 3. All advertising materials mentioning features or use of this software 83 * must display the following acknowledgement: 84 * This product includes software developed by Peter Galbavy 85 * 4. The name of the author may not be used to endorse or promote products 86 * derived from this software without specific prior written permission. 87 * 88 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 89 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 90 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 91 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 92 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 93 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 94 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 95 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 96 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 97 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 98 * POSSIBILITY OF SUCH DAMAGE. 99 */ 100 101 /* 102 * Based on aic6360 by Jarle Greipsland 103 * 104 * Acknowledgements: Many of the algorithms used in this driver are 105 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 106 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 107 */ 108 109 /* 110 * Grabbed from the sparc port at revision 1.73 for the NeXT. 111 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 112 */ 113 114 #include <sys/types.h> 115 #include <sys/param.h> 116 #include <sys/systm.h> 117 #include <sys/kernel.h> 118 #include <sys/errno.h> 119 #include <sys/ioctl.h> 120 #include <sys/device.h> 121 #include <sys/buf.h> 122 #include <sys/proc.h> 123 #include <sys/user.h> 124 #include <sys/queue.h> 125 126 #include <dev/scsipi/scsi_all.h> 127 #include <dev/scsipi/scsipi_all.h> 128 #include <dev/scsipi/scsiconf.h> 129 #include <dev/scsipi/scsi_message.h> 130 131 #include <machine/bus.h> 132 #include <machine/autoconf.h> 133 #include <machine/cpu.h> 134 135 #include <dev/ic/ncr53c9xreg.h> 136 #include <dev/ic/ncr53c9xvar.h> 137 138 #include <next68k/next68k/isr.h> 139 140 #include <next68k/dev/nextdmareg.h> 141 #include <next68k/dev/nextdmavar.h> 142 143 #include "espreg.h" 144 #include "espvar.h" 145 146 void espattach_intio __P((struct device *, struct device *, void *)); 147 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 148 149 /* DMA callbacks */ 150 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 151 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 152 void esp_dmacb_shutdown __P((void *arg)); 153 154 void espattach __P((struct esp_softc *)); 155 156 /* Linkup to the rest of the kernel */ 157 struct cfattach esp_ca = { 158 sizeof(struct esp_softc), espmatch_intio, espattach_intio 159 }; 160 161 struct scsipi_adapter esp_switch = { 162 ncr53c9x_scsi_cmd, 163 minphys, /* no max at this level; handled by DMA code */ 164 NULL, 165 NULL, 166 }; 167 168 struct scsipi_device esp_dev = { 169 NULL, /* Use default error handler */ 170 NULL, /* have a queue, served by this */ 171 NULL, /* have no async handler */ 172 NULL, /* Use default 'done' routine */ 173 }; 174 175 /* 176 * Functions and the switch for the MI code. 177 */ 178 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 179 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 180 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 181 void esp_dma_reset __P((struct ncr53c9x_softc *)); 182 int esp_dma_intr __P((struct ncr53c9x_softc *)); 183 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 184 size_t *, int, size_t *)); 185 void esp_dma_go __P((struct ncr53c9x_softc *)); 186 void esp_dma_stop __P((struct ncr53c9x_softc *)); 187 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 188 189 struct ncr53c9x_glue esp_glue = { 190 esp_read_reg, 191 esp_write_reg, 192 esp_dma_isintr, 193 esp_dma_reset, 194 esp_dma_intr, 195 esp_dma_setup, 196 esp_dma_go, 197 esp_dma_stop, 198 esp_dma_isactive, 199 NULL, /* gl_clear_latched_intr */ 200 }; 201 202 int 203 espmatch_intio(parent, cf, aux) 204 struct device *parent; 205 struct cfdata *cf; 206 void *aux; 207 { 208 /* should probably probe here */ 209 /* Should also probably set up data from config */ 210 211 /* this code isn't working yet, don't match on it */ 212 return(0); 213 } 214 215 void 216 espattach_intio(parent, self, aux) 217 struct device *parent, *self; 218 void *aux; 219 { 220 struct esp_softc *esc = (void *)self; 221 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 222 223 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 224 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 225 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 226 panic("\n%s: can't map ncr53c90 registers\n", 227 sc->sc_dev.dv_xname); 228 } 229 230 sc->sc_id = 7; 231 sc->sc_freq = 20; /* Mhz */ 232 233 /* @@@ Some ESP_DCTL bits probably need setting */ 234 235 /* Set up SCSI DMA */ 236 { 237 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 238 239 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 240 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 241 panic("\n%s: can't map scsi DMA registers\n", 242 sc->sc_dev.dv_xname); 243 } 244 245 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 246 esc->sc_scsi_dma.nd_chaining_flag = 0; 247 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 248 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 249 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 250 esc->sc_scsi_dma.nd_cb_arg = sc; 251 nextdma_config(&esc->sc_scsi_dma); 252 nextdma_init(&esc->sc_scsi_dma); 253 254 /* @@@ maxxfer is not set yet here */ 255 { 256 int error; 257 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 258 sc->sc_maxxfer, 1, sc->sc_maxxfer, 259 0, BUS_DMA_ALLOCNOW, &esc->sc_dmamap)) != 0) { 260 panic("%s: can't create i/o DMA map, error = %d\n", 261 sc->sc_dev.dv_xname,error); 262 } 263 } 264 265 espattach(esc); 266 } 267 } 268 269 /* 270 * Attach this instance, and then all the sub-devices 271 */ 272 void 273 espattach(esc) 274 struct esp_softc *esc; 275 { 276 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 277 278 /* 279 * Set up glue for MI code early; we use some of it here. 280 */ 281 sc->sc_glue = &esp_glue; 282 283 /* 284 * XXX More of this should be in ncr53c9x_attach(), but 285 * XXX should we really poke around the chip that much in 286 * XXX the MI code? Think about this more... 287 */ 288 289 /* 290 * It is necessary to try to load the 2nd config register here, 291 * to find out what rev the esp chip is, else the ncr53c9x_reset 292 * will not set up the defaults correctly. 293 */ 294 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 295 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 296 sc->sc_cfg3 = NCRCFG3_CDB; 297 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 298 299 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 300 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 301 sc->sc_rev = NCR_VARIANT_ESP100; 302 } else { 303 sc->sc_cfg2 = NCRCFG2_SCSI2; 304 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 305 sc->sc_cfg3 = 0; 306 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 307 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 308 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 309 if (NCR_READ_REG(sc, NCR_CFG3) != 310 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 311 sc->sc_rev = NCR_VARIANT_ESP100A; 312 } else { 313 /* NCRCFG2_FE enables > 64K transfers */ 314 sc->sc_cfg2 |= NCRCFG2_FE; 315 sc->sc_cfg3 = 0; 316 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 317 sc->sc_rev = NCR_VARIANT_ESP200; 318 } 319 } 320 321 /* 322 * XXX minsync and maxxfer _should_ be set up in MI code, 323 * XXX but it appears to have some dependency on what sort 324 * XXX of DMA we're hooked up to, etc. 325 */ 326 327 /* 328 * This is the value used to start sync negotiations 329 * Note that the NCR register "SYNCTP" is programmed 330 * in "clocks per byte", and has a minimum value of 4. 331 * The SCSI period used in negotiation is one-fourth 332 * of the time (in nanoseconds) needed to transfer one byte. 333 * Since the chip's clock is given in MHz, we have the following 334 * formula: 4 * period = (1000 / freq) * 4 335 */ 336 sc->sc_minsync = 1000 / sc->sc_freq; 337 338 /* 339 * Alas, we must now modify the value a bit, because it's 340 * only valid when can switch on FASTCLK and FASTSCSI bits 341 * in config register 3... 342 */ 343 switch (sc->sc_rev) { 344 case NCR_VARIANT_ESP100: 345 sc->sc_maxxfer = 64 * 1024; 346 sc->sc_minsync = 0; /* No synch on old chip? */ 347 break; 348 349 case NCR_VARIANT_ESP100A: 350 sc->sc_maxxfer = 64 * 1024; 351 /* Min clocks/byte is 5 */ 352 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 353 break; 354 355 case NCR_VARIANT_ESP200: 356 sc->sc_maxxfer = 16 * 1024 * 1024; 357 /* XXX - do actually set FAST* bits */ 358 break; 359 } 360 361 /* Establish interrupt channel */ 362 isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc, 363 NEXT_I_IPL(NEXT_I_SCSI), 0); 364 INTR_ENABLE(NEXT_I_SCSI); 365 366 /* register interrupt stats */ 367 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 368 369 /* Do the common parts of attachment. */ 370 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 371 372 #if 0 373 /* Turn on target selection using the `dma' method */ 374 ncr53c9x_dmaselect = 1; 375 376 bootpath_store(1, NULL); 377 #endif 378 379 } 380 381 /* 382 * Glue functions. 383 */ 384 385 u_char 386 esp_read_reg(sc, reg) 387 struct ncr53c9x_softc *sc; 388 int reg; 389 { 390 struct esp_softc *esc = (struct esp_softc *)sc; 391 392 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 393 } 394 395 void 396 esp_write_reg(sc, reg, val) 397 struct ncr53c9x_softc *sc; 398 int reg; 399 u_char val; 400 { 401 struct esp_softc *esc = (struct esp_softc *)sc; 402 403 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 404 } 405 406 int 407 esp_dma_isintr(sc) 408 struct ncr53c9x_softc *sc; 409 { 410 return (INTR_OCCURRED(NEXT_I_SCSI)); 411 } 412 413 void 414 esp_dma_reset(sc) 415 struct ncr53c9x_softc *sc; 416 { 417 struct esp_softc *esc = (struct esp_softc *)sc; 418 nextdma_reset(&esc->sc_scsi_dma); 419 } 420 421 int 422 esp_dma_intr(sc) 423 struct ncr53c9x_softc *sc; 424 { 425 /* Do nothing here, since the DMA has real interrupts 426 * of its own. 427 */ 428 return (0); 429 } 430 431 int 432 esp_dma_setup(sc, addr, len, datain, dmasize) 433 struct ncr53c9x_softc *sc; 434 caddr_t *addr; 435 size_t *len; 436 int datain; 437 size_t *dmasize; 438 { 439 struct esp_softc *esc = (struct esp_softc *)sc; 440 441 #ifdef DIAGNOSTIC 442 if (esc->sc_datain != -1) { 443 panic("%s: map already loaded in esp_dma_setup, datain = %d", 444 sc->sc_dev.dv_xname,esc->sc_datain); 445 } 446 #endif 447 448 { 449 int error; 450 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 451 esc->sc_dmamap, *addr, *dmasize, NULL, BUS_DMA_NOWAIT); 452 if (error) { 453 panic("%s: can't start DMA\n"); 454 } 455 } 456 457 esc->sc_datain = datain; 458 459 return (0); 460 } 461 462 void 463 esp_dma_go(sc) 464 struct ncr53c9x_softc *sc; 465 { 466 struct esp_softc *esc = (struct esp_softc *)sc; 467 nextdma_start(&esc->sc_scsi_dma, 468 (esc->sc_datain ? DMACSR_READ : DMACSR_WRITE)); 469 } 470 471 void 472 esp_dma_stop(sc) 473 struct ncr53c9x_softc *sc; 474 { 475 panic("Not yet implemented"); 476 } 477 478 int 479 esp_dma_isactive(sc) 480 struct ncr53c9x_softc *sc; 481 { 482 struct esp_softc *esc = (struct esp_softc *)sc; 483 return( !nextdma_finished(&esc->sc_scsi_dma)); 484 } 485 486 /****************************************************************/ 487 488 /* Internal dma callback routines */ 489 bus_dmamap_t 490 esp_dmacb_continue(arg) 491 void *arg; 492 { 493 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 494 struct esp_softc *esc = (struct esp_softc *)sc; 495 496 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap, 497 0, esc->sc_dmamap->dm_mapsize, 498 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 499 500 #ifdef DIAGNOSTIC 501 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 502 panic("%s: map not loaded in dma continue callback, datain = %d", 503 sc->sc_dev.dv_xname,esc->sc_datain); 504 } 505 #endif 506 507 return(esc->sc_dmamap); 508 } 509 510 void 511 esp_dmacb_completed(map, arg) 512 bus_dmamap_t map; 513 void *arg; 514 { 515 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 516 struct esp_softc *esc = (struct esp_softc *)sc; 517 518 #ifdef DIAGNOSTIC 519 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 520 panic("%s: map not loaded in dma completed callback, datain = %d", 521 sc->sc_dev.dv_xname,esc->sc_datain); 522 } 523 if (map != esc->sc_dmamap) { 524 panic("%s: unexpected tx completed map", sc->sc_dev.dv_xname); 525 } 526 #endif 527 528 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap, 529 0, esc->sc_dmamap->dm_mapsize, 530 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 531 } 532 533 void 534 esp_dmacb_shutdown(arg) 535 void *arg; 536 { 537 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 538 struct esp_softc *esc = (struct esp_softc *)sc; 539 540 #ifdef DIAGNOSTIC 541 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 542 panic("%s: map not loaded in dma shutdown callback, datain = %d", 543 sc->sc_dev.dv_xname,esc->sc_datain); 544 } 545 #endif 546 547 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap); 548 esc->sc_datain = -1; 549 } 550
Indexes created Thu Sep 25 16:09:42 GMT 2025