esp.c revision 1.21
1 /* $NetBSD: esp.c,v 1.21 1999/03/02 12:11:24 dbj Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Grabbed from the sparc port at revision 1.73 for the NeXT. 81 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 82 */ 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/device.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 #include <sys/user.h> 94 #include <sys/queue.h> 95 96 #include <dev/scsipi/scsi_all.h> 97 #include <dev/scsipi/scsipi_all.h> 98 #include <dev/scsipi/scsiconf.h> 99 #include <dev/scsipi/scsi_message.h> 100 101 #include <machine/bus.h> 102 #include <machine/autoconf.h> 103 #include <machine/cpu.h> 104 105 #include <dev/ic/ncr53c9xreg.h> 106 #include <dev/ic/ncr53c9xvar.h> 107 108 #include <next68k/next68k/isr.h> 109 110 #include <next68k/dev/nextdmareg.h> 111 #include <next68k/dev/nextdmavar.h> 112 113 #include "espreg.h" 114 #include "espvar.h" 115 116 #ifdef DEBUG 117 #define ESP_DEBUG 118 #endif 119 120 #ifdef ESP_DEBUG 121 int esp_debug = 0; 122 #define DPRINTF(x) if (esp_debug) printf x; 123 #else 124 #define DPRINTF(x) 125 #endif 126 127 128 void espattach_intio __P((struct device *, struct device *, void *)); 129 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 130 131 /* DMA callbacks */ 132 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 133 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 134 void esp_dmacb_shutdown __P((void *arg)); 135 136 #ifdef ESP_DEBUG 137 char esp_dma_dump[5*1024] = ""; 138 struct ncr53c9x_softc *esp_debug_sc = 0; 139 void esp_dma_store __P((struct ncr53c9x_softc *sc)); 140 void esp_dma_print __P((struct ncr53c9x_softc *sc)); 141 #endif 142 143 144 /* Linkup to the rest of the kernel */ 145 struct cfattach esp_ca = { 146 sizeof(struct esp_softc), espmatch_intio, espattach_intio 147 }; 148 149 struct scsipi_device esp_dev = { 150 NULL, /* Use default error handler */ 151 NULL, /* have a queue, served by this */ 152 NULL, /* have no async handler */ 153 NULL, /* Use default 'done' routine */ 154 }; 155 156 /* 157 * Functions and the switch for the MI code. 158 */ 159 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 160 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 161 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 162 void esp_dma_reset __P((struct ncr53c9x_softc *)); 163 int esp_dma_intr __P((struct ncr53c9x_softc *)); 164 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 165 size_t *, int, size_t *)); 166 void esp_dma_go __P((struct ncr53c9x_softc *)); 167 void esp_dma_stop __P((struct ncr53c9x_softc *)); 168 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 169 170 struct ncr53c9x_glue esp_glue = { 171 esp_read_reg, 172 esp_write_reg, 173 esp_dma_isintr, 174 esp_dma_reset, 175 esp_dma_intr, 176 esp_dma_setup, 177 esp_dma_go, 178 esp_dma_stop, 179 esp_dma_isactive, 180 NULL, /* gl_clear_latched_intr */ 181 }; 182 183 #ifdef ESP_DEBUG 184 #define XCHR(x) "0123456789abcdef"[(x) & 0xf] 185 static void 186 esp_hex_dump(unsigned char *pkt, size_t len) 187 { 188 size_t i, j; 189 190 printf("0000: "); 191 for(i=0; i<len; i++) { 192 printf("%c%c ", XCHR(pkt[i]>>4), XCHR(pkt[i])); 193 if ((i+1) % 16 == 0) { 194 printf(" %c", '"'); 195 for(j=0; j<16; j++) 196 printf("%c", pkt[i-15+j]>=32 && pkt[i-15+j]<127?pkt[i-15+j]:'.'); 197 printf("%c\n%c%c%c%c: ", '"', XCHR((i+1)>>12), 198 XCHR((i+1)>>8), XCHR((i+1)>>4), XCHR(i+1)); 199 } 200 } 201 printf("\n"); 202 } 203 #endif 204 205 int 206 espmatch_intio(parent, cf, aux) 207 struct device *parent; 208 struct cfdata *cf; 209 void *aux; 210 { 211 /* should probably probe here */ 212 /* Should also probably set up data from config */ 213 214 return(1); 215 } 216 217 void 218 espattach_intio(parent, self, aux) 219 struct device *parent, *self; 220 void *aux; 221 { 222 struct esp_softc *esc = (void *)self; 223 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 224 225 #ifdef ESP_DEBUG 226 esp_debug_sc = sc; 227 #endif 228 229 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 230 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 231 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 232 panic("\n%s: can't map ncr53c90 registers", 233 sc->sc_dev.dv_xname); 234 } 235 236 sc->sc_id = 7; 237 sc->sc_freq = 20; /* Mhz */ 238 239 /* 240 * Set up glue for MI code early; we use some of it here. 241 */ 242 sc->sc_glue = &esp_glue; 243 244 /* 245 * XXX More of this should be in ncr53c9x_attach(), but 246 * XXX should we really poke around the chip that much in 247 * XXX the MI code? Think about this more... 248 */ 249 250 /* 251 * It is necessary to try to load the 2nd config register here, 252 * to find out what rev the esp chip is, else the ncr53c9x_reset 253 * will not set up the defaults correctly. 254 */ 255 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 256 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 257 sc->sc_cfg3 = NCRCFG3_CDB; 258 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 259 260 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 261 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 262 sc->sc_rev = NCR_VARIANT_ESP100; 263 } else { 264 sc->sc_cfg2 = NCRCFG2_SCSI2; 265 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 266 sc->sc_cfg3 = 0; 267 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 268 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 269 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 270 if (NCR_READ_REG(sc, NCR_CFG3) != 271 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 272 sc->sc_rev = NCR_VARIANT_ESP100A; 273 } else { 274 /* NCRCFG2_FE enables > 64K transfers */ 275 sc->sc_cfg2 |= NCRCFG2_FE; 276 sc->sc_cfg3 = 0; 277 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 278 sc->sc_rev = NCR_VARIANT_ESP200; 279 } 280 } 281 282 /* 283 * XXX minsync and maxxfer _should_ be set up in MI code, 284 * XXX but it appears to have some dependency on what sort 285 * XXX of DMA we're hooked up to, etc. 286 */ 287 288 /* 289 * This is the value used to start sync negotiations 290 * Note that the NCR register "SYNCTP" is programmed 291 * in "clocks per byte", and has a minimum value of 4. 292 * The SCSI period used in negotiation is one-fourth 293 * of the time (in nanoseconds) needed to transfer one byte. 294 * Since the chip's clock is given in MHz, we have the following 295 * formula: 4 * period = (1000 / freq) * 4 296 */ 297 sc->sc_minsync = 1000 / sc->sc_freq; 298 299 /* 300 * Alas, we must now modify the value a bit, because it's 301 * only valid when can switch on FASTCLK and FASTSCSI bits 302 * in config register 3... 303 */ 304 switch (sc->sc_rev) { 305 case NCR_VARIANT_ESP100: 306 sc->sc_maxxfer = 64 * 1024; 307 sc->sc_minsync = 0; /* No synch on old chip? */ 308 break; 309 310 case NCR_VARIANT_ESP100A: 311 sc->sc_maxxfer = 64 * 1024; 312 /* Min clocks/byte is 5 */ 313 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 314 break; 315 316 case NCR_VARIANT_ESP200: 317 sc->sc_maxxfer = 16 * 1024 * 1024; 318 /* XXX - do actually set FAST* bits */ 319 break; 320 } 321 322 /* @@@ Some ESP_DCTL bits probably need setting */ 323 NCR_WRITE_REG(sc, ESP_DCTL, 324 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 325 DELAY(10); 326 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 327 DELAY(10); 328 329 /* Set up SCSI DMA */ 330 { 331 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 332 333 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 334 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 335 panic("\n%s: can't map scsi DMA registers", 336 sc->sc_dev.dv_xname); 337 } 338 339 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 340 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 341 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 342 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 343 esc->sc_scsi_dma.nd_cb_arg = sc; 344 nextdma_config(&esc->sc_scsi_dma); 345 nextdma_init(&esc->sc_scsi_dma); 346 347 #if 0 348 /* Turn on target selection using the `dma' method */ 349 ncr53c9x_dmaselect = 1; 350 #else 351 ncr53c9x_dmaselect = 0; 352 #endif 353 354 esc->sc_datain = -1; 355 esc->sc_dmaaddr = 0; 356 esc->sc_dmalen = 0; 357 esc->sc_dmasize = 0; 358 359 esc->sc_loaded = 0; 360 361 esc->sc_begin = 0; 362 esc->sc_begin_size = 0; 363 364 { 365 int error; 366 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 367 sc->sc_maxxfer, sc->sc_maxxfer/NBPG, sc->sc_maxxfer, 368 0, BUS_DMA_ALLOCNOW, &esc->sc_main_dmamap)) != 0) { 369 panic("%s: can't create main i/o DMA map, error = %d", 370 sc->sc_dev.dv_xname,error); 371 } 372 } 373 esc->sc_main = 0; 374 esc->sc_main_size = 0; 375 376 { 377 int error; 378 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 379 ESP_DMA_TAILBUFSIZE, 380 1, ESP_DMA_TAILBUFSIZE, 381 0, BUS_DMA_ALLOCNOW, &esc->sc_tail_dmamap)) != 0) { 382 panic("%s: can't create tail i/o DMA map, error = %d", 383 sc->sc_dev.dv_xname,error); 384 } 385 } 386 esc->sc_tail = 0; 387 esc->sc_tail_size = 0; 388 389 } 390 391 /* Establish interrupt channel */ 392 isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc, 393 NEXT_I_IPL(NEXT_I_SCSI), 0); 394 INTR_ENABLE(NEXT_I_SCSI); 395 396 /* register interrupt stats */ 397 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 398 399 /* Do the common parts of attachment. */ 400 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 401 sc->sc_adapter.scsipi_minphys = minphys; 402 ncr53c9x_attach(sc, &esp_dev); 403 } 404 405 /* 406 * Glue functions. 407 */ 408 409 u_char 410 esp_read_reg(sc, reg) 411 struct ncr53c9x_softc *sc; 412 int reg; 413 { 414 struct esp_softc *esc = (struct esp_softc *)sc; 415 416 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 417 } 418 419 void 420 esp_write_reg(sc, reg, val) 421 struct ncr53c9x_softc *sc; 422 int reg; 423 u_char val; 424 { 425 struct esp_softc *esc = (struct esp_softc *)sc; 426 427 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 428 } 429 430 int 431 esp_dma_isintr(sc) 432 struct ncr53c9x_softc *sc; 433 { 434 struct esp_softc *esc = (struct esp_softc *)sc; 435 436 int r = (INTR_OCCURRED(NEXT_I_SCSI)); 437 438 if (r) { 439 440 { 441 int s; 442 s = spldma(); 443 444 DPRINTF(("esp_dma_isintr = 0x%b\n", 445 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS)); 446 447 while (esp_dma_isactive(sc)) { 448 449 #ifdef DIAGNOSTIC 450 r = (INTR_OCCURRED(NEXT_I_SCSI)); 451 if (!r) panic("esp intr enabled but dma failed to flush"); 452 #endif 453 454 if (esc->sc_datain) { 455 NCR_WRITE_REG(sc, ESP_DCTL, 456 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD | ESPDCTL_FLUSH); 457 NCR_WRITE_REG(sc, ESP_DCTL, 458 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 459 } else { 460 NCR_WRITE_REG(sc, ESP_DCTL, 461 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_FLUSH); 462 NCR_WRITE_REG(sc, ESP_DCTL, 463 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 464 } 465 466 /* Really this code should only be used in polled mode */ 467 { 468 int nr; 469 nr = nextdma_intr(&esc->sc_scsi_dma); 470 if (nr) { 471 DPRINTF(("nextma_intr = %d\n",nr)); 472 } 473 } 474 } 475 476 splx(s); 477 } 478 479 #ifdef DIAGNOSTIC 480 r = (INTR_OCCURRED(NEXT_I_SCSI)); 481 if (!r) panic("esp intr not enabled after dma flush"); 482 #endif 483 484 /* Clear the DMAMOD bit in the DCTL register, since if this 485 * routine returns true, then the ncr53c9x_intr handler will 486 * be called and needs access to the scsi registers. 487 */ 488 if (esc->sc_datain) { 489 NCR_WRITE_REG(sc, ESP_DCTL, 490 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 491 } else { 492 NCR_WRITE_REG(sc, ESP_DCTL, 493 ESPDCTL_20MHZ | ESPDCTL_INTENB); 494 } 495 496 } 497 498 return (r); 499 } 500 501 void 502 esp_dma_reset(sc) 503 struct ncr53c9x_softc *sc; 504 { 505 struct esp_softc *esc = (struct esp_softc *)sc; 506 507 DPRINTF(("esp dma reset\n")); 508 509 #ifdef ESP_DEBUG 510 if (esp_debug) { 511 printf(" *intrstat = 0x%b\n", 512 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS); 513 printf(" *intrmask = 0x%b\n", 514 (*(volatile u_long *)IIOV(NEXT_P_INTRMASK)),NEXT_INTR_BITS); 515 } 516 #endif 517 518 /* Clear the DMAMOD bit in the DCTL register: */ 519 NCR_WRITE_REG(sc, ESP_DCTL, 520 ESPDCTL_20MHZ | ESPDCTL_INTENB); 521 522 nextdma_reset(&esc->sc_scsi_dma); 523 524 esc->sc_datain = -1; 525 esc->sc_dmaaddr = 0; 526 esc->sc_dmalen = 0; 527 esc->sc_dmasize = 0; 528 529 esc->sc_loaded = 0; 530 531 esc->sc_begin = 0; 532 esc->sc_begin_size = 0; 533 534 if (esc->sc_main_dmamap->dm_mapsize) { 535 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 536 } 537 esc->sc_main = 0; 538 esc->sc_main_size = 0; 539 540 if (esc->sc_tail_dmamap->dm_mapsize) { 541 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 542 } 543 esc->sc_tail = 0; 544 esc->sc_tail_size = 0; 545 } 546 547 int 548 esp_dma_intr(sc) 549 struct ncr53c9x_softc *sc; 550 { 551 #ifdef DIAGNOSTIC 552 panic("%s: esp_dma_intr shouldn't be invoked.\n", sc->sc_dev.dv_xname); 553 #endif 554 555 return -1; 556 } 557 558 /* it appears that: 559 * addr and len arguments to this need to be kept up to date 560 * with the status of the transfter. 561 * the dmasize of this is the actual length of the transfer 562 * request, which is guaranteed to be less than maxxfer. 563 * (len may be > maxxfer) 564 */ 565 566 int 567 esp_dma_setup(sc, addr, len, datain, dmasize) 568 struct ncr53c9x_softc *sc; 569 caddr_t *addr; 570 size_t *len; 571 int datain; 572 size_t *dmasize; 573 { 574 struct esp_softc *esc = (struct esp_softc *)sc; 575 576 #ifdef DIAGNOSTIC 577 #ifdef ESP_DEBUG 578 /* if this is a read DMA, pre-fill the buffer with 0xdeadbeef 579 * to identify bogus reads 580 */ 581 if (datain) { 582 int *v = (int *)(*addr); 583 int i; 584 for(i=0;i<((*len)/4);i++) v[i] = 0xdeadbeef; 585 v = (int *)(&(esc->sc_tailbuf[0])); 586 for(i=0;i<((sizeof(esc->sc_tailbuf)/4));i++) v[i] = 0xdeaffeed; 587 } 588 #endif 589 #endif 590 591 DPRINTF(("esp_dma_setup(0x%08lx,0x%08lx,0x%08lx)\n",*addr,*len,*dmasize)); 592 593 #ifdef DIAGNOSTIC /* @@@ this is ok sometimes. verify that we handle it ok 594 * and then remove this check 595 */ 596 if (*len != *dmasize) { 597 panic("esp dmalen != size"); 598 } 599 #endif 600 601 #ifdef DIAGNOSTIC 602 if ((esc->sc_datain != -1) || 603 (esc->sc_main_dmamap->dm_mapsize != 0) || 604 (esc->sc_tail_dmamap->dm_mapsize != 0) || 605 (esc->sc_dmasize != 0)) { 606 panic("%s: map already loaded in esp_dma_setup\n" 607 "\tdatain = %d\n\tmain_mapsize=%d\n\tail_mapsize=%d\n\tdmasize = %d", 608 sc->sc_dev.dv_xname, esc->sc_datain, 609 esc->sc_main_dmamap->dm_mapsize, 610 esc->sc_tail_dmamap->dm_mapsize, 611 esc->sc_dmasize); 612 } 613 #endif 614 615 /* we are sometimes asked to dma zero bytes, that's easy */ 616 if (*len <= 0) { 617 return(0); 618 } 619 620 /* Save these in case we have to abort DMA */ 621 esc->sc_datain = datain; 622 esc->sc_dmaaddr = addr; 623 esc->sc_dmalen = len; 624 esc->sc_dmasize = *dmasize; 625 626 esc->sc_loaded = 0; 627 628 { 629 size_t slop_bgn_size; /* # bytes to be fifo'd at beginning */ 630 size_t slop_end_size; /* # bytes to be transferred in tail buffer */ 631 632 { 633 u_long bgn = (u_long)(*esc->sc_dmaaddr); 634 u_long end = (u_long)(*esc->sc_dmaaddr+esc->sc_dmasize); 635 636 slop_bgn_size = DMA_BEGINALIGNMENT-(bgn % DMA_BEGINALIGNMENT); 637 if (slop_bgn_size == DMA_BEGINALIGNMENT) slop_bgn_size = 0; 638 slop_end_size = (end % DMA_ENDALIGNMENT); 639 } 640 641 /* Check to make sure we haven't counted extra slop 642 * as would happen for a very short dma buffer, also 643 * for short buffers, just stuff the entire thing in the tail 644 */ 645 if ((slop_bgn_size+slop_end_size >= esc->sc_dmasize) 646 #if 0 647 || (esc->sc_dmasize <= ESP_DMA_MAXTAIL) 648 #endif 649 ) 650 { 651 slop_bgn_size = 0; 652 slop_end_size = esc->sc_dmasize; 653 } 654 655 /* initialize the fifo buffer */ 656 if (slop_bgn_size) { 657 esc->sc_begin = *esc->sc_dmaaddr; 658 esc->sc_begin_size = slop_bgn_size; 659 } else { 660 esc->sc_begin = 0; 661 esc->sc_begin_size = 0; 662 } 663 664 /* Load the normal DMA map */ 665 { 666 esc->sc_main = *esc->sc_dmaaddr+slop_bgn_size; 667 esc->sc_main_size = (esc->sc_dmasize)-(slop_end_size+slop_bgn_size); 668 669 if (esc->sc_main_size) { 670 int error; 671 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 672 esc->sc_main_dmamap, 673 esc->sc_main, esc->sc_main_size, 674 NULL, BUS_DMA_NOWAIT); 675 if (error) { 676 panic("%s: can't load main dma map. error = %d, addr=0x%08x, size=0x%08x", 677 sc->sc_dev.dv_xname, error,esc->sc_main,esc->sc_main_size); 678 } 679 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 680 0, esc->sc_main_dmamap->dm_mapsize, 681 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 682 } else { 683 esc->sc_main = 0; 684 } 685 } 686 687 /* Load the tail DMA map */ 688 if (slop_end_size) { 689 esc->sc_tail = DMA_ENDALIGN(caddr_t,esc->sc_tailbuf+slop_end_size)-slop_end_size; 690 /* If the beginning of the tail is not correctly aligned, 691 * we have no choice but to align the start, which might then unalign the end. 692 */ 693 esc->sc_tail = DMA_ALIGN(caddr_t,esc->sc_tail); 694 /* So therefore, we change the tail size to be end aligned again. */ 695 esc->sc_tail_size = DMA_ENDALIGN(caddr_t,esc->sc_tail+slop_end_size)-esc->sc_tail; 696 697 /* @@@ next dma overrun lossage */ 698 if (!esc->sc_datain) { 699 esc->sc_tail_size += ESP_DMA_OVERRUN; 700 } 701 702 { 703 int error; 704 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 705 esc->sc_tail_dmamap, 706 esc->sc_tail, esc->sc_tail_size, 707 NULL, BUS_DMA_NOWAIT); 708 if (error) { 709 panic("%s: can't load tail dma map. error = %d, addr=0x%08x, size=0x%08x", 710 sc->sc_dev.dv_xname, error,esc->sc_tail,esc->sc_tail_size); 711 } 712 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 713 0, esc->sc_tail_dmamap->dm_mapsize, 714 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 715 } 716 } 717 } 718 719 return (0); 720 } 721 722 #ifdef ESP_DEBUG 723 /* For debugging */ 724 void 725 esp_dma_store(sc) 726 struct ncr53c9x_softc *sc; 727 { 728 struct esp_softc *esc = (struct esp_softc *)sc; 729 char *p = &esp_dma_dump[0]; 730 731 p += sprintf(p,"%s: sc_datain=%d\n",sc->sc_dev.dv_xname,esc->sc_datain); 732 p += sprintf(p,"%s: sc_loaded=0x%08x\n",sc->sc_dev.dv_xname,esc->sc_loaded); 733 734 if (esc->sc_dmaaddr) { 735 p += sprintf(p,"%s: sc_dmaaddr=0x%08lx\n",sc->sc_dev.dv_xname,*esc->sc_dmaaddr); 736 } else { 737 p += sprintf(p,"%s: sc_dmaaddr=NULL\n",sc->sc_dev.dv_xname); 738 } 739 if (esc->sc_dmalen) { 740 p += sprintf(p,"%s: sc_dmalen=0x%08lx\n",sc->sc_dev.dv_xname,*esc->sc_dmalen); 741 } else { 742 p += sprintf(p,"%s: sc_dmalen=NULL\n",sc->sc_dev.dv_xname); 743 } 744 p += sprintf(p,"%s: sc_dmasize=0x%08x\n",sc->sc_dev.dv_xname,esc->sc_dmasize); 745 746 p += sprintf(p,"%s: sc_begin = 0x%08x, sc_begin_size = 0x%08x\n", 747 sc->sc_dev.dv_xname, esc->sc_begin, esc->sc_begin_size); 748 p += sprintf(p,"%s: sc_main = 0x%08x, sc_main_size = 0x%08x\n", 749 sc->sc_dev.dv_xname, esc->sc_main, esc->sc_main_size); 750 { 751 int i; 752 bus_dmamap_t map = esc->sc_main_dmamap; 753 p += sprintf(p,"%s: sc_main_dmamap. mapsize = 0x%08x, nsegs = %d\n", 754 sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs); 755 for(i=0;i<map->dm_nsegs;i++) { 756 p += sprintf(p,"%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n", 757 sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len); 758 } 759 } 760 p += sprintf(p,"%s: sc_tail = 0x%08x, sc_tail_size = 0x%08x\n", 761 sc->sc_dev.dv_xname, esc->sc_tail, esc->sc_tail_size); 762 { 763 int i; 764 bus_dmamap_t map = esc->sc_tail_dmamap; 765 p += sprintf(p,"%s: sc_tail_dmamap. mapsize = 0x%08x, nsegs = %d\n", 766 sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs); 767 for(i=0;i<map->dm_nsegs;i++) { 768 p += sprintf(p,"%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n", 769 sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len); 770 } 771 } 772 } 773 774 void 775 esp_dma_print(sc) 776 struct ncr53c9x_softc *sc; 777 { 778 esp_dma_store(sc); 779 printf("%s",esp_dma_dump); 780 } 781 #endif 782 783 void 784 esp_dma_go(sc) 785 struct ncr53c9x_softc *sc; 786 { 787 struct esp_softc *esc = (struct esp_softc *)sc; 788 789 DPRINTF(("%s: esp_dma_go(datain = %d)\n", 790 sc->sc_dev.dv_xname, esc->sc_datain)); 791 792 #ifdef ESP_DEBUG 793 if (esp_debug) esp_dma_print(sc); 794 else esp_dma_store(sc); 795 #endif 796 797 #ifdef ESP_DEBUG 798 { 799 int n = NCR_READ_REG(sc, NCR_FFLAG); 800 DPRINTF(("%s: fifo size = %d, seq = 0x%x\n", 801 sc->sc_dev.dv_xname, 802 n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 803 } 804 #endif 805 806 /* zero length dma transfers are boring, dmasize is probably -1 in those cases 807 * because it was never set up by esp_dma_setup 808 */ 809 if (esc->sc_dmasize == 0) { 810 return; 811 } 812 813 #if defined(DIAGNOSTIC) 814 if ((esc->sc_begin_size == 0) && 815 (esc->sc_main_dmamap->dm_mapsize == 0) && 816 (esc->sc_tail_dmamap->dm_mapsize == 0)) { 817 esp_dma_print(sc); 818 panic("%s: No DMA requested!",sc->sc_dev.dv_xname); 819 } 820 #endif 821 822 /* Stuff the fifo with the begin buffer */ 823 if (esc->sc_datain) { 824 int i; 825 for(i=0;i<esc->sc_begin_size;i++) { 826 esc->sc_begin[i]=NCR_READ_REG(sc, NCR_FIFO); 827 } 828 } else { 829 int i; 830 for(i=0;i<esc->sc_begin_size;i++) { 831 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_begin[i]); 832 } 833 } 834 835 /* if we are a dma write cycle, copy the end slop */ 836 if (esc->sc_datain == 0) { 837 memcpy(esc->sc_tail, 838 (*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size), 839 (esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size))); 840 } 841 842 nextdma_start(&esc->sc_scsi_dma, 843 (esc->sc_datain ? DMACSR_READ : DMACSR_WRITE)); 844 845 if (esc->sc_datain) { 846 NCR_WRITE_REG(sc, ESP_DCTL, 847 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 848 } else { 849 NCR_WRITE_REG(sc, ESP_DCTL, 850 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 851 } 852 853 } 854 855 void 856 esp_dma_stop(sc) 857 struct ncr53c9x_softc *sc; 858 { 859 panic("Not yet implemented"); 860 } 861 862 int 863 esp_dma_isactive(sc) 864 struct ncr53c9x_softc *sc; 865 { 866 struct esp_softc *esc = (struct esp_softc *)sc; 867 int r = !nextdma_finished(&esc->sc_scsi_dma); 868 DPRINTF(("esp_dma_isactive = %d\n",r)); 869 return(r); 870 } 871 872 /****************************************************************/ 873 874 /* Internal dma callback routines */ 875 bus_dmamap_t 876 esp_dmacb_continue(arg) 877 void *arg; 878 { 879 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 880 struct esp_softc *esc = (struct esp_softc *)sc; 881 882 DPRINTF(("%s: dma continue\n",sc->sc_dev.dv_xname)); 883 884 #ifdef DIAGNOSTIC 885 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 886 panic("%s: map not loaded in dma continue callback, datain = %d", 887 sc->sc_dev.dv_xname,esc->sc_datain); 888 } 889 #endif 890 891 if ((!(esc->sc_loaded & ESP_LOADED_MAIN)) && 892 (esc->sc_main_dmamap->dm_mapsize)) { 893 DPRINTF(("%s: Loading main map\n",sc->sc_dev.dv_xname)); 894 #if 0 895 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 896 0, esc->sc_main_dmamap->dm_mapsize, 897 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 898 #endif 899 esc->sc_loaded |= ESP_LOADED_MAIN; 900 return(esc->sc_main_dmamap); 901 } 902 903 if ((!(esc->sc_loaded & ESP_LOADED_TAIL)) && 904 (esc->sc_tail_dmamap->dm_mapsize)) { 905 DPRINTF(("%s: Loading tail map\n",sc->sc_dev.dv_xname)); 906 #if 0 907 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 908 0, esc->sc_tail_dmamap->dm_mapsize, 909 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 910 #endif 911 esc->sc_loaded |= ESP_LOADED_TAIL; 912 return(esc->sc_tail_dmamap); 913 } 914 915 DPRINTF(("%s: not loading map\n",sc->sc_dev.dv_xname)); 916 return(0); 917 } 918 919 920 void 921 esp_dmacb_completed(map, arg) 922 bus_dmamap_t map; 923 void *arg; 924 { 925 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 926 struct esp_softc *esc = (struct esp_softc *)sc; 927 928 DPRINTF(("%s: dma completed\n",sc->sc_dev.dv_xname)); 929 930 #ifdef DIAGNOSTIC 931 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 932 panic("%s: invalid dma direction in completed callback, datain = %d", 933 sc->sc_dev.dv_xname,esc->sc_datain); 934 } 935 if ((map != esc->sc_main_dmamap) && (map != esc->sc_tail_dmamap)) { 936 panic("%s: unexpected completed map", sc->sc_dev.dv_xname); 937 } 938 #endif 939 940 #if 0 941 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, map, 942 0, map->dm_mapsize, 943 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 944 #endif 945 946 } 947 948 void 949 esp_dmacb_shutdown(arg) 950 void *arg; 951 { 952 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 953 struct esp_softc *esc = (struct esp_softc *)sc; 954 955 DPRINTF(("%s: dma shutdown\n",sc->sc_dev.dv_xname)); 956 957 /* Stuff the end slop into fifo */ 958 959 #ifdef ESP_DEBUG 960 if (esp_debug) { 961 962 int n = NCR_READ_REG(sc, NCR_FFLAG); 963 DPRINTF(("%s: fifo size = %d, seq = 0x%x\n", 964 sc->sc_dev.dv_xname,n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 965 966 NCR_DMA(("%s:dmaintr: tcl=%d, tcm=%d, tch=%d\n", 967 sc->sc_dev.dv_xname, 968 NCR_READ_REG(sc, NCR_TCL), 969 NCR_READ_REG(sc, NCR_TCM), 970 (sc->sc_cfg2 & NCRCFG2_FE) 971 ? NCR_READ_REG(sc, NCR_TCH) : 0)); 972 } 973 #endif 974 975 /* First copy the tail dma buffer data for read transfers */ 976 if (esc->sc_datain == 1) { 977 memcpy((*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size), 978 esc->sc_tail, 979 (esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size))); 980 } 981 982 *(esc->sc_dmaaddr) += esc->sc_dmasize; 983 *(esc->sc_dmalen) -= esc->sc_dmasize; 984 985 #ifdef ESP_DEBUG 986 if (esp_debug) { 987 printf("%s: dma_shutdown: addr=0x%08lx,len=0x%08lx,size=0x%08lx\n", 988 sc->sc_dev.dv_xname, 989 *esc->sc_dmaaddr, *esc->sc_dmalen, esc->sc_dmasize); 990 esp_hex_dump(*(esc->sc_dmaaddr),esc->sc_dmasize); 991 printf("%s: tail=0x%08lx,tailbuf=0x%08lx,tail_size=0x%08lx\n", 992 sc->sc_dev.dv_xname, 993 esc->sc_tail, &(esc->sc_tailbuf[0]), esc->sc_tail_size); 994 esp_hex_dump(&(esc->sc_tailbuf[0]),sizeof(esc->sc_tailbuf)); 995 } 996 #endif 997 998 if (esc->sc_main_dmamap->dm_mapsize) { 999 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 1000 0, esc->sc_main_dmamap->dm_mapsize, 1001 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1002 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 1003 } 1004 esc->sc_main = 0; 1005 esc->sc_main_size = 0; 1006 1007 if (esc->sc_tail_dmamap->dm_mapsize) { 1008 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 1009 0, esc->sc_tail_dmamap->dm_mapsize, 1010 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1011 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 1012 } 1013 esc->sc_tail = 0; 1014 esc->sc_tail_size = 0; 1015 1016 esc->sc_datain = -1; 1017 esc->sc_dmaaddr = 0; 1018 esc->sc_dmalen = 0; 1019 esc->sc_dmasize = 0; 1020 1021 esc->sc_loaded = 0; 1022 1023 esc->sc_begin = 0; 1024 esc->sc_begin_size = 0; 1025 1026 #ifdef ESP_DEBUG 1027 if (esp_debug) { 1028 printf(" *intrstat = 0x%b\n", 1029 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS); 1030 printf(" *intrmask = 0x%b\n", 1031 (*(volatile u_long *)IIOV(NEXT_P_INTRMASK)),NEXT_INTR_BITS); 1032 } 1033 #endif 1034 1035 } 1036
Indexes created Wed Sep 24 05:09:52 GMT 2025