esp.c revision 1.22
1 /* $NetBSD: esp.c,v 1.22 1999/03/03 16:02:23 dbj Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Grabbed from the sparc port at revision 1.73 for the NeXT. 81 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 82 */ 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/device.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 #include <sys/user.h> 94 #include <sys/queue.h> 95 96 #include <dev/scsipi/scsi_all.h> 97 #include <dev/scsipi/scsipi_all.h> 98 #include <dev/scsipi/scsiconf.h> 99 #include <dev/scsipi/scsi_message.h> 100 101 #include <machine/bus.h> 102 #include <machine/autoconf.h> 103 #include <machine/cpu.h> 104 105 #include <dev/ic/ncr53c9xreg.h> 106 #include <dev/ic/ncr53c9xvar.h> 107 108 #include <next68k/next68k/isr.h> 109 110 #include <next68k/dev/nextdmareg.h> 111 #include <next68k/dev/nextdmavar.h> 112 113 #include "espreg.h" 114 #include "espvar.h" 115 116 #ifdef DEBUG 117 #define ESP_DEBUG 118 #endif 119 120 #ifdef ESP_DEBUG 121 int esp_debug = 0; 122 #define DPRINTF(x) if (esp_debug) printf x; 123 #else 124 #define DPRINTF(x) 125 #endif 126 127 128 void espattach_intio __P((struct device *, struct device *, void *)); 129 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 130 131 /* DMA callbacks */ 132 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 133 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 134 void esp_dmacb_shutdown __P((void *arg)); 135 136 #ifdef ESP_DEBUG 137 char esp_dma_dump[5*1024] = ""; 138 struct ncr53c9x_softc *esp_debug_sc = 0; 139 void esp_dma_store __P((struct ncr53c9x_softc *sc)); 140 void esp_dma_print __P((struct ncr53c9x_softc *sc)); 141 int esp_dma_nest = 0; 142 #endif 143 144 145 /* Linkup to the rest of the kernel */ 146 struct cfattach esp_ca = { 147 sizeof(struct esp_softc), espmatch_intio, espattach_intio 148 }; 149 150 struct scsipi_device esp_dev = { 151 NULL, /* Use default error handler */ 152 NULL, /* have a queue, served by this */ 153 NULL, /* have no async handler */ 154 NULL, /* Use default 'done' routine */ 155 }; 156 157 /* 158 * Functions and the switch for the MI code. 159 */ 160 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 161 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 162 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 163 void esp_dma_reset __P((struct ncr53c9x_softc *)); 164 int esp_dma_intr __P((struct ncr53c9x_softc *)); 165 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 166 size_t *, int, size_t *)); 167 void esp_dma_go __P((struct ncr53c9x_softc *)); 168 void esp_dma_stop __P((struct ncr53c9x_softc *)); 169 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 170 171 struct ncr53c9x_glue esp_glue = { 172 esp_read_reg, 173 esp_write_reg, 174 esp_dma_isintr, 175 esp_dma_reset, 176 esp_dma_intr, 177 esp_dma_setup, 178 esp_dma_go, 179 esp_dma_stop, 180 esp_dma_isactive, 181 NULL, /* gl_clear_latched_intr */ 182 }; 183 184 #ifdef ESP_DEBUG 185 #define XCHR(x) "0123456789abcdef"[(x) & 0xf] 186 static void 187 esp_hex_dump(unsigned char *pkt, size_t len) 188 { 189 size_t i, j; 190 191 printf("0000: "); 192 for(i=0; i<len; i++) { 193 printf("%c%c ", XCHR(pkt[i]>>4), XCHR(pkt[i])); 194 if ((i+1) % 16 == 0) { 195 printf(" %c", '"'); 196 for(j=0; j<16; j++) 197 printf("%c", pkt[i-15+j]>=32 && pkt[i-15+j]<127?pkt[i-15+j]:'.'); 198 printf("%c\n%c%c%c%c: ", '"', XCHR((i+1)>>12), 199 XCHR((i+1)>>8), XCHR((i+1)>>4), XCHR(i+1)); 200 } 201 } 202 printf("\n"); 203 } 204 #endif 205 206 int 207 espmatch_intio(parent, cf, aux) 208 struct device *parent; 209 struct cfdata *cf; 210 void *aux; 211 { 212 /* should probably probe here */ 213 /* Should also probably set up data from config */ 214 215 return(1); 216 } 217 218 void 219 espattach_intio(parent, self, aux) 220 struct device *parent, *self; 221 void *aux; 222 { 223 struct esp_softc *esc = (void *)self; 224 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 225 226 #ifdef ESP_DEBUG 227 esp_debug_sc = sc; 228 #endif 229 230 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 231 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 232 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 233 panic("\n%s: can't map ncr53c90 registers", 234 sc->sc_dev.dv_xname); 235 } 236 237 sc->sc_id = 7; 238 sc->sc_freq = 20; /* Mhz */ 239 240 /* 241 * Set up glue for MI code early; we use some of it here. 242 */ 243 sc->sc_glue = &esp_glue; 244 245 /* 246 * XXX More of this should be in ncr53c9x_attach(), but 247 * XXX should we really poke around the chip that much in 248 * XXX the MI code? Think about this more... 249 */ 250 251 /* 252 * It is necessary to try to load the 2nd config register here, 253 * to find out what rev the esp chip is, else the ncr53c9x_reset 254 * will not set up the defaults correctly. 255 */ 256 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 257 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 258 sc->sc_cfg3 = NCRCFG3_CDB; 259 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 260 261 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 262 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 263 sc->sc_rev = NCR_VARIANT_ESP100; 264 } else { 265 sc->sc_cfg2 = NCRCFG2_SCSI2; 266 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 267 sc->sc_cfg3 = 0; 268 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 269 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 270 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 271 if (NCR_READ_REG(sc, NCR_CFG3) != 272 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 273 sc->sc_rev = NCR_VARIANT_ESP100A; 274 } else { 275 /* NCRCFG2_FE enables > 64K transfers */ 276 sc->sc_cfg2 |= NCRCFG2_FE; 277 sc->sc_cfg3 = 0; 278 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 279 sc->sc_rev = NCR_VARIANT_ESP200; 280 } 281 } 282 283 /* 284 * XXX minsync and maxxfer _should_ be set up in MI code, 285 * XXX but it appears to have some dependency on what sort 286 * XXX of DMA we're hooked up to, etc. 287 */ 288 289 /* 290 * This is the value used to start sync negotiations 291 * Note that the NCR register "SYNCTP" is programmed 292 * in "clocks per byte", and has a minimum value of 4. 293 * The SCSI period used in negotiation is one-fourth 294 * of the time (in nanoseconds) needed to transfer one byte. 295 * Since the chip's clock is given in MHz, we have the following 296 * formula: 4 * period = (1000 / freq) * 4 297 */ 298 sc->sc_minsync = 1000 / sc->sc_freq; 299 300 /* 301 * Alas, we must now modify the value a bit, because it's 302 * only valid when can switch on FASTCLK and FASTSCSI bits 303 * in config register 3... 304 */ 305 switch (sc->sc_rev) { 306 case NCR_VARIANT_ESP100: 307 sc->sc_maxxfer = 64 * 1024; 308 sc->sc_minsync = 0; /* No synch on old chip? */ 309 break; 310 311 case NCR_VARIANT_ESP100A: 312 sc->sc_maxxfer = 64 * 1024; 313 /* Min clocks/byte is 5 */ 314 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 315 break; 316 317 case NCR_VARIANT_ESP200: 318 sc->sc_maxxfer = 16 * 1024 * 1024; 319 /* XXX - do actually set FAST* bits */ 320 break; 321 } 322 323 /* @@@ Some ESP_DCTL bits probably need setting */ 324 NCR_WRITE_REG(sc, ESP_DCTL, 325 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 326 DELAY(10); 327 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 328 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 329 DELAY(10); 330 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 331 332 /* Set up SCSI DMA */ 333 { 334 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 335 336 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 337 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 338 panic("\n%s: can't map scsi DMA registers", 339 sc->sc_dev.dv_xname); 340 } 341 342 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 343 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 344 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 345 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 346 esc->sc_scsi_dma.nd_cb_arg = sc; 347 nextdma_config(&esc->sc_scsi_dma); 348 nextdma_init(&esc->sc_scsi_dma); 349 350 #if 0 351 /* Turn on target selection using the `dma' method */ 352 ncr53c9x_dmaselect = 1; 353 #else 354 ncr53c9x_dmaselect = 0; 355 #endif 356 357 esc->sc_datain = -1; 358 esc->sc_dmaaddr = 0; 359 esc->sc_dmalen = 0; 360 esc->sc_dmasize = 0; 361 362 esc->sc_loaded = 0; 363 364 esc->sc_begin = 0; 365 esc->sc_begin_size = 0; 366 367 { 368 int error; 369 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 370 sc->sc_maxxfer, sc->sc_maxxfer/NBPG, sc->sc_maxxfer, 371 0, BUS_DMA_ALLOCNOW, &esc->sc_main_dmamap)) != 0) { 372 panic("%s: can't create main i/o DMA map, error = %d", 373 sc->sc_dev.dv_xname,error); 374 } 375 } 376 esc->sc_main = 0; 377 esc->sc_main_size = 0; 378 379 { 380 int error; 381 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 382 ESP_DMA_TAILBUFSIZE, 383 1, ESP_DMA_TAILBUFSIZE, 384 0, BUS_DMA_ALLOCNOW, &esc->sc_tail_dmamap)) != 0) { 385 panic("%s: can't create tail i/o DMA map, error = %d", 386 sc->sc_dev.dv_xname,error); 387 } 388 } 389 esc->sc_tail = 0; 390 esc->sc_tail_size = 0; 391 392 } 393 394 /* Establish interrupt channel */ 395 isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc, 396 NEXT_I_IPL(NEXT_I_SCSI), 0); 397 INTR_ENABLE(NEXT_I_SCSI); 398 399 /* register interrupt stats */ 400 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 401 402 /* Do the common parts of attachment. */ 403 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 404 sc->sc_adapter.scsipi_minphys = minphys; 405 ncr53c9x_attach(sc, &esp_dev); 406 } 407 408 /* 409 * Glue functions. 410 */ 411 412 u_char 413 esp_read_reg(sc, reg) 414 struct ncr53c9x_softc *sc; 415 int reg; 416 { 417 struct esp_softc *esc = (struct esp_softc *)sc; 418 419 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 420 } 421 422 void 423 esp_write_reg(sc, reg, val) 424 struct ncr53c9x_softc *sc; 425 int reg; 426 u_char val; 427 { 428 struct esp_softc *esc = (struct esp_softc *)sc; 429 430 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 431 } 432 433 int 434 esp_dma_isintr(sc) 435 struct ncr53c9x_softc *sc; 436 { 437 struct esp_softc *esc = (struct esp_softc *)sc; 438 439 int r = (INTR_OCCURRED(NEXT_I_SCSI)); 440 441 if (r) { 442 443 { 444 int s; 445 s = spldma(); 446 447 #ifdef ESP_DEBUG 448 esp_dma_nest++; 449 #endif 450 451 DPRINTF(("esp_dma_isintr = 0x%b\n", 452 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS)); 453 454 while (esp_dma_isactive(sc)) { 455 456 #ifdef DIAGNOSTIC 457 r = (INTR_OCCURRED(NEXT_I_SCSI)); 458 if (!r) panic("esp intr enabled but dma failed to flush"); 459 #endif 460 461 if (esc->sc_datain) { 462 NCR_WRITE_REG(sc, ESP_DCTL, 463 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD | ESPDCTL_FLUSH); 464 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 465 NCR_WRITE_REG(sc, ESP_DCTL, 466 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 467 } else { 468 NCR_WRITE_REG(sc, ESP_DCTL, 469 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_FLUSH); 470 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 471 NCR_WRITE_REG(sc, ESP_DCTL, 472 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 473 } 474 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 475 476 /* Really this code should only be used in polled mode */ 477 { 478 int nr; 479 nr = nextdma_intr(&esc->sc_scsi_dma); 480 if (nr) { 481 DPRINTF(("nextma_intr = %d\n",nr)); 482 } 483 } 484 } 485 486 #ifdef ESP_DEBUG 487 esp_dma_nest--; 488 #endif 489 490 splx(s); 491 } 492 493 #ifdef DIAGNOSTIC 494 r = (INTR_OCCURRED(NEXT_I_SCSI)); 495 if (!r) panic("esp intr not enabled after dma flush"); 496 #endif 497 498 /* Clear the DMAMOD bit in the DCTL register, since if this 499 * routine returns true, then the ncr53c9x_intr handler will 500 * be called and needs access to the scsi registers. 501 */ 502 if (esc->sc_datain) { 503 NCR_WRITE_REG(sc, ESP_DCTL, 504 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 505 } else { 506 NCR_WRITE_REG(sc, ESP_DCTL, 507 ESPDCTL_20MHZ | ESPDCTL_INTENB); 508 } 509 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 510 511 } 512 513 return (r); 514 } 515 516 void 517 esp_dma_reset(sc) 518 struct ncr53c9x_softc *sc; 519 { 520 struct esp_softc *esc = (struct esp_softc *)sc; 521 522 DPRINTF(("esp dma reset\n")); 523 524 #ifdef ESP_DEBUG 525 if (esp_debug) { 526 printf(" *intrstat = 0x%b\n", 527 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS); 528 printf(" *intrmask = 0x%b\n", 529 (*(volatile u_long *)IIOV(NEXT_P_INTRMASK)),NEXT_INTR_BITS); 530 } 531 #endif 532 533 /* Clear the DMAMOD bit in the DCTL register: */ 534 NCR_WRITE_REG(sc, ESP_DCTL, 535 ESPDCTL_20MHZ | ESPDCTL_INTENB); 536 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 537 538 nextdma_reset(&esc->sc_scsi_dma); 539 540 esc->sc_datain = -1; 541 esc->sc_dmaaddr = 0; 542 esc->sc_dmalen = 0; 543 esc->sc_dmasize = 0; 544 545 esc->sc_loaded = 0; 546 547 esc->sc_begin = 0; 548 esc->sc_begin_size = 0; 549 550 if (esc->sc_main_dmamap->dm_mapsize) { 551 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 552 } 553 esc->sc_main = 0; 554 esc->sc_main_size = 0; 555 556 if (esc->sc_tail_dmamap->dm_mapsize) { 557 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 558 } 559 esc->sc_tail = 0; 560 esc->sc_tail_size = 0; 561 } 562 563 int 564 esp_dma_intr(sc) 565 struct ncr53c9x_softc *sc; 566 { 567 #ifdef DIAGNOSTIC 568 panic("%s: esp_dma_intr shouldn't be invoked.\n", sc->sc_dev.dv_xname); 569 #endif 570 571 return -1; 572 } 573 574 /* it appears that: 575 * addr and len arguments to this need to be kept up to date 576 * with the status of the transfter. 577 * the dmasize of this is the actual length of the transfer 578 * request, which is guaranteed to be less than maxxfer. 579 * (len may be > maxxfer) 580 */ 581 582 int 583 esp_dma_setup(sc, addr, len, datain, dmasize) 584 struct ncr53c9x_softc *sc; 585 caddr_t *addr; 586 size_t *len; 587 int datain; 588 size_t *dmasize; 589 { 590 struct esp_softc *esc = (struct esp_softc *)sc; 591 592 #ifdef DIAGNOSTIC 593 #ifdef ESP_DEBUG 594 /* if this is a read DMA, pre-fill the buffer with 0xdeadbeef 595 * to identify bogus reads 596 */ 597 if (datain) { 598 int *v = (int *)(*addr); 599 int i; 600 for(i=0;i<((*len)/4);i++) v[i] = 0xdeadbeef; 601 v = (int *)(&(esc->sc_tailbuf[0])); 602 for(i=0;i<((sizeof(esc->sc_tailbuf)/4));i++) v[i] = 0xdeaffeed; 603 } 604 #endif 605 #endif 606 607 DPRINTF(("esp_dma_setup(0x%08lx,0x%08lx,0x%08lx)\n",*addr,*len,*dmasize)); 608 609 #ifdef DIAGNOSTIC /* @@@ this is ok sometimes. verify that we handle it ok 610 * and then remove this check 611 */ 612 if (*len != *dmasize) { 613 panic("esp dmalen != size"); 614 } 615 #endif 616 617 #ifdef DIAGNOSTIC 618 if ((esc->sc_datain != -1) || 619 (esc->sc_main_dmamap->dm_mapsize != 0) || 620 (esc->sc_tail_dmamap->dm_mapsize != 0) || 621 (esc->sc_dmasize != 0)) { 622 panic("%s: map already loaded in esp_dma_setup\n" 623 "\tdatain = %d\n\tmain_mapsize=%d\n\tail_mapsize=%d\n\tdmasize = %d", 624 sc->sc_dev.dv_xname, esc->sc_datain, 625 esc->sc_main_dmamap->dm_mapsize, 626 esc->sc_tail_dmamap->dm_mapsize, 627 esc->sc_dmasize); 628 } 629 #endif 630 631 /* we are sometimes asked to dma zero bytes, that's easy */ 632 if (*len <= 0) { 633 return(0); 634 } 635 636 /* Save these in case we have to abort DMA */ 637 esc->sc_datain = datain; 638 esc->sc_dmaaddr = addr; 639 esc->sc_dmalen = len; 640 esc->sc_dmasize = *dmasize; 641 642 esc->sc_loaded = 0; 643 644 { 645 size_t slop_bgn_size; /* # bytes to be fifo'd at beginning */ 646 size_t slop_end_size; /* # bytes to be transferred in tail buffer */ 647 648 { 649 u_long bgn = (u_long)(*esc->sc_dmaaddr); 650 u_long end = (u_long)(*esc->sc_dmaaddr+esc->sc_dmasize); 651 652 slop_bgn_size = DMA_BEGINALIGNMENT-(bgn % DMA_BEGINALIGNMENT); 653 if (slop_bgn_size == DMA_BEGINALIGNMENT) slop_bgn_size = 0; 654 slop_end_size = (end % DMA_ENDALIGNMENT); 655 } 656 657 /* Check to make sure we haven't counted extra slop 658 * as would happen for a very short dma buffer, also 659 * for short buffers, just stuff the entire thing in the tail 660 */ 661 if ((slop_bgn_size+slop_end_size >= esc->sc_dmasize) 662 #if 0 663 || (esc->sc_dmasize <= ESP_DMA_MAXTAIL) 664 #endif 665 ) 666 { 667 slop_bgn_size = 0; 668 slop_end_size = esc->sc_dmasize; 669 } 670 671 /* initialize the fifo buffer */ 672 if (slop_bgn_size) { 673 esc->sc_begin = *esc->sc_dmaaddr; 674 esc->sc_begin_size = slop_bgn_size; 675 } else { 676 esc->sc_begin = 0; 677 esc->sc_begin_size = 0; 678 } 679 680 /* Load the normal DMA map */ 681 { 682 esc->sc_main = *esc->sc_dmaaddr+slop_bgn_size; 683 esc->sc_main_size = (esc->sc_dmasize)-(slop_end_size+slop_bgn_size); 684 685 if (esc->sc_main_size) { 686 int error; 687 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 688 esc->sc_main_dmamap, 689 esc->sc_main, esc->sc_main_size, 690 NULL, BUS_DMA_NOWAIT); 691 if (error) { 692 panic("%s: can't load main dma map. error = %d, addr=0x%08x, size=0x%08x", 693 sc->sc_dev.dv_xname, error,esc->sc_main,esc->sc_main_size); 694 } 695 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 696 0, esc->sc_main_dmamap->dm_mapsize, 697 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 698 } else { 699 esc->sc_main = 0; 700 } 701 } 702 703 /* Load the tail DMA map */ 704 if (slop_end_size) { 705 esc->sc_tail = DMA_ENDALIGN(caddr_t,esc->sc_tailbuf+slop_end_size)-slop_end_size; 706 /* If the beginning of the tail is not correctly aligned, 707 * we have no choice but to align the start, which might then unalign the end. 708 */ 709 esc->sc_tail = DMA_ALIGN(caddr_t,esc->sc_tail); 710 /* So therefore, we change the tail size to be end aligned again. */ 711 esc->sc_tail_size = DMA_ENDALIGN(caddr_t,esc->sc_tail+slop_end_size)-esc->sc_tail; 712 713 /* @@@ next dma overrun lossage */ 714 if (!esc->sc_datain) { 715 esc->sc_tail_size += ESP_DMA_OVERRUN; 716 } 717 718 { 719 int error; 720 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 721 esc->sc_tail_dmamap, 722 esc->sc_tail, esc->sc_tail_size, 723 NULL, BUS_DMA_NOWAIT); 724 if (error) { 725 panic("%s: can't load tail dma map. error = %d, addr=0x%08x, size=0x%08x", 726 sc->sc_dev.dv_xname, error,esc->sc_tail,esc->sc_tail_size); 727 } 728 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 729 0, esc->sc_tail_dmamap->dm_mapsize, 730 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 731 } 732 } 733 } 734 735 return (0); 736 } 737 738 #ifdef ESP_DEBUG 739 /* For debugging */ 740 void 741 esp_dma_store(sc) 742 struct ncr53c9x_softc *sc; 743 { 744 struct esp_softc *esc = (struct esp_softc *)sc; 745 char *p = &esp_dma_dump[0]; 746 747 p += sprintf(p,"%s: sc_datain=%d\n",sc->sc_dev.dv_xname,esc->sc_datain); 748 p += sprintf(p,"%s: sc_loaded=0x%08x\n",sc->sc_dev.dv_xname,esc->sc_loaded); 749 750 if (esc->sc_dmaaddr) { 751 p += sprintf(p,"%s: sc_dmaaddr=0x%08lx\n",sc->sc_dev.dv_xname,*esc->sc_dmaaddr); 752 } else { 753 p += sprintf(p,"%s: sc_dmaaddr=NULL\n",sc->sc_dev.dv_xname); 754 } 755 if (esc->sc_dmalen) { 756 p += sprintf(p,"%s: sc_dmalen=0x%08lx\n",sc->sc_dev.dv_xname,*esc->sc_dmalen); 757 } else { 758 p += sprintf(p,"%s: sc_dmalen=NULL\n",sc->sc_dev.dv_xname); 759 } 760 p += sprintf(p,"%s: sc_dmasize=0x%08x\n",sc->sc_dev.dv_xname,esc->sc_dmasize); 761 762 p += sprintf(p,"%s: sc_begin = 0x%08x, sc_begin_size = 0x%08x\n", 763 sc->sc_dev.dv_xname, esc->sc_begin, esc->sc_begin_size); 764 p += sprintf(p,"%s: sc_main = 0x%08x, sc_main_size = 0x%08x\n", 765 sc->sc_dev.dv_xname, esc->sc_main, esc->sc_main_size); 766 { 767 int i; 768 bus_dmamap_t map = esc->sc_main_dmamap; 769 p += sprintf(p,"%s: sc_main_dmamap. mapsize = 0x%08x, nsegs = %d\n", 770 sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs); 771 for(i=0;i<map->dm_nsegs;i++) { 772 p += sprintf(p,"%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n", 773 sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len); 774 } 775 } 776 p += sprintf(p,"%s: sc_tail = 0x%08x, sc_tail_size = 0x%08x\n", 777 sc->sc_dev.dv_xname, esc->sc_tail, esc->sc_tail_size); 778 { 779 int i; 780 bus_dmamap_t map = esc->sc_tail_dmamap; 781 p += sprintf(p,"%s: sc_tail_dmamap. mapsize = 0x%08x, nsegs = %d\n", 782 sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs); 783 for(i=0;i<map->dm_nsegs;i++) { 784 p += sprintf(p,"%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n", 785 sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len); 786 } 787 } 788 } 789 790 void 791 esp_dma_print(sc) 792 struct ncr53c9x_softc *sc; 793 { 794 esp_dma_store(sc); 795 printf("%s",esp_dma_dump); 796 } 797 #endif 798 799 void 800 esp_dma_go(sc) 801 struct ncr53c9x_softc *sc; 802 { 803 struct esp_softc *esc = (struct esp_softc *)sc; 804 805 DPRINTF(("%s: esp_dma_go(datain = %d)\n", 806 sc->sc_dev.dv_xname, esc->sc_datain)); 807 808 #ifdef ESP_DEBUG 809 if (esp_debug) esp_dma_print(sc); 810 else esp_dma_store(sc); 811 #endif 812 813 #ifdef ESP_DEBUG 814 { 815 int n = NCR_READ_REG(sc, NCR_FFLAG); 816 DPRINTF(("%s: fifo size = %d, seq = 0x%x\n", 817 sc->sc_dev.dv_xname, 818 n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 819 } 820 #endif 821 822 /* zero length dma transfers are boring, dmasize is probably -1 in those cases 823 * because it was never set up by esp_dma_setup 824 */ 825 if (esc->sc_dmasize == 0) { 826 return; 827 } 828 829 #if defined(DIAGNOSTIC) 830 if ((esc->sc_begin_size == 0) && 831 (esc->sc_main_dmamap->dm_mapsize == 0) && 832 (esc->sc_tail_dmamap->dm_mapsize == 0)) { 833 esp_dma_print(sc); 834 panic("%s: No DMA requested!",sc->sc_dev.dv_xname); 835 } 836 #endif 837 838 /* Stuff the fifo with the begin buffer */ 839 if (esc->sc_datain) { 840 int i; 841 for(i=0;i<esc->sc_begin_size;i++) { 842 esc->sc_begin[i]=NCR_READ_REG(sc, NCR_FIFO); 843 } 844 } else { 845 int i; 846 for(i=0;i<esc->sc_begin_size;i++) { 847 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_begin[i]); 848 } 849 } 850 851 /* if we are a dma write cycle, copy the end slop */ 852 if (esc->sc_datain == 0) { 853 memcpy(esc->sc_tail, 854 (*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size), 855 (esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size))); 856 } 857 858 nextdma_start(&esc->sc_scsi_dma, 859 (esc->sc_datain ? DMACSR_READ : DMACSR_WRITE)); 860 861 if (esc->sc_datain) { 862 NCR_WRITE_REG(sc, ESP_DCTL, 863 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 864 } else { 865 NCR_WRITE_REG(sc, ESP_DCTL, 866 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 867 } 868 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 869 } 870 871 void 872 esp_dma_stop(sc) 873 struct ncr53c9x_softc *sc; 874 { 875 panic("Not yet implemented"); 876 } 877 878 int 879 esp_dma_isactive(sc) 880 struct ncr53c9x_softc *sc; 881 { 882 struct esp_softc *esc = (struct esp_softc *)sc; 883 int r = !nextdma_finished(&esc->sc_scsi_dma); 884 DPRINTF(("esp_dma_isactive = %d\n",r)); 885 return(r); 886 } 887 888 /****************************************************************/ 889 890 /* Internal dma callback routines */ 891 bus_dmamap_t 892 esp_dmacb_continue(arg) 893 void *arg; 894 { 895 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 896 struct esp_softc *esc = (struct esp_softc *)sc; 897 898 DPRINTF(("%s: dma continue\n",sc->sc_dev.dv_xname)); 899 900 #ifdef DIAGNOSTIC 901 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 902 panic("%s: map not loaded in dma continue callback, datain = %d", 903 sc->sc_dev.dv_xname,esc->sc_datain); 904 } 905 #endif 906 907 if ((!(esc->sc_loaded & ESP_LOADED_MAIN)) && 908 (esc->sc_main_dmamap->dm_mapsize)) { 909 DPRINTF(("%s: Loading main map\n",sc->sc_dev.dv_xname)); 910 #if 0 911 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 912 0, esc->sc_main_dmamap->dm_mapsize, 913 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 914 #endif 915 esc->sc_loaded |= ESP_LOADED_MAIN; 916 return(esc->sc_main_dmamap); 917 } 918 919 if ((!(esc->sc_loaded & ESP_LOADED_TAIL)) && 920 (esc->sc_tail_dmamap->dm_mapsize)) { 921 DPRINTF(("%s: Loading tail map\n",sc->sc_dev.dv_xname)); 922 #if 0 923 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 924 0, esc->sc_tail_dmamap->dm_mapsize, 925 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 926 #endif 927 esc->sc_loaded |= ESP_LOADED_TAIL; 928 return(esc->sc_tail_dmamap); 929 } 930 931 DPRINTF(("%s: not loading map\n",sc->sc_dev.dv_xname)); 932 return(0); 933 } 934 935 936 void 937 esp_dmacb_completed(map, arg) 938 bus_dmamap_t map; 939 void *arg; 940 { 941 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 942 struct esp_softc *esc = (struct esp_softc *)sc; 943 944 DPRINTF(("%s: dma completed\n",sc->sc_dev.dv_xname)); 945 946 #ifdef DIAGNOSTIC 947 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 948 panic("%s: invalid dma direction in completed callback, datain = %d", 949 sc->sc_dev.dv_xname,esc->sc_datain); 950 } 951 if ((map != esc->sc_main_dmamap) && (map != esc->sc_tail_dmamap)) { 952 panic("%s: unexpected completed map", sc->sc_dev.dv_xname); 953 } 954 #endif 955 956 957 #if 0 958 if ((map == esc->sc_tail_dmamap) || 959 ((esc->sc_tail_size == 0) && (map == esc->sc_main_dmamap))) { 960 961 /* Clear the DMAMOD bit in the DCTL register to give control 962 * back to the scsi chip. 963 */ 964 if (esc->sc_datain) { 965 NCR_WRITE_REG(sc, ESP_DCTL, 966 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 967 } else { 968 NCR_WRITE_REG(sc, ESP_DCTL, 969 ESPDCTL_20MHZ | ESPDCTL_INTENB); 970 } 971 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 972 } 973 #endif 974 975 976 #if 0 977 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, map, 978 0, map->dm_mapsize, 979 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 980 #endif 981 982 } 983 984 void 985 esp_dmacb_shutdown(arg) 986 void *arg; 987 { 988 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 989 struct esp_softc *esc = (struct esp_softc *)sc; 990 991 DPRINTF(("%s: dma shutdown\n",sc->sc_dev.dv_xname)); 992 993 #if 0 994 { 995 /* Clear the DMAMOD bit in the DCTL register to give control 996 * back to the scsi chip. 997 */ 998 if (esc->sc_datain) { 999 NCR_WRITE_REG(sc, ESP_DCTL, 1000 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 1001 } else { 1002 NCR_WRITE_REG(sc, ESP_DCTL, 1003 ESPDCTL_20MHZ | ESPDCTL_INTENB); 1004 } 1005 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 1006 } 1007 #endif 1008 1009 DPRINTF(("%s: esp_dma_nest == %d\n",sc->sc_dev.dv_xname,esp_dma_nest)); 1010 1011 /* Stuff the end slop into fifo */ 1012 1013 #ifdef ESP_DEBUG 1014 if (esp_debug) { 1015 1016 int n = NCR_READ_REG(sc, NCR_FFLAG); 1017 DPRINTF(("%s: fifo size = %d, seq = 0x%x\n", 1018 sc->sc_dev.dv_xname,n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 1019 1020 NCR_DMA(("%s:dmaintr: tcl=%d, tcm=%d, tch=%d\n", 1021 sc->sc_dev.dv_xname, 1022 NCR_READ_REG(sc, NCR_TCL), 1023 NCR_READ_REG(sc, NCR_TCM), 1024 (sc->sc_cfg2 & NCRCFG2_FE) 1025 ? NCR_READ_REG(sc, NCR_TCH) : 0)); 1026 } 1027 #endif 1028 1029 if (esc->sc_main_dmamap->dm_mapsize) { 1030 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 1031 0, esc->sc_main_dmamap->dm_mapsize, 1032 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1033 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 1034 } 1035 1036 if (esc->sc_tail_dmamap->dm_mapsize) { 1037 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 1038 0, esc->sc_tail_dmamap->dm_mapsize, 1039 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1040 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 1041 } 1042 1043 /* copy the tail dma buffer data for read transfers */ 1044 if (esc->sc_datain == 1) { 1045 memcpy((*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size), 1046 esc->sc_tail, 1047 (esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size))); 1048 } 1049 1050 #ifdef ESP_DEBUG 1051 if (esp_debug) { 1052 printf("%s: dma_shutdown: addr=0x%08lx,len=0x%08lx,size=0x%08lx\n", 1053 sc->sc_dev.dv_xname, 1054 *esc->sc_dmaaddr, *esc->sc_dmalen, esc->sc_dmasize); 1055 esp_hex_dump(*(esc->sc_dmaaddr),esc->sc_dmasize); 1056 printf("%s: tail=0x%08lx,tailbuf=0x%08lx,tail_size=0x%08lx\n", 1057 sc->sc_dev.dv_xname, 1058 esc->sc_tail, &(esc->sc_tailbuf[0]), esc->sc_tail_size); 1059 esp_hex_dump(&(esc->sc_tailbuf[0]),sizeof(esc->sc_tailbuf)); 1060 } 1061 #endif 1062 1063 *(esc->sc_dmaaddr) += esc->sc_dmasize; 1064 *(esc->sc_dmalen) -= esc->sc_dmasize; 1065 1066 esc->sc_main = 0; 1067 esc->sc_main_size = 0; 1068 esc->sc_tail = 0; 1069 esc->sc_tail_size = 0; 1070 1071 esc->sc_datain = -1; 1072 esc->sc_dmaaddr = 0; 1073 esc->sc_dmalen = 0; 1074 esc->sc_dmasize = 0; 1075 1076 esc->sc_loaded = 0; 1077 1078 esc->sc_begin = 0; 1079 esc->sc_begin_size = 0; 1080 1081 #ifdef ESP_DEBUG 1082 if (esp_debug) { 1083 printf(" *intrstat = 0x%b\n", 1084 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS); 1085 printf(" *intrmask = 0x%b\n", 1086 (*(volatile u_long *)IIOV(NEXT_P_INTRMASK)),NEXT_INTR_BITS); 1087 } 1088 #endif 1089 } 1090
Indexes created Wed Sep 24 02:09:48 GMT 2025