esp.c revision 1.23
1 /* $NetBSD: esp.c,v 1.23 1999/03/14 10:31:05 dbj Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Grabbed from the sparc port at revision 1.73 for the NeXT. 81 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 82 */ 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/device.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 #include <sys/user.h> 94 #include <sys/queue.h> 95 96 #include <dev/scsipi/scsi_all.h> 97 #include <dev/scsipi/scsipi_all.h> 98 #include <dev/scsipi/scsiconf.h> 99 #include <dev/scsipi/scsi_message.h> 100 101 #include <machine/bus.h> 102 #include <machine/autoconf.h> 103 #include <machine/cpu.h> 104 105 #include <dev/ic/ncr53c9xreg.h> 106 #include <dev/ic/ncr53c9xvar.h> 107 108 #include <next68k/next68k/isr.h> 109 110 #include <next68k/dev/nextdmareg.h> 111 #include <next68k/dev/nextdmavar.h> 112 113 #include "espreg.h" 114 #include "espvar.h" 115 116 #ifdef DEBUG 117 #define ESP_DEBUG 118 #endif 119 120 #ifdef ESP_DEBUG 121 int esp_debug = 0; 122 #define DPRINTF(x) if (esp_debug) printf x; 123 #else 124 #define DPRINTF(x) 125 #endif 126 127 128 void espattach_intio __P((struct device *, struct device *, void *)); 129 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 130 131 /* DMA callbacks */ 132 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 133 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 134 void esp_dmacb_shutdown __P((void *arg)); 135 136 #ifdef ESP_DEBUG 137 char esp_dma_dump[5*1024] = ""; 138 struct ncr53c9x_softc *esp_debug_sc = 0; 139 void esp_dma_store __P((struct ncr53c9x_softc *sc)); 140 void esp_dma_print __P((struct ncr53c9x_softc *sc)); 141 int esp_dma_nest = 0; 142 #endif 143 144 145 /* Linkup to the rest of the kernel */ 146 struct cfattach esp_ca = { 147 sizeof(struct esp_softc), espmatch_intio, espattach_intio 148 }; 149 150 struct scsipi_device esp_dev = { 151 NULL, /* Use default error handler */ 152 NULL, /* have a queue, served by this */ 153 NULL, /* have no async handler */ 154 NULL, /* Use default 'done' routine */ 155 }; 156 157 /* 158 * Functions and the switch for the MI code. 159 */ 160 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 161 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 162 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 163 void esp_dma_reset __P((struct ncr53c9x_softc *)); 164 int esp_dma_intr __P((struct ncr53c9x_softc *)); 165 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 166 size_t *, int, size_t *)); 167 void esp_dma_go __P((struct ncr53c9x_softc *)); 168 void esp_dma_stop __P((struct ncr53c9x_softc *)); 169 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 170 171 struct ncr53c9x_glue esp_glue = { 172 esp_read_reg, 173 esp_write_reg, 174 esp_dma_isintr, 175 esp_dma_reset, 176 esp_dma_intr, 177 esp_dma_setup, 178 esp_dma_go, 179 esp_dma_stop, 180 esp_dma_isactive, 181 NULL, /* gl_clear_latched_intr */ 182 }; 183 184 #ifdef ESP_DEBUG 185 #define XCHR(x) "0123456789abcdef"[(x) & 0xf] 186 static void 187 esp_hex_dump(unsigned char *pkt, size_t len) 188 { 189 size_t i, j; 190 191 printf("0000: "); 192 for(i=0; i<len; i++) { 193 printf("%c%c ", XCHR(pkt[i]>>4), XCHR(pkt[i])); 194 if ((i+1) % 16 == 0) { 195 printf(" %c", '"'); 196 for(j=0; j<16; j++) 197 printf("%c", pkt[i-15+j]>=32 && pkt[i-15+j]<127?pkt[i-15+j]:'.'); 198 printf("%c\n%c%c%c%c: ", '"', XCHR((i+1)>>12), 199 XCHR((i+1)>>8), XCHR((i+1)>>4), XCHR(i+1)); 200 } 201 } 202 printf("\n"); 203 } 204 #endif 205 206 int 207 espmatch_intio(parent, cf, aux) 208 struct device *parent; 209 struct cfdata *cf; 210 void *aux; 211 { 212 /* should probably probe here */ 213 /* Should also probably set up data from config */ 214 215 return(1); 216 } 217 218 void 219 espattach_intio(parent, self, aux) 220 struct device *parent, *self; 221 void *aux; 222 { 223 struct esp_softc *esc = (void *)self; 224 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 225 226 #ifdef ESP_DEBUG 227 esp_debug_sc = sc; 228 #endif 229 230 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 231 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 232 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 233 panic("\n%s: can't map ncr53c90 registers", 234 sc->sc_dev.dv_xname); 235 } 236 237 sc->sc_id = 7; 238 sc->sc_freq = 20; /* Mhz */ 239 240 /* 241 * Set up glue for MI code early; we use some of it here. 242 */ 243 sc->sc_glue = &esp_glue; 244 245 /* 246 * XXX More of this should be in ncr53c9x_attach(), but 247 * XXX should we really poke around the chip that much in 248 * XXX the MI code? Think about this more... 249 */ 250 251 /* 252 * It is necessary to try to load the 2nd config register here, 253 * to find out what rev the esp chip is, else the ncr53c9x_reset 254 * will not set up the defaults correctly. 255 */ 256 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 257 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 258 sc->sc_cfg3 = NCRCFG3_CDB; 259 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 260 261 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 262 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 263 sc->sc_rev = NCR_VARIANT_ESP100; 264 } else { 265 sc->sc_cfg2 = NCRCFG2_SCSI2; 266 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 267 sc->sc_cfg3 = 0; 268 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 269 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 270 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 271 if (NCR_READ_REG(sc, NCR_CFG3) != 272 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 273 sc->sc_rev = NCR_VARIANT_ESP100A; 274 } else { 275 /* NCRCFG2_FE enables > 64K transfers */ 276 sc->sc_cfg2 |= NCRCFG2_FE; 277 sc->sc_cfg3 = 0; 278 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 279 sc->sc_rev = NCR_VARIANT_ESP200; 280 } 281 } 282 283 /* 284 * XXX minsync and maxxfer _should_ be set up in MI code, 285 * XXX but it appears to have some dependency on what sort 286 * XXX of DMA we're hooked up to, etc. 287 */ 288 289 /* 290 * This is the value used to start sync negotiations 291 * Note that the NCR register "SYNCTP" is programmed 292 * in "clocks per byte", and has a minimum value of 4. 293 * The SCSI period used in negotiation is one-fourth 294 * of the time (in nanoseconds) needed to transfer one byte. 295 * Since the chip's clock is given in MHz, we have the following 296 * formula: 4 * period = (1000 / freq) * 4 297 */ 298 sc->sc_minsync = 1000 / sc->sc_freq; 299 300 /* 301 * Alas, we must now modify the value a bit, because it's 302 * only valid when can switch on FASTCLK and FASTSCSI bits 303 * in config register 3... 304 */ 305 switch (sc->sc_rev) { 306 case NCR_VARIANT_ESP100: 307 sc->sc_maxxfer = 64 * 1024; 308 sc->sc_minsync = 0; /* No synch on old chip? */ 309 break; 310 311 case NCR_VARIANT_ESP100A: 312 sc->sc_maxxfer = 64 * 1024; 313 /* Min clocks/byte is 5 */ 314 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 315 break; 316 317 case NCR_VARIANT_ESP200: 318 sc->sc_maxxfer = 16 * 1024 * 1024; 319 /* XXX - do actually set FAST* bits */ 320 break; 321 } 322 323 /* @@@ Some ESP_DCTL bits probably need setting */ 324 NCR_WRITE_REG(sc, ESP_DCTL, 325 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 326 DELAY(10); 327 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 328 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 329 DELAY(10); 330 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 331 332 /* Set up SCSI DMA */ 333 { 334 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 335 336 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 337 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 338 panic("\n%s: can't map scsi DMA registers", 339 sc->sc_dev.dv_xname); 340 } 341 342 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 343 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 344 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 345 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 346 esc->sc_scsi_dma.nd_cb_arg = sc; 347 nextdma_config(&esc->sc_scsi_dma); 348 nextdma_init(&esc->sc_scsi_dma); 349 350 #if 0 351 /* Turn on target selection using the `dma' method */ 352 ncr53c9x_dmaselect = 1; 353 #else 354 ncr53c9x_dmaselect = 0; 355 #endif 356 357 esc->sc_datain = -1; 358 esc->sc_dmaaddr = 0; 359 esc->sc_dmalen = 0; 360 esc->sc_dmasize = 0; 361 362 esc->sc_loaded = 0; 363 364 esc->sc_begin = 0; 365 esc->sc_begin_size = 0; 366 367 { 368 int error; 369 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 370 sc->sc_maxxfer, sc->sc_maxxfer/NBPG, sc->sc_maxxfer, 371 0, BUS_DMA_ALLOCNOW, &esc->sc_main_dmamap)) != 0) { 372 panic("%s: can't create main i/o DMA map, error = %d", 373 sc->sc_dev.dv_xname,error); 374 } 375 } 376 esc->sc_main = 0; 377 esc->sc_main_size = 0; 378 379 { 380 int error; 381 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 382 ESP_DMA_TAILBUFSIZE, 383 1, ESP_DMA_TAILBUFSIZE, 384 0, BUS_DMA_ALLOCNOW, &esc->sc_tail_dmamap)) != 0) { 385 panic("%s: can't create tail i/o DMA map, error = %d", 386 sc->sc_dev.dv_xname,error); 387 } 388 } 389 esc->sc_tail = 0; 390 esc->sc_tail_size = 0; 391 392 } 393 394 /* Establish interrupt channel */ 395 isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc, 396 NEXT_I_IPL(NEXT_I_SCSI), 0); 397 INTR_ENABLE(NEXT_I_SCSI); 398 399 /* register interrupt stats */ 400 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 401 402 /* Do the common parts of attachment. */ 403 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 404 sc->sc_adapter.scsipi_minphys = minphys; 405 ncr53c9x_attach(sc, &esp_dev); 406 } 407 408 /* 409 * Glue functions. 410 */ 411 412 u_char 413 esp_read_reg(sc, reg) 414 struct ncr53c9x_softc *sc; 415 int reg; 416 { 417 struct esp_softc *esc = (struct esp_softc *)sc; 418 419 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 420 } 421 422 void 423 esp_write_reg(sc, reg, val) 424 struct ncr53c9x_softc *sc; 425 int reg; 426 u_char val; 427 { 428 struct esp_softc *esc = (struct esp_softc *)sc; 429 430 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 431 } 432 433 int 434 esp_dma_isintr(sc) 435 struct ncr53c9x_softc *sc; 436 { 437 struct esp_softc *esc = (struct esp_softc *)sc; 438 439 int r = (INTR_OCCURRED(NEXT_I_SCSI)); 440 441 if (r) { 442 443 { 444 int flushcount; 445 int s; 446 s = spldma(); 447 448 flushcount = 0; 449 450 #ifdef ESP_DEBUG 451 esp_dma_nest++; 452 #endif 453 454 DPRINTF(("esp_dma_isintr = 0x%b\n", 455 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS)); 456 457 while (esp_dma_isactive(sc)) { 458 flushcount++; 459 460 #ifdef DIAGNOSTIC 461 r = (INTR_OCCURRED(NEXT_I_SCSI)); 462 if (!r) panic("esp intr enabled but dma failed to flush"); 463 #endif 464 #ifdef DIAGNOSTIC 465 #if 0 466 if ((esc->sc_loaded & (ESP_LOADED_TAIL/* |ESP_UNLOADED_MAIN */)) 467 != (ESP_LOADED_TAIL /* |ESP_UNLOADED_MAIN */)) { 468 if (esc->sc_datain) { 469 NCR_WRITE_REG(sc, ESP_DCTL, 470 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 471 } else { 472 NCR_WRITE_REG(sc, ESP_DCTL, 473 ESPDCTL_20MHZ | ESPDCTL_INTENB); 474 } 475 next_dma_print(&esc->sc_scsi_dma); 476 esp_dma_print(sc); 477 printf("%s: unexpected flush: tc=0x%06x\n", 478 sc->sc_dev.dv_xname, 479 (((sc->sc_cfg2 & NCRCFG2_FE) 480 ? NCR_READ_REG(sc, NCR_TCH) : 0)<<16)| 481 (NCR_READ_REG(sc, NCR_TCM)<<8)| 482 NCR_READ_REG(sc, NCR_TCL)); 483 ncr53c9x_readregs(sc); 484 printf("%s: readregs[intr=%02x,stat=%02x,step=%02x]\n", 485 sc->sc_dev.dv_xname, 486 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep); 487 panic("%s: flushing flushing non-tail dma\n", 488 sc->sc_dev.dv_xname); 489 } 490 #endif 491 #endif 492 DPRINTF(("%s: flushing dma, count = %d\n", sc->sc_dev.dv_xname,flushcount)); 493 if (esc->sc_datain) { 494 NCR_WRITE_REG(sc, ESP_DCTL, 495 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD | ESPDCTL_FLUSH); 496 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 497 NCR_WRITE_REG(sc, ESP_DCTL, 498 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 499 } else { 500 NCR_WRITE_REG(sc, ESP_DCTL, 501 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_FLUSH); 502 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 503 NCR_WRITE_REG(sc, ESP_DCTL, 504 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 505 } 506 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 507 508 { 509 int nr; 510 nr = nextdma_intr(&esc->sc_scsi_dma); 511 if (nr) { 512 DPRINTF(("nextma_intr = %d\n",nr)); 513 #ifdef DIAGNOSTIC 514 #if 0 515 if (flushcount > 16) { 516 printf("%s: unexpected flushcount %d\n",sc->sc_dev.dv_xname,flushcount); 517 } 518 #endif 519 #endif 520 #ifdef DIAGNOSTIC 521 #if 0 522 if (esp_dma_isactive(sc)) { 523 esp_dma_print(sc); 524 printf("%s: dma still active after a flush with count %d\n", 525 sc->sc_dev.dv_xname,flushcount); 526 527 } 528 #endif 529 #endif 530 flushcount = 0; 531 } 532 } 533 } 534 535 #ifdef ESP_DEBUG 536 esp_dma_nest--; 537 #endif 538 539 splx(s); 540 } 541 542 #ifdef DIAGNOSTIC 543 r = (INTR_OCCURRED(NEXT_I_SCSI)); 544 if (!r) panic("esp intr not enabled after dma flush"); 545 #endif 546 547 /* Clear the DMAMOD bit in the DCTL register, since if this 548 * routine returns true, then the ncr53c9x_intr handler will 549 * be called and needs access to the scsi registers. 550 */ 551 if (esc->sc_datain) { 552 NCR_WRITE_REG(sc, ESP_DCTL, 553 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 554 } else { 555 NCR_WRITE_REG(sc, ESP_DCTL, 556 ESPDCTL_20MHZ | ESPDCTL_INTENB); 557 } 558 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 559 560 } 561 562 return (r); 563 } 564 565 void 566 esp_dma_reset(sc) 567 struct ncr53c9x_softc *sc; 568 { 569 struct esp_softc *esc = (struct esp_softc *)sc; 570 571 DPRINTF(("esp dma reset\n")); 572 573 #ifdef ESP_DEBUG 574 if (esp_debug) { 575 printf(" *intrstat = 0x%b\n", 576 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS); 577 printf(" *intrmask = 0x%b\n", 578 (*(volatile u_long *)IIOV(NEXT_P_INTRMASK)),NEXT_INTR_BITS); 579 } 580 #endif 581 582 /* Clear the DMAMOD bit in the DCTL register: */ 583 NCR_WRITE_REG(sc, ESP_DCTL, 584 ESPDCTL_20MHZ | ESPDCTL_INTENB); 585 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 586 587 nextdma_reset(&esc->sc_scsi_dma); 588 589 esc->sc_datain = -1; 590 esc->sc_dmaaddr = 0; 591 esc->sc_dmalen = 0; 592 esc->sc_dmasize = 0; 593 594 esc->sc_loaded = 0; 595 596 esc->sc_begin = 0; 597 esc->sc_begin_size = 0; 598 599 if (esc->sc_main_dmamap->dm_mapsize) { 600 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 601 } 602 esc->sc_main = 0; 603 esc->sc_main_size = 0; 604 605 if (esc->sc_tail_dmamap->dm_mapsize) { 606 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 607 } 608 esc->sc_tail = 0; 609 esc->sc_tail_size = 0; 610 } 611 612 int 613 esp_dma_intr(sc) 614 struct ncr53c9x_softc *sc; 615 { 616 #ifdef DIAGNOSTIC 617 panic("%s: esp_dma_intr shouldn't be invoked.\n", sc->sc_dev.dv_xname); 618 #endif 619 620 return -1; 621 } 622 623 /* it appears that: 624 * addr and len arguments to this need to be kept up to date 625 * with the status of the transfter. 626 * the dmasize of this is the actual length of the transfer 627 * request, which is guaranteed to be less than maxxfer. 628 * (len may be > maxxfer) 629 */ 630 631 int 632 esp_dma_setup(sc, addr, len, datain, dmasize) 633 struct ncr53c9x_softc *sc; 634 caddr_t *addr; 635 size_t *len; 636 int datain; 637 size_t *dmasize; 638 { 639 struct esp_softc *esc = (struct esp_softc *)sc; 640 641 #ifdef DIAGNOSTIC 642 #ifdef ESP_DEBUG 643 /* if this is a read DMA, pre-fill the buffer with 0xdeadbeef 644 * to identify bogus reads 645 */ 646 if (datain) { 647 int *v = (int *)(*addr); 648 int i; 649 for(i=0;i<((*len)/4);i++) v[i] = 0xdeadbeef; 650 v = (int *)(&(esc->sc_tailbuf[0])); 651 for(i=0;i<((sizeof(esc->sc_tailbuf)/4));i++) v[i] = 0xdeaffeed; 652 } else { 653 int *v; 654 int i; 655 v = (int *)(&(esc->sc_tailbuf[0])); 656 for(i=0;i<((sizeof(esc->sc_tailbuf)/4));i++) v[i] = 0xfeeb1eed; 657 } 658 #endif 659 #endif 660 661 DPRINTF(("esp_dma_setup(0x%08lx,0x%08lx,0x%08lx)\n",*addr,*len,*dmasize)); 662 663 #ifdef DIAGNOSTIC /* @@@ this is ok sometimes. verify that we handle it ok 664 * and then remove this check 665 */ 666 if (*len != *dmasize) { 667 panic("esp dmalen 0x%lx != size 0x%lx",*len,*dmasize); 668 } 669 #endif 670 671 #ifdef DIAGNOSTIC 672 if ((esc->sc_datain != -1) || 673 (esc->sc_main_dmamap->dm_mapsize != 0) || 674 (esc->sc_tail_dmamap->dm_mapsize != 0) || 675 (esc->sc_dmasize != 0)) { 676 panic("%s: map already loaded in esp_dma_setup\n" 677 "\tdatain = %d\n\tmain_mapsize=%d\n\tail_mapsize=%d\n\tdmasize = %d", 678 sc->sc_dev.dv_xname, esc->sc_datain, 679 esc->sc_main_dmamap->dm_mapsize, 680 esc->sc_tail_dmamap->dm_mapsize, 681 esc->sc_dmasize); 682 } 683 #endif 684 685 /* we are sometimes asked to dma zero bytes, that's easy */ 686 if (*len <= 0) { 687 return(0); 688 } 689 690 /* Save these in case we have to abort DMA */ 691 esc->sc_datain = datain; 692 esc->sc_dmaaddr = addr; 693 esc->sc_dmalen = len; 694 esc->sc_dmasize = *dmasize; 695 696 esc->sc_loaded = 0; 697 698 #define DMA_SCSI_ALIGNMENT 16 699 #define DMA_SCSI_ALIGN(type, addr) \ 700 ((type)(((unsigned)(addr)+DMA_SCSI_ALIGNMENT-1) \ 701 &~(DMA_SCSI_ALIGNMENT-1))) 702 #define DMA_SCSI_ALIGNED(addr) \ 703 (((unsigned)(addr)&(DMA_SCSI_ALIGNMENT-1))==0) 704 705 { 706 size_t slop_bgn_size; /* # bytes to be fifo'd at beginning */ 707 size_t slop_end_size; /* # bytes to be transferred in tail buffer */ 708 709 { 710 u_long bgn = (u_long)(*esc->sc_dmaaddr); 711 u_long end = (u_long)(*esc->sc_dmaaddr+esc->sc_dmasize); 712 713 slop_bgn_size = DMA_SCSI_ALIGNMENT-(bgn % DMA_SCSI_ALIGNMENT); 714 if (slop_bgn_size == DMA_SCSI_ALIGNMENT) slop_bgn_size = 0; 715 slop_end_size = (end % DMA_ENDALIGNMENT); 716 } 717 718 /* Force a minimum slop end size. This ensures that write 719 * requests will overrun, as required to get completion interrupts. 720 * In addition, since the tail buffer is guaranteed to be mapped 721 * in a single dma segment, the overrun won't accidentally 722 * end up in its own segment. 723 */ 724 if (!esc->sc_datain) { 725 slop_end_size += ESP_DMA_MAXTAIL; 726 } 727 728 /* Check to make sure we haven't counted extra slop 729 * as would happen for a very short dma buffer, also 730 * for short buffers, just stuff the entire thing in the tail 731 */ 732 if ((slop_bgn_size+slop_end_size >= esc->sc_dmasize) 733 #if 0 734 || (esc->sc_dmasize <= ESP_DMA_MAXTAIL) 735 #endif 736 ) 737 { 738 slop_bgn_size = 0; 739 slop_end_size = esc->sc_dmasize; 740 } 741 742 /* initialize the fifo buffer */ 743 if (slop_bgn_size) { 744 esc->sc_begin = *esc->sc_dmaaddr; 745 esc->sc_begin_size = slop_bgn_size; 746 } else { 747 esc->sc_begin = 0; 748 esc->sc_begin_size = 0; 749 } 750 751 /* Load the normal DMA map */ 752 { 753 esc->sc_main = *esc->sc_dmaaddr+slop_bgn_size; 754 esc->sc_main_size = (esc->sc_dmasize)-(slop_end_size+slop_bgn_size); 755 756 if (esc->sc_main_size) { 757 int error; 758 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 759 esc->sc_main_dmamap, 760 esc->sc_main, esc->sc_main_size, 761 NULL, BUS_DMA_NOWAIT); 762 if (error) { 763 panic("%s: can't load main dma map. error = %d, addr=0x%08x, size=0x%08x", 764 sc->sc_dev.dv_xname, error,esc->sc_main,esc->sc_main_size); 765 } 766 #if 0 767 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 768 0, esc->sc_main_dmamap->dm_mapsize, 769 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 770 #endif 771 } else { 772 esc->sc_main = 0; 773 } 774 } 775 776 /* Load the tail DMA map */ 777 if (slop_end_size) { 778 esc->sc_tail = DMA_ENDALIGN(caddr_t,esc->sc_tailbuf+slop_end_size)-slop_end_size; 779 /* If the beginning of the tail is not correctly aligned, 780 * we have no choice but to align the start, which might then unalign the end. 781 */ 782 esc->sc_tail = DMA_SCSI_ALIGN(caddr_t,esc->sc_tail); 783 /* So therefore, we change the tail size to be end aligned again. */ 784 esc->sc_tail_size = DMA_ENDALIGN(caddr_t,esc->sc_tail+slop_end_size)-esc->sc_tail; 785 786 /* @@@ next dma overrun lossage */ 787 if (!esc->sc_datain) { 788 esc->sc_tail_size += ESP_DMA_OVERRUN; 789 } 790 791 { 792 int error; 793 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 794 esc->sc_tail_dmamap, 795 esc->sc_tail, esc->sc_tail_size, 796 NULL, BUS_DMA_NOWAIT); 797 if (error) { 798 panic("%s: can't load tail dma map. error = %d, addr=0x%08x, size=0x%08x", 799 sc->sc_dev.dv_xname, error,esc->sc_tail,esc->sc_tail_size); 800 } 801 #if 0 802 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 803 0, esc->sc_tail_dmamap->dm_mapsize, 804 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 805 #endif 806 } 807 } 808 } 809 810 return (0); 811 } 812 813 #ifdef ESP_DEBUG 814 /* For debugging */ 815 void 816 esp_dma_store(sc) 817 struct ncr53c9x_softc *sc; 818 { 819 struct esp_softc *esc = (struct esp_softc *)sc; 820 char *p = &esp_dma_dump[0]; 821 822 p += sprintf(p,"%s: sc_datain=%d\n",sc->sc_dev.dv_xname,esc->sc_datain); 823 p += sprintf(p,"%s: sc_loaded=0x%08x\n",sc->sc_dev.dv_xname,esc->sc_loaded); 824 825 if (esc->sc_dmaaddr) { 826 p += sprintf(p,"%s: sc_dmaaddr=0x%08lx\n",sc->sc_dev.dv_xname,*esc->sc_dmaaddr); 827 } else { 828 p += sprintf(p,"%s: sc_dmaaddr=NULL\n",sc->sc_dev.dv_xname); 829 } 830 if (esc->sc_dmalen) { 831 p += sprintf(p,"%s: sc_dmalen=0x%08lx\n",sc->sc_dev.dv_xname,*esc->sc_dmalen); 832 } else { 833 p += sprintf(p,"%s: sc_dmalen=NULL\n",sc->sc_dev.dv_xname); 834 } 835 p += sprintf(p,"%s: sc_dmasize=0x%08x\n",sc->sc_dev.dv_xname,esc->sc_dmasize); 836 837 p += sprintf(p,"%s: sc_begin = 0x%08x, sc_begin_size = 0x%08x\n", 838 sc->sc_dev.dv_xname, esc->sc_begin, esc->sc_begin_size); 839 p += sprintf(p,"%s: sc_main = 0x%08x, sc_main_size = 0x%08x\n", 840 sc->sc_dev.dv_xname, esc->sc_main, esc->sc_main_size); 841 { 842 int i; 843 bus_dmamap_t map = esc->sc_main_dmamap; 844 p += sprintf(p,"%s: sc_main_dmamap. mapsize = 0x%08x, nsegs = %d\n", 845 sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs); 846 for(i=0;i<map->dm_nsegs;i++) { 847 p += sprintf(p,"%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n", 848 sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len); 849 } 850 } 851 p += sprintf(p,"%s: sc_tail = 0x%08x, sc_tail_size = 0x%08x\n", 852 sc->sc_dev.dv_xname, esc->sc_tail, esc->sc_tail_size); 853 { 854 int i; 855 bus_dmamap_t map = esc->sc_tail_dmamap; 856 p += sprintf(p,"%s: sc_tail_dmamap. mapsize = 0x%08x, nsegs = %d\n", 857 sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs); 858 for(i=0;i<map->dm_nsegs;i++) { 859 p += sprintf(p,"%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n", 860 sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len); 861 } 862 } 863 } 864 865 void 866 esp_dma_print(sc) 867 struct ncr53c9x_softc *sc; 868 { 869 esp_dma_store(sc); 870 printf("%s",esp_dma_dump); 871 } 872 #endif 873 874 void 875 esp_dma_go(sc) 876 struct ncr53c9x_softc *sc; 877 { 878 struct esp_softc *esc = (struct esp_softc *)sc; 879 880 DPRINTF(("%s: esp_dma_go(datain = %d)\n", 881 sc->sc_dev.dv_xname, esc->sc_datain)); 882 883 #ifdef ESP_DEBUG 884 if (esp_debug) esp_dma_print(sc); 885 else esp_dma_store(sc); 886 #endif 887 888 #ifdef ESP_DEBUG 889 { 890 int n = NCR_READ_REG(sc, NCR_FFLAG); 891 DPRINTF(("%s: fifo size = %d, seq = 0x%x\n", 892 sc->sc_dev.dv_xname, 893 n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 894 } 895 #endif 896 897 /* zero length dma transfers are boring */ 898 if (esc->sc_dmasize == 0) { 899 return; 900 } 901 902 #if defined(DIAGNOSTIC) 903 if ((esc->sc_begin_size == 0) && 904 (esc->sc_main_dmamap->dm_mapsize == 0) && 905 (esc->sc_tail_dmamap->dm_mapsize == 0)) { 906 esp_dma_print(sc); 907 panic("%s: No DMA requested!",sc->sc_dev.dv_xname); 908 } 909 #endif 910 911 /* Stuff the fifo with the begin buffer */ 912 if (esc->sc_datain) { 913 int i; 914 DPRINTF(("%s: FIFO read of %d bytes:", 915 sc->sc_dev.dv_xname,esc->sc_begin_size)); 916 for(i=0;i<esc->sc_begin_size;i++) { 917 esc->sc_begin[i]=NCR_READ_REG(sc, NCR_FIFO)&0xff; 918 DPRINTF((" %02x",esc->sc_begin[i])); 919 } 920 DPRINTF(("\n")); 921 } else { 922 int i; 923 DPRINTF(("%s: FIFO write of %d bytes:", 924 sc->sc_dev.dv_xname,esc->sc_begin_size)); 925 for(i=0;i<esc->sc_begin_size;i++) { 926 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_begin[i]); 927 DPRINTF((" %02x",esc->sc_begin[i])); 928 } 929 DPRINTF(("\n")); 930 } 931 932 /* if we are a dma write cycle, copy the end slop */ 933 if (esc->sc_datain == 0) { 934 memcpy(esc->sc_tail, 935 (*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size), 936 (esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size))); 937 } 938 939 if (esc->sc_main_dmamap->dm_mapsize) { 940 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 941 0, esc->sc_main_dmamap->dm_mapsize, 942 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 943 } 944 945 if (esc->sc_tail_dmamap->dm_mapsize) { 946 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 947 0, esc->sc_tail_dmamap->dm_mapsize, 948 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 949 } 950 951 nextdma_start(&esc->sc_scsi_dma, 952 (esc->sc_datain ? DMACSR_READ : DMACSR_WRITE)); 953 954 if (esc->sc_datain) { 955 NCR_WRITE_REG(sc, ESP_DCTL, 956 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 957 } else { 958 NCR_WRITE_REG(sc, ESP_DCTL, 959 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 960 } 961 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 962 } 963 964 void 965 esp_dma_stop(sc) 966 struct ncr53c9x_softc *sc; 967 { 968 panic("Not yet implemented"); 969 } 970 971 int 972 esp_dma_isactive(sc) 973 struct ncr53c9x_softc *sc; 974 { 975 struct esp_softc *esc = (struct esp_softc *)sc; 976 int r = !nextdma_finished(&esc->sc_scsi_dma); 977 DPRINTF(("esp_dma_isactive = %d\n",r)); 978 return(r); 979 } 980 981 /****************************************************************/ 982 983 /* Internal dma callback routines */ 984 bus_dmamap_t 985 esp_dmacb_continue(arg) 986 void *arg; 987 { 988 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 989 struct esp_softc *esc = (struct esp_softc *)sc; 990 991 DPRINTF(("%s: dma continue\n",sc->sc_dev.dv_xname)); 992 993 #ifdef DIAGNOSTIC 994 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 995 panic("%s: map not loaded in dma continue callback, datain = %d", 996 sc->sc_dev.dv_xname,esc->sc_datain); 997 } 998 #endif 999 1000 if ((!(esc->sc_loaded & ESP_LOADED_MAIN)) && 1001 (esc->sc_main_dmamap->dm_mapsize)) { 1002 DPRINTF(("%s: Loading main map\n",sc->sc_dev.dv_xname)); 1003 #if 0 1004 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 1005 0, esc->sc_main_dmamap->dm_mapsize, 1006 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1007 #endif 1008 esc->sc_loaded |= ESP_LOADED_MAIN; 1009 return(esc->sc_main_dmamap); 1010 } 1011 1012 if ((!(esc->sc_loaded & ESP_LOADED_TAIL)) && 1013 (esc->sc_tail_dmamap->dm_mapsize)) { 1014 DPRINTF(("%s: Loading tail map\n",sc->sc_dev.dv_xname)); 1015 #if 0 1016 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 1017 0, esc->sc_tail_dmamap->dm_mapsize, 1018 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1019 #endif 1020 esc->sc_loaded |= ESP_LOADED_TAIL; 1021 return(esc->sc_tail_dmamap); 1022 } 1023 1024 DPRINTF(("%s: not loading map\n",sc->sc_dev.dv_xname)); 1025 return(0); 1026 } 1027 1028 1029 void 1030 esp_dmacb_completed(map, arg) 1031 bus_dmamap_t map; 1032 void *arg; 1033 { 1034 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1035 struct esp_softc *esc = (struct esp_softc *)sc; 1036 1037 DPRINTF(("%s: dma completed\n",sc->sc_dev.dv_xname)); 1038 1039 #ifdef DIAGNOSTIC 1040 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 1041 panic("%s: invalid dma direction in completed callback, datain = %d", 1042 sc->sc_dev.dv_xname,esc->sc_datain); 1043 } 1044 #endif 1045 1046 if (map == esc->sc_main_dmamap) { 1047 #ifdef DIAGNOSTIC 1048 if ((esc->sc_loaded & ESP_UNLOADED_MAIN) || 1049 !(esc->sc_loaded & ESP_LOADED_MAIN)) { 1050 panic("%s: unexpected completed call for main map\n",sc->sc_dev.dv_xname); 1051 } 1052 #endif 1053 esc->sc_loaded |= ESP_UNLOADED_MAIN; 1054 } else if (map == esc->sc_tail_dmamap) { 1055 #ifdef DIAGNOSTIC 1056 if ((esc->sc_loaded & ESP_UNLOADED_TAIL) || 1057 !(esc->sc_loaded & ESP_LOADED_TAIL)) { 1058 panic("%s: unexpected completed call for tail map\n",sc->sc_dev.dv_xname); 1059 } 1060 #endif 1061 esc->sc_loaded |= ESP_UNLOADED_TAIL; 1062 } 1063 #ifdef DIAGNOSTIC 1064 else { 1065 panic("%s: unexpected completed map", sc->sc_dev.dv_xname); 1066 } 1067 #endif 1068 1069 #ifdef ESP_DEBUG 1070 if (esp_debug) { 1071 if (map == esc->sc_main_dmamap) { 1072 printf("%s: completed main map\n",sc->sc_dev.dv_xname); 1073 } else if (map == esc->sc_tail_dmamap) { 1074 printf("%s: completed tail map\n",sc->sc_dev.dv_xname); 1075 } 1076 } 1077 #endif 1078 1079 #if 0 1080 if ((map == esc->sc_tail_dmamap) || 1081 ((esc->sc_tail_size == 0) && (map == esc->sc_main_dmamap))) { 1082 1083 /* Clear the DMAMOD bit in the DCTL register to give control 1084 * back to the scsi chip. 1085 */ 1086 if (esc->sc_datain) { 1087 NCR_WRITE_REG(sc, ESP_DCTL, 1088 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 1089 } else { 1090 NCR_WRITE_REG(sc, ESP_DCTL, 1091 ESPDCTL_20MHZ | ESPDCTL_INTENB); 1092 } 1093 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 1094 } 1095 #endif 1096 1097 1098 #if 0 1099 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, map, 1100 0, map->dm_mapsize, 1101 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1102 #endif 1103 1104 } 1105 1106 void 1107 esp_dmacb_shutdown(arg) 1108 void *arg; 1109 { 1110 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1111 struct esp_softc *esc = (struct esp_softc *)sc; 1112 1113 DPRINTF(("%s: dma shutdown\n",sc->sc_dev.dv_xname)); 1114 1115 #if 0 1116 { 1117 /* Clear the DMAMOD bit in the DCTL register to give control 1118 * back to the scsi chip. 1119 */ 1120 if (esc->sc_datain) { 1121 NCR_WRITE_REG(sc, ESP_DCTL, 1122 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 1123 } else { 1124 NCR_WRITE_REG(sc, ESP_DCTL, 1125 ESPDCTL_20MHZ | ESPDCTL_INTENB); 1126 } 1127 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 1128 } 1129 #endif 1130 1131 DPRINTF(("%s: esp_dma_nest == %d\n",sc->sc_dev.dv_xname,esp_dma_nest)); 1132 1133 /* Stuff the end slop into fifo */ 1134 1135 #ifdef ESP_DEBUG 1136 if (esp_debug) { 1137 1138 int n = NCR_READ_REG(sc, NCR_FFLAG); 1139 DPRINTF(("%s: fifo size = %d, seq = 0x%x\n", 1140 sc->sc_dev.dv_xname,n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 1141 } 1142 #endif 1143 1144 if (esc->sc_main_dmamap->dm_mapsize) { 1145 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 1146 0, esc->sc_main_dmamap->dm_mapsize, 1147 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1148 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 1149 } 1150 1151 if (esc->sc_tail_dmamap->dm_mapsize) { 1152 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 1153 0, esc->sc_tail_dmamap->dm_mapsize, 1154 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1155 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 1156 } 1157 1158 /* copy the tail dma buffer data for read transfers */ 1159 if (esc->sc_datain == 1) { 1160 memcpy((*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size), 1161 esc->sc_tail, 1162 (esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size))); 1163 } 1164 1165 #ifdef ESP_DEBUG 1166 if (esp_debug) { 1167 printf("%s: dma_shutdown: addr=0x%08lx,len=0x%08lx,size=0x%08lx\n", 1168 sc->sc_dev.dv_xname, 1169 *esc->sc_dmaaddr, *esc->sc_dmalen, esc->sc_dmasize); 1170 esp_hex_dump(*(esc->sc_dmaaddr),(esc->sc_dmasize<=1200)?esc->sc_dmasize:1200); 1171 printf("%s: tail=0x%08lx,tailbuf=0x%08lx,tail_size=0x%08lx\n", 1172 sc->sc_dev.dv_xname, 1173 esc->sc_tail, &(esc->sc_tailbuf[0]), esc->sc_tail_size); 1174 esp_hex_dump(&(esc->sc_tailbuf[0]),sizeof(esc->sc_tailbuf)); 1175 } 1176 #endif 1177 1178 *(esc->sc_dmaaddr) += esc->sc_dmasize; 1179 *(esc->sc_dmalen) -= esc->sc_dmasize; 1180 1181 esc->sc_main = 0; 1182 esc->sc_main_size = 0; 1183 esc->sc_tail = 0; 1184 esc->sc_tail_size = 0; 1185 1186 esc->sc_datain = -1; 1187 esc->sc_dmaaddr = 0; 1188 esc->sc_dmalen = 0; 1189 esc->sc_dmasize = 0; 1190 1191 esc->sc_loaded = 0; 1192 1193 esc->sc_begin = 0; 1194 esc->sc_begin_size = 0; 1195 1196 #ifdef ESP_DEBUG 1197 if (esp_debug) { 1198 printf(" *intrstat = 0x%b\n", 1199 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS); 1200 printf(" *intrmask = 0x%b\n", 1201 (*(volatile u_long *)IIOV(NEXT_P_INTRMASK)),NEXT_INTR_BITS); 1202 } 1203 #endif 1204 } 1205
Indexes created Wed Sep 24 05:09:52 GMT 2025