esp.c revision 1.25
1 /* $NetBSD: esp.c,v 1.25 1999/08/28 09:19:04 dbj Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Grabbed from the sparc port at revision 1.73 for the NeXT. 81 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 82 */ 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/device.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 #include <sys/user.h> 94 #include <sys/queue.h> 95 96 #include <dev/scsipi/scsi_all.h> 97 #include <dev/scsipi/scsipi_all.h> 98 #include <dev/scsipi/scsiconf.h> 99 #include <dev/scsipi/scsi_message.h> 100 101 #include <machine/bus.h> 102 #include <machine/autoconf.h> 103 #include <machine/cpu.h> 104 105 #include <dev/ic/ncr53c9xreg.h> 106 #include <dev/ic/ncr53c9xvar.h> 107 108 #include <next68k/next68k/isr.h> 109 110 #include <next68k/dev/nextdmareg.h> 111 #include <next68k/dev/nextdmavar.h> 112 113 #include "espreg.h" 114 #include "espvar.h" 115 116 #ifdef DEBUG 117 #define ESP_DEBUG 118 #endif 119 120 #ifdef ESP_DEBUG 121 int esp_debug = 0; 122 #define DPRINTF(x) if (esp_debug) printf x; 123 #else 124 #define DPRINTF(x) 125 #endif 126 127 128 void espattach_intio __P((struct device *, struct device *, void *)); 129 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 130 131 /* DMA callbacks */ 132 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 133 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 134 void esp_dmacb_shutdown __P((void *arg)); 135 136 #ifdef ESP_DEBUG 137 char esp_dma_dump[5*1024] = ""; 138 struct ncr53c9x_softc *esp_debug_sc = 0; 139 void esp_dma_store __P((struct ncr53c9x_softc *sc)); 140 void esp_dma_print __P((struct ncr53c9x_softc *sc)); 141 int esp_dma_nest = 0; 142 #endif 143 144 145 /* Linkup to the rest of the kernel */ 146 struct cfattach esp_ca = { 147 sizeof(struct esp_softc), espmatch_intio, espattach_intio 148 }; 149 150 struct scsipi_device esp_dev = { 151 NULL, /* Use default error handler */ 152 NULL, /* have a queue, served by this */ 153 NULL, /* have no async handler */ 154 NULL, /* Use default 'done' routine */ 155 }; 156 157 /* 158 * Functions and the switch for the MI code. 159 */ 160 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 161 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 162 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 163 void esp_dma_reset __P((struct ncr53c9x_softc *)); 164 int esp_dma_intr __P((struct ncr53c9x_softc *)); 165 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 166 size_t *, int, size_t *)); 167 void esp_dma_go __P((struct ncr53c9x_softc *)); 168 void esp_dma_stop __P((struct ncr53c9x_softc *)); 169 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 170 171 struct ncr53c9x_glue esp_glue = { 172 esp_read_reg, 173 esp_write_reg, 174 esp_dma_isintr, 175 esp_dma_reset, 176 esp_dma_intr, 177 esp_dma_setup, 178 esp_dma_go, 179 esp_dma_stop, 180 esp_dma_isactive, 181 NULL, /* gl_clear_latched_intr */ 182 }; 183 184 #ifdef ESP_DEBUG 185 #define XCHR(x) "0123456789abcdef"[(x) & 0xf] 186 static void 187 esp_hex_dump(unsigned char *pkt, size_t len) 188 { 189 size_t i, j; 190 191 printf("00000000 "); 192 for(i=0; i<len; i++) { 193 printf("%c%c ", XCHR(pkt[i]>>4), XCHR(pkt[i])); 194 if ((i+1) % 16 == 8) { 195 printf(" "); 196 } 197 if ((i+1) % 16 == 0) { 198 printf(" %c", '|'); 199 for(j=0; j<16; j++) { 200 printf("%c", pkt[i-15+j]>=32 && pkt[i-15+j]<127?pkt[i-15+j]:'.'); 201 } 202 printf("%c\n%c%c%c%c%c%c%c%c ", '|', 203 XCHR((i+1)>>28),XCHR((i+1)>>24),XCHR((i+1)>>20),XCHR((i+1)>>16), 204 XCHR((i+1)>>12), XCHR((i+1)>>8), XCHR((i+1)>>4), XCHR(i+1)); 205 } 206 } 207 printf("\n"); 208 } 209 #endif 210 211 int 212 espmatch_intio(parent, cf, aux) 213 struct device *parent; 214 struct cfdata *cf; 215 void *aux; 216 { 217 /* should probably probe here */ 218 /* Should also probably set up data from config */ 219 220 return(1); 221 } 222 223 void 224 espattach_intio(parent, self, aux) 225 struct device *parent, *self; 226 void *aux; 227 { 228 struct esp_softc *esc = (void *)self; 229 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 230 231 #ifdef ESP_DEBUG 232 esp_debug_sc = sc; 233 #endif 234 235 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 236 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 237 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 238 panic("\n%s: can't map ncr53c90 registers", 239 sc->sc_dev.dv_xname); 240 } 241 242 sc->sc_id = 7; 243 sc->sc_freq = 20; /* Mhz */ 244 245 /* 246 * Set up glue for MI code early; we use some of it here. 247 */ 248 sc->sc_glue = &esp_glue; 249 250 /* 251 * XXX More of this should be in ncr53c9x_attach(), but 252 * XXX should we really poke around the chip that much in 253 * XXX the MI code? Think about this more... 254 */ 255 256 /* 257 * It is necessary to try to load the 2nd config register here, 258 * to find out what rev the esp chip is, else the ncr53c9x_reset 259 * will not set up the defaults correctly. 260 */ 261 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 262 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 263 sc->sc_cfg3 = NCRCFG3_CDB; 264 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 265 266 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 267 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 268 sc->sc_rev = NCR_VARIANT_ESP100; 269 } else { 270 sc->sc_cfg2 = NCRCFG2_SCSI2; 271 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 272 sc->sc_cfg3 = 0; 273 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 274 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 275 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 276 if (NCR_READ_REG(sc, NCR_CFG3) != 277 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 278 sc->sc_rev = NCR_VARIANT_ESP100A; 279 } else { 280 /* NCRCFG2_FE enables > 64K transfers */ 281 sc->sc_cfg2 |= NCRCFG2_FE; 282 sc->sc_cfg3 = 0; 283 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 284 sc->sc_rev = NCR_VARIANT_ESP200; 285 } 286 } 287 288 /* 289 * XXX minsync and maxxfer _should_ be set up in MI code, 290 * XXX but it appears to have some dependency on what sort 291 * XXX of DMA we're hooked up to, etc. 292 */ 293 294 /* 295 * This is the value used to start sync negotiations 296 * Note that the NCR register "SYNCTP" is programmed 297 * in "clocks per byte", and has a minimum value of 4. 298 * The SCSI period used in negotiation is one-fourth 299 * of the time (in nanoseconds) needed to transfer one byte. 300 * Since the chip's clock is given in MHz, we have the following 301 * formula: 4 * period = (1000 / freq) * 4 302 */ 303 sc->sc_minsync = 1000 / sc->sc_freq; 304 305 /* 306 * Alas, we must now modify the value a bit, because it's 307 * only valid when can switch on FASTCLK and FASTSCSI bits 308 * in config register 3... 309 */ 310 switch (sc->sc_rev) { 311 case NCR_VARIANT_ESP100: 312 sc->sc_maxxfer = 64 * 1024; 313 sc->sc_minsync = 0; /* No synch on old chip? */ 314 break; 315 316 case NCR_VARIANT_ESP100A: 317 sc->sc_maxxfer = 64 * 1024; 318 /* Min clocks/byte is 5 */ 319 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 320 break; 321 322 case NCR_VARIANT_ESP200: 323 sc->sc_maxxfer = 16 * 1024 * 1024; 324 /* XXX - do actually set FAST* bits */ 325 break; 326 } 327 328 /* @@@ Some ESP_DCTL bits probably need setting */ 329 NCR_WRITE_REG(sc, ESP_DCTL, 330 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 331 DELAY(10); 332 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 333 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 334 DELAY(10); 335 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 336 337 /* Set up SCSI DMA */ 338 { 339 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 340 341 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 342 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 343 panic("\n%s: can't map scsi DMA registers", 344 sc->sc_dev.dv_xname); 345 } 346 347 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 348 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 349 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 350 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 351 esc->sc_scsi_dma.nd_cb_arg = sc; 352 nextdma_config(&esc->sc_scsi_dma); 353 nextdma_init(&esc->sc_scsi_dma); 354 355 #if 0 356 /* Turn on target selection using the `dma' method */ 357 ncr53c9x_dmaselect = 1; 358 #else 359 ncr53c9x_dmaselect = 0; 360 #endif 361 362 esc->sc_datain = -1; 363 esc->sc_dmaaddr = 0; 364 esc->sc_dmalen = 0; 365 esc->sc_dmasize = 0; 366 367 esc->sc_loaded = 0; 368 369 esc->sc_begin = 0; 370 esc->sc_begin_size = 0; 371 372 { 373 int error; 374 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 375 sc->sc_maxxfer, sc->sc_maxxfer/NBPG, sc->sc_maxxfer, 376 0, BUS_DMA_ALLOCNOW, &esc->sc_main_dmamap)) != 0) { 377 panic("%s: can't create main i/o DMA map, error = %d", 378 sc->sc_dev.dv_xname,error); 379 } 380 } 381 esc->sc_main = 0; 382 esc->sc_main_size = 0; 383 384 { 385 int error; 386 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 387 ESP_DMA_TAILBUFSIZE, 388 1, ESP_DMA_TAILBUFSIZE, 389 0, BUS_DMA_ALLOCNOW, &esc->sc_tail_dmamap)) != 0) { 390 panic("%s: can't create tail i/o DMA map, error = %d", 391 sc->sc_dev.dv_xname,error); 392 } 393 } 394 esc->sc_tail = 0; 395 esc->sc_tail_size = 0; 396 397 } 398 399 /* Establish interrupt channel */ 400 isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc, 401 NEXT_I_IPL(NEXT_I_SCSI), 0); 402 INTR_ENABLE(NEXT_I_SCSI); 403 404 /* register interrupt stats */ 405 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 406 407 /* Do the common parts of attachment. */ 408 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 409 sc->sc_adapter.scsipi_minphys = minphys; 410 ncr53c9x_attach(sc, &esp_dev); 411 } 412 413 /* 414 * Glue functions. 415 */ 416 417 u_char 418 esp_read_reg(sc, reg) 419 struct ncr53c9x_softc *sc; 420 int reg; 421 { 422 struct esp_softc *esc = (struct esp_softc *)sc; 423 424 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 425 } 426 427 void 428 esp_write_reg(sc, reg, val) 429 struct ncr53c9x_softc *sc; 430 int reg; 431 u_char val; 432 { 433 struct esp_softc *esc = (struct esp_softc *)sc; 434 435 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 436 } 437 438 int 439 esp_dma_isintr(sc) 440 struct ncr53c9x_softc *sc; 441 { 442 struct esp_softc *esc = (struct esp_softc *)sc; 443 444 int r = (INTR_OCCURRED(NEXT_I_SCSI)); 445 446 if (r) { 447 448 { 449 int flushcount; 450 int s; 451 s = spldma(); 452 453 flushcount = 0; 454 455 #ifdef ESP_DEBUG 456 esp_dma_nest++; 457 #endif 458 459 DPRINTF(("esp_dma_isintr = 0x%b\n", 460 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS)); 461 462 while (esp_dma_isactive(sc)) { 463 flushcount++; 464 465 #ifdef DIAGNOSTIC 466 r = (INTR_OCCURRED(NEXT_I_SCSI)); 467 if (!r) panic("esp intr enabled but dma failed to flush"); 468 #endif 469 #ifdef DIAGNOSTIC 470 #if 0 471 if ((esc->sc_loaded & (ESP_LOADED_TAIL/* |ESP_UNLOADED_MAIN */)) 472 != (ESP_LOADED_TAIL /* |ESP_UNLOADED_MAIN */)) { 473 if (esc->sc_datain) { 474 NCR_WRITE_REG(sc, ESP_DCTL, 475 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 476 } else { 477 NCR_WRITE_REG(sc, ESP_DCTL, 478 ESPDCTL_20MHZ | ESPDCTL_INTENB); 479 } 480 next_dma_print(&esc->sc_scsi_dma); 481 esp_dma_print(sc); 482 printf("%s: unexpected flush: tc=0x%06x\n", 483 sc->sc_dev.dv_xname, 484 (((sc->sc_cfg2 & NCRCFG2_FE) 485 ? NCR_READ_REG(sc, NCR_TCH) : 0)<<16)| 486 (NCR_READ_REG(sc, NCR_TCM)<<8)| 487 NCR_READ_REG(sc, NCR_TCL)); 488 ncr53c9x_readregs(sc); 489 printf("%s: readregs[intr=%02x,stat=%02x,step=%02x]\n", 490 sc->sc_dev.dv_xname, 491 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep); 492 panic("%s: flushing flushing non-tail dma\n", 493 sc->sc_dev.dv_xname); 494 } 495 #endif 496 #endif 497 DPRINTF(("%s: flushing dma, count = %d\n", sc->sc_dev.dv_xname,flushcount)); 498 if (esc->sc_datain) { 499 NCR_WRITE_REG(sc, ESP_DCTL, 500 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD | ESPDCTL_FLUSH); 501 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 502 NCR_WRITE_REG(sc, ESP_DCTL, 503 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 504 } else { 505 NCR_WRITE_REG(sc, ESP_DCTL, 506 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_FLUSH); 507 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 508 NCR_WRITE_REG(sc, ESP_DCTL, 509 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 510 } 511 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 512 513 { 514 int nr; 515 nr = nextdma_intr(&esc->sc_scsi_dma); 516 if (nr) { 517 DPRINTF(("nextma_intr = %d\n",nr)); 518 #ifdef DIAGNOSTIC 519 #if 0 520 if (flushcount > 16) { 521 printf("%s: unexpected flushcount %d\n",sc->sc_dev.dv_xname,flushcount); 522 } 523 #endif 524 #endif 525 #ifdef DIAGNOSTIC 526 #if 0 527 if (esp_dma_isactive(sc)) { 528 esp_dma_print(sc); 529 printf("%s: dma still active after a flush with count %d\n", 530 sc->sc_dev.dv_xname,flushcount); 531 532 } 533 #endif 534 #endif 535 flushcount = 0; 536 } 537 } 538 } 539 540 #ifdef ESP_DEBUG 541 esp_dma_nest--; 542 #endif 543 544 splx(s); 545 } 546 547 #ifdef DIAGNOSTIC 548 r = (INTR_OCCURRED(NEXT_I_SCSI)); 549 if (!r) panic("esp intr not enabled after dma flush"); 550 #endif 551 552 /* Clear the DMAMOD bit in the DCTL register, since if this 553 * routine returns true, then the ncr53c9x_intr handler will 554 * be called and needs access to the scsi registers. 555 */ 556 if (esc->sc_datain) { 557 NCR_WRITE_REG(sc, ESP_DCTL, 558 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 559 } else { 560 NCR_WRITE_REG(sc, ESP_DCTL, 561 ESPDCTL_20MHZ | ESPDCTL_INTENB); 562 } 563 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 564 565 } 566 567 return (r); 568 } 569 570 void 571 esp_dma_reset(sc) 572 struct ncr53c9x_softc *sc; 573 { 574 struct esp_softc *esc = (struct esp_softc *)sc; 575 576 DPRINTF(("esp dma reset\n")); 577 578 #ifdef ESP_DEBUG 579 if (esp_debug) { 580 printf(" *intrstat = 0x%b\n", 581 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS); 582 printf(" *intrmask = 0x%b\n", 583 (*(volatile u_long *)IIOV(NEXT_P_INTRMASK)),NEXT_INTR_BITS); 584 } 585 #endif 586 587 /* Clear the DMAMOD bit in the DCTL register: */ 588 NCR_WRITE_REG(sc, ESP_DCTL, 589 ESPDCTL_20MHZ | ESPDCTL_INTENB); 590 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 591 592 nextdma_reset(&esc->sc_scsi_dma); 593 594 esc->sc_datain = -1; 595 esc->sc_dmaaddr = 0; 596 esc->sc_dmalen = 0; 597 esc->sc_dmasize = 0; 598 599 esc->sc_loaded = 0; 600 601 esc->sc_begin = 0; 602 esc->sc_begin_size = 0; 603 604 if (esc->sc_main_dmamap->dm_mapsize) { 605 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 606 } 607 esc->sc_main = 0; 608 esc->sc_main_size = 0; 609 610 if (esc->sc_tail_dmamap->dm_mapsize) { 611 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 612 } 613 esc->sc_tail = 0; 614 esc->sc_tail_size = 0; 615 } 616 617 int 618 esp_dma_intr(sc) 619 struct ncr53c9x_softc *sc; 620 { 621 #ifdef DIAGNOSTIC 622 panic("%s: esp_dma_intr shouldn't be invoked.\n", sc->sc_dev.dv_xname); 623 #endif 624 625 return -1; 626 } 627 628 /* it appears that: 629 * addr and len arguments to this need to be kept up to date 630 * with the status of the transfter. 631 * the dmasize of this is the actual length of the transfer 632 * request, which is guaranteed to be less than maxxfer. 633 * (len may be > maxxfer) 634 */ 635 636 int 637 esp_dma_setup(sc, addr, len, datain, dmasize) 638 struct ncr53c9x_softc *sc; 639 caddr_t *addr; 640 size_t *len; 641 int datain; 642 size_t *dmasize; 643 { 644 struct esp_softc *esc = (struct esp_softc *)sc; 645 646 #ifdef DIAGNOSTIC 647 #ifdef ESP_DEBUG 648 /* if this is a read DMA, pre-fill the buffer with 0xdeadbeef 649 * to identify bogus reads 650 */ 651 if (datain) { 652 int *v = (int *)(*addr); 653 int i; 654 for(i=0;i<((*len)/4);i++) v[i] = 0xdeadbeef; 655 v = (int *)(&(esc->sc_tailbuf[0])); 656 for(i=0;i<((sizeof(esc->sc_tailbuf)/4));i++) v[i] = 0xdeaffeed; 657 } else { 658 int *v; 659 int i; 660 v = (int *)(&(esc->sc_tailbuf[0])); 661 for(i=0;i<((sizeof(esc->sc_tailbuf)/4));i++) v[i] = 0xfeeb1eed; 662 } 663 #endif 664 #endif 665 666 DPRINTF(("esp_dma_setup(0x%08lx,0x%08lx,0x%08lx)\n",*addr,*len,*dmasize)); 667 668 #if 0 669 #ifdef DIAGNOSTIC /* @@@ this is ok sometimes. verify that we handle it ok 670 * and then remove this check 671 */ 672 if (*len != *dmasize) { 673 panic("esp dmalen 0x%lx != size 0x%lx",*len,*dmasize); 674 } 675 #endif 676 #endif 677 678 #ifdef DIAGNOSTIC 679 if ((esc->sc_datain != -1) || 680 (esc->sc_main_dmamap->dm_mapsize != 0) || 681 (esc->sc_tail_dmamap->dm_mapsize != 0) || 682 (esc->sc_dmasize != 0)) { 683 panic("%s: map already loaded in esp_dma_setup\n" 684 "\tdatain = %d\n\tmain_mapsize=%d\n\tail_mapsize=%d\n\tdmasize = %d", 685 sc->sc_dev.dv_xname, esc->sc_datain, 686 esc->sc_main_dmamap->dm_mapsize, 687 esc->sc_tail_dmamap->dm_mapsize, 688 esc->sc_dmasize); 689 } 690 #endif 691 692 /* we are sometimes asked to dma zero bytes, that's easy */ 693 if (*dmasize <= 0) { 694 return(0); 695 } 696 697 /* Save these in case we have to abort DMA */ 698 esc->sc_datain = datain; 699 esc->sc_dmaaddr = addr; 700 esc->sc_dmalen = len; 701 esc->sc_dmasize = *dmasize; 702 703 esc->sc_loaded = 0; 704 705 #define DMA_SCSI_ALIGNMENT 16 706 #define DMA_SCSI_ALIGN(type, addr) \ 707 ((type)(((unsigned)(addr)+DMA_SCSI_ALIGNMENT-1) \ 708 &~(DMA_SCSI_ALIGNMENT-1))) 709 #define DMA_SCSI_ALIGNED(addr) \ 710 (((unsigned)(addr)&(DMA_SCSI_ALIGNMENT-1))==0) 711 712 { 713 size_t slop_bgn_size; /* # bytes to be fifo'd at beginning */ 714 size_t slop_end_size; /* # bytes to be transferred in tail buffer */ 715 716 { 717 u_long bgn = (u_long)(*esc->sc_dmaaddr); 718 u_long end = (u_long)(*esc->sc_dmaaddr+esc->sc_dmasize); 719 720 slop_bgn_size = DMA_SCSI_ALIGNMENT-(bgn % DMA_SCSI_ALIGNMENT); 721 if (slop_bgn_size == DMA_SCSI_ALIGNMENT) slop_bgn_size = 0; 722 slop_end_size = (end % DMA_ENDALIGNMENT); 723 } 724 725 /* Force a minimum slop end size. This ensures that write 726 * requests will overrun, as required to get completion interrupts. 727 * In addition, since the tail buffer is guaranteed to be mapped 728 * in a single dma segment, the overrun won't accidentally 729 * end up in its own segment. 730 */ 731 if (!esc->sc_datain) { 732 #if 0 733 slop_end_size += ESP_DMA_MAXTAIL; 734 #else 735 slop_end_size += 0x10; 736 #endif 737 } 738 739 /* Check to make sure we haven't counted extra slop 740 * as would happen for a very short dma buffer, also 741 * for short buffers, just stuff the entire thing in the tail 742 */ 743 if ((slop_bgn_size+slop_end_size >= esc->sc_dmasize) 744 #if 0 745 || (esc->sc_dmasize <= ESP_DMA_MAXTAIL) 746 #endif 747 ) 748 { 749 slop_bgn_size = 0; 750 slop_end_size = esc->sc_dmasize; 751 } 752 753 /* initialize the fifo buffer */ 754 if (slop_bgn_size) { 755 esc->sc_begin = *esc->sc_dmaaddr; 756 esc->sc_begin_size = slop_bgn_size; 757 } else { 758 esc->sc_begin = 0; 759 esc->sc_begin_size = 0; 760 } 761 762 /* Load the normal DMA map */ 763 { 764 esc->sc_main = *esc->sc_dmaaddr+slop_bgn_size; 765 esc->sc_main_size = (esc->sc_dmasize)-(slop_end_size+slop_bgn_size); 766 767 if (esc->sc_main_size) { 768 int error; 769 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 770 esc->sc_main_dmamap, 771 esc->sc_main, esc->sc_main_size, 772 NULL, BUS_DMA_NOWAIT); 773 if (error) { 774 panic("%s: can't load main dma map. error = %d, addr=0x%08x, size=0x%08x", 775 sc->sc_dev.dv_xname, error,esc->sc_main,esc->sc_main_size); 776 } 777 #if 0 778 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 779 0, esc->sc_main_dmamap->dm_mapsize, 780 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 781 #endif 782 } else { 783 esc->sc_main = 0; 784 } 785 } 786 787 /* Load the tail DMA map */ 788 if (slop_end_size) { 789 esc->sc_tail = DMA_ENDALIGN(caddr_t,esc->sc_tailbuf+slop_end_size)-slop_end_size; 790 /* If the beginning of the tail is not correctly aligned, 791 * we have no choice but to align the start, which might then unalign the end. 792 */ 793 esc->sc_tail = DMA_SCSI_ALIGN(caddr_t,esc->sc_tail); 794 /* So therefore, we change the tail size to be end aligned again. */ 795 esc->sc_tail_size = DMA_ENDALIGN(caddr_t,esc->sc_tail+slop_end_size)-esc->sc_tail; 796 797 /* @@@ next dma overrun lossage */ 798 if (!esc->sc_datain) { 799 esc->sc_tail_size += ESP_DMA_OVERRUN; 800 } 801 802 { 803 int error; 804 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 805 esc->sc_tail_dmamap, 806 esc->sc_tail, esc->sc_tail_size, 807 NULL, BUS_DMA_NOWAIT); 808 if (error) { 809 panic("%s: can't load tail dma map. error = %d, addr=0x%08x, size=0x%08x", 810 sc->sc_dev.dv_xname, error,esc->sc_tail,esc->sc_tail_size); 811 } 812 #if 0 813 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 814 0, esc->sc_tail_dmamap->dm_mapsize, 815 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 816 #endif 817 } 818 } 819 } 820 821 return (0); 822 } 823 824 #ifdef ESP_DEBUG 825 /* For debugging */ 826 void 827 esp_dma_store(sc) 828 struct ncr53c9x_softc *sc; 829 { 830 struct esp_softc *esc = (struct esp_softc *)sc; 831 char *p = &esp_dma_dump[0]; 832 833 p += sprintf(p,"%s: sc_datain=%d\n",sc->sc_dev.dv_xname,esc->sc_datain); 834 p += sprintf(p,"%s: sc_loaded=0x%08x\n",sc->sc_dev.dv_xname,esc->sc_loaded); 835 836 if (esc->sc_dmaaddr) { 837 p += sprintf(p,"%s: sc_dmaaddr=0x%08lx\n",sc->sc_dev.dv_xname,*esc->sc_dmaaddr); 838 } else { 839 p += sprintf(p,"%s: sc_dmaaddr=NULL\n",sc->sc_dev.dv_xname); 840 } 841 if (esc->sc_dmalen) { 842 p += sprintf(p,"%s: sc_dmalen=0x%08lx\n",sc->sc_dev.dv_xname,*esc->sc_dmalen); 843 } else { 844 p += sprintf(p,"%s: sc_dmalen=NULL\n",sc->sc_dev.dv_xname); 845 } 846 p += sprintf(p,"%s: sc_dmasize=0x%08x\n",sc->sc_dev.dv_xname,esc->sc_dmasize); 847 848 p += sprintf(p,"%s: sc_begin = 0x%08x, sc_begin_size = 0x%08x\n", 849 sc->sc_dev.dv_xname, esc->sc_begin, esc->sc_begin_size); 850 p += sprintf(p,"%s: sc_main = 0x%08x, sc_main_size = 0x%08x\n", 851 sc->sc_dev.dv_xname, esc->sc_main, esc->sc_main_size); 852 { 853 int i; 854 bus_dmamap_t map = esc->sc_main_dmamap; 855 p += sprintf(p,"%s: sc_main_dmamap. mapsize = 0x%08x, nsegs = %d\n", 856 sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs); 857 for(i=0;i<map->dm_nsegs;i++) { 858 p += sprintf(p,"%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n", 859 sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len); 860 } 861 } 862 p += sprintf(p,"%s: sc_tail = 0x%08x, sc_tail_size = 0x%08x\n", 863 sc->sc_dev.dv_xname, esc->sc_tail, esc->sc_tail_size); 864 { 865 int i; 866 bus_dmamap_t map = esc->sc_tail_dmamap; 867 p += sprintf(p,"%s: sc_tail_dmamap. mapsize = 0x%08x, nsegs = %d\n", 868 sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs); 869 for(i=0;i<map->dm_nsegs;i++) { 870 p += sprintf(p,"%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n", 871 sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len); 872 } 873 } 874 } 875 876 void 877 esp_dma_print(sc) 878 struct ncr53c9x_softc *sc; 879 { 880 esp_dma_store(sc); 881 printf("%s",esp_dma_dump); 882 } 883 #endif 884 885 void 886 esp_dma_go(sc) 887 struct ncr53c9x_softc *sc; 888 { 889 struct esp_softc *esc = (struct esp_softc *)sc; 890 891 DPRINTF(("%s: esp_dma_go(datain = %d)\n", 892 sc->sc_dev.dv_xname, esc->sc_datain)); 893 894 #ifdef ESP_DEBUG 895 if (esp_debug) esp_dma_print(sc); 896 else esp_dma_store(sc); 897 #endif 898 899 #ifdef ESP_DEBUG 900 { 901 int n = NCR_READ_REG(sc, NCR_FFLAG); 902 DPRINTF(("%s: fifo size = %d, seq = 0x%x\n", 903 sc->sc_dev.dv_xname, 904 n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 905 } 906 #endif 907 908 /* zero length dma transfers are boring */ 909 if (esc->sc_dmasize == 0) { 910 return; 911 } 912 913 #if defined(DIAGNOSTIC) 914 if ((esc->sc_begin_size == 0) && 915 (esc->sc_main_dmamap->dm_mapsize == 0) && 916 (esc->sc_tail_dmamap->dm_mapsize == 0)) { 917 esp_dma_print(sc); 918 panic("%s: No DMA requested!",sc->sc_dev.dv_xname); 919 } 920 #endif 921 922 /* Stuff the fifo with the begin buffer */ 923 if (esc->sc_datain) { 924 int i; 925 DPRINTF(("%s: FIFO read of %d bytes:", 926 sc->sc_dev.dv_xname,esc->sc_begin_size)); 927 for(i=0;i<esc->sc_begin_size;i++) { 928 esc->sc_begin[i]=NCR_READ_REG(sc, NCR_FIFO); 929 DPRINTF((" %02x",esc->sc_begin[i]&0xff)); 930 } 931 DPRINTF(("\n")); 932 } else { 933 int i; 934 DPRINTF(("%s: FIFO write of %d bytes:", 935 sc->sc_dev.dv_xname,esc->sc_begin_size)); 936 for(i=0;i<esc->sc_begin_size;i++) { 937 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_begin[i]); 938 DPRINTF((" %02x",esc->sc_begin[i]&0xff)); 939 } 940 DPRINTF(("\n")); 941 } 942 943 /* if we are a dma write cycle, copy the end slop */ 944 if (esc->sc_datain == 0) { 945 memcpy(esc->sc_tail, 946 (*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size), 947 (esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size))); 948 } 949 950 if (esc->sc_main_dmamap->dm_mapsize) { 951 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 952 0, esc->sc_main_dmamap->dm_mapsize, 953 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 954 } 955 956 if (esc->sc_tail_dmamap->dm_mapsize) { 957 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 958 0, esc->sc_tail_dmamap->dm_mapsize, 959 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 960 } 961 962 nextdma_start(&esc->sc_scsi_dma, 963 (esc->sc_datain ? DMACSR_SETREAD : DMACSR_SETWRITE)); 964 965 if (esc->sc_datain) { 966 NCR_WRITE_REG(sc, ESP_DCTL, 967 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 968 } else { 969 NCR_WRITE_REG(sc, ESP_DCTL, 970 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 971 } 972 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 973 } 974 975 void 976 esp_dma_stop(sc) 977 struct ncr53c9x_softc *sc; 978 { 979 panic("Not yet implemented"); 980 } 981 982 int 983 esp_dma_isactive(sc) 984 struct ncr53c9x_softc *sc; 985 { 986 struct esp_softc *esc = (struct esp_softc *)sc; 987 int r = !nextdma_finished(&esc->sc_scsi_dma); 988 DPRINTF(("esp_dma_isactive = %d\n",r)); 989 return(r); 990 } 991 992 /****************************************************************/ 993 994 /* Internal dma callback routines */ 995 bus_dmamap_t 996 esp_dmacb_continue(arg) 997 void *arg; 998 { 999 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1000 struct esp_softc *esc = (struct esp_softc *)sc; 1001 1002 DPRINTF(("%s: dma continue\n",sc->sc_dev.dv_xname)); 1003 1004 #ifdef DIAGNOSTIC 1005 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 1006 panic("%s: map not loaded in dma continue callback, datain = %d", 1007 sc->sc_dev.dv_xname,esc->sc_datain); 1008 } 1009 #endif 1010 1011 if ((!(esc->sc_loaded & ESP_LOADED_MAIN)) && 1012 (esc->sc_main_dmamap->dm_mapsize)) { 1013 DPRINTF(("%s: Loading main map\n",sc->sc_dev.dv_xname)); 1014 #if 0 1015 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 1016 0, esc->sc_main_dmamap->dm_mapsize, 1017 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1018 #endif 1019 esc->sc_loaded |= ESP_LOADED_MAIN; 1020 return(esc->sc_main_dmamap); 1021 } 1022 1023 if ((!(esc->sc_loaded & ESP_LOADED_TAIL)) && 1024 (esc->sc_tail_dmamap->dm_mapsize)) { 1025 DPRINTF(("%s: Loading tail map\n",sc->sc_dev.dv_xname)); 1026 #if 0 1027 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 1028 0, esc->sc_tail_dmamap->dm_mapsize, 1029 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1030 #endif 1031 esc->sc_loaded |= ESP_LOADED_TAIL; 1032 return(esc->sc_tail_dmamap); 1033 } 1034 1035 DPRINTF(("%s: not loading map\n",sc->sc_dev.dv_xname)); 1036 return(0); 1037 } 1038 1039 1040 void 1041 esp_dmacb_completed(map, arg) 1042 bus_dmamap_t map; 1043 void *arg; 1044 { 1045 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1046 struct esp_softc *esc = (struct esp_softc *)sc; 1047 1048 DPRINTF(("%s: dma completed\n",sc->sc_dev.dv_xname)); 1049 1050 #ifdef DIAGNOSTIC 1051 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 1052 panic("%s: invalid dma direction in completed callback, datain = %d", 1053 sc->sc_dev.dv_xname,esc->sc_datain); 1054 } 1055 #endif 1056 1057 if (map == esc->sc_main_dmamap) { 1058 #ifdef DIAGNOSTIC 1059 if ((esc->sc_loaded & ESP_UNLOADED_MAIN) || 1060 !(esc->sc_loaded & ESP_LOADED_MAIN)) { 1061 panic("%s: unexpected completed call for main map\n",sc->sc_dev.dv_xname); 1062 } 1063 #endif 1064 esc->sc_loaded |= ESP_UNLOADED_MAIN; 1065 } else if (map == esc->sc_tail_dmamap) { 1066 #ifdef DIAGNOSTIC 1067 if ((esc->sc_loaded & ESP_UNLOADED_TAIL) || 1068 !(esc->sc_loaded & ESP_LOADED_TAIL)) { 1069 panic("%s: unexpected completed call for tail map\n",sc->sc_dev.dv_xname); 1070 } 1071 #endif 1072 esc->sc_loaded |= ESP_UNLOADED_TAIL; 1073 } 1074 #ifdef DIAGNOSTIC 1075 else { 1076 panic("%s: unexpected completed map", sc->sc_dev.dv_xname); 1077 } 1078 #endif 1079 1080 #ifdef ESP_DEBUG 1081 if (esp_debug) { 1082 if (map == esc->sc_main_dmamap) { 1083 printf("%s: completed main map\n",sc->sc_dev.dv_xname); 1084 } else if (map == esc->sc_tail_dmamap) { 1085 printf("%s: completed tail map\n",sc->sc_dev.dv_xname); 1086 } 1087 } 1088 #endif 1089 1090 #if 0 1091 if ((map == esc->sc_tail_dmamap) || 1092 ((esc->sc_tail_size == 0) && (map == esc->sc_main_dmamap))) { 1093 1094 /* Clear the DMAMOD bit in the DCTL register to give control 1095 * back to the scsi chip. 1096 */ 1097 if (esc->sc_datain) { 1098 NCR_WRITE_REG(sc, ESP_DCTL, 1099 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 1100 } else { 1101 NCR_WRITE_REG(sc, ESP_DCTL, 1102 ESPDCTL_20MHZ | ESPDCTL_INTENB); 1103 } 1104 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 1105 } 1106 #endif 1107 1108 1109 #if 0 1110 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, map, 1111 0, map->dm_mapsize, 1112 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1113 #endif 1114 1115 } 1116 1117 void 1118 esp_dmacb_shutdown(arg) 1119 void *arg; 1120 { 1121 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1122 struct esp_softc *esc = (struct esp_softc *)sc; 1123 1124 DPRINTF(("%s: dma shutdown\n",sc->sc_dev.dv_xname)); 1125 1126 #if 0 1127 { 1128 /* Clear the DMAMOD bit in the DCTL register to give control 1129 * back to the scsi chip. 1130 */ 1131 if (esc->sc_datain) { 1132 NCR_WRITE_REG(sc, ESP_DCTL, 1133 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 1134 } else { 1135 NCR_WRITE_REG(sc, ESP_DCTL, 1136 ESPDCTL_20MHZ | ESPDCTL_INTENB); 1137 } 1138 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 1139 } 1140 #endif 1141 1142 DPRINTF(("%s: esp_dma_nest == %d\n",sc->sc_dev.dv_xname,esp_dma_nest)); 1143 1144 /* Stuff the end slop into fifo */ 1145 1146 #ifdef ESP_DEBUG 1147 if (esp_debug) { 1148 1149 int n = NCR_READ_REG(sc, NCR_FFLAG); 1150 DPRINTF(("%s: fifo size = %d, seq = 0x%x\n", 1151 sc->sc_dev.dv_xname,n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 1152 } 1153 #endif 1154 1155 if (esc->sc_main_dmamap->dm_mapsize) { 1156 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 1157 0, esc->sc_main_dmamap->dm_mapsize, 1158 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1159 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 1160 } 1161 1162 if (esc->sc_tail_dmamap->dm_mapsize) { 1163 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 1164 0, esc->sc_tail_dmamap->dm_mapsize, 1165 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1166 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 1167 } 1168 1169 /* copy the tail dma buffer data for read transfers */ 1170 if (esc->sc_datain == 1) { 1171 memcpy((*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size), 1172 esc->sc_tail, 1173 (esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size))); 1174 } 1175 1176 #ifdef ESP_DEBUG 1177 if (esp_debug) { 1178 printf("%s: dma_shutdown: addr=0x%08lx,len=0x%08lx,size=0x%08lx\n", 1179 sc->sc_dev.dv_xname, 1180 *esc->sc_dmaaddr, *esc->sc_dmalen, esc->sc_dmasize); 1181 if (esp_debug > 10) { 1182 esp_hex_dump(*(esc->sc_dmaaddr),esc->sc_dmasize); 1183 printf("%s: tail=0x%08lx,tailbuf=0x%08lx,tail_size=0x%08lx\n", 1184 sc->sc_dev.dv_xname, 1185 esc->sc_tail, &(esc->sc_tailbuf[0]), esc->sc_tail_size); 1186 esp_hex_dump(&(esc->sc_tailbuf[0]),sizeof(esc->sc_tailbuf)); 1187 } 1188 } 1189 #endif 1190 1191 *(esc->sc_dmaaddr) += esc->sc_dmasize; 1192 *(esc->sc_dmalen) -= esc->sc_dmasize; 1193 1194 esc->sc_main = 0; 1195 esc->sc_main_size = 0; 1196 esc->sc_tail = 0; 1197 esc->sc_tail_size = 0; 1198 1199 esc->sc_datain = -1; 1200 esc->sc_dmaaddr = 0; 1201 esc->sc_dmalen = 0; 1202 esc->sc_dmasize = 0; 1203 1204 esc->sc_loaded = 0; 1205 1206 esc->sc_begin = 0; 1207 esc->sc_begin_size = 0; 1208 1209 #ifdef ESP_DEBUG 1210 if (esp_debug) { 1211 printf(" *intrstat = 0x%b\n", 1212 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS); 1213 printf(" *intrmask = 0x%b\n", 1214 (*(volatile u_long *)IIOV(NEXT_P_INTRMASK)),NEXT_INTR_BITS); 1215 } 1216 #endif 1217 } 1218
Indexes created Wed Sep 24 05:09:52 GMT 2025