esp.c revision 1.26
1 /* $NetBSD: esp.c,v 1.26 2000/06/04 19:14:53 cgd Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Grabbed from the sparc port at revision 1.73 for the NeXT. 81 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 82 */ 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/device.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 #include <sys/user.h> 94 #include <sys/queue.h> 95 96 #include <dev/scsipi/scsi_all.h> 97 #include <dev/scsipi/scsipi_all.h> 98 #include <dev/scsipi/scsiconf.h> 99 #include <dev/scsipi/scsi_message.h> 100 101 #include <machine/bus.h> 102 #include <machine/autoconf.h> 103 #include <machine/cpu.h> 104 105 #include <dev/ic/ncr53c9xreg.h> 106 #include <dev/ic/ncr53c9xvar.h> 107 108 #include <next68k/next68k/isr.h> 109 110 #include <next68k/dev/nextdmareg.h> 111 #include <next68k/dev/nextdmavar.h> 112 113 #include "espreg.h" 114 #include "espvar.h" 115 116 #ifdef DEBUG 117 #define ESP_DEBUG 118 #endif 119 120 #ifdef ESP_DEBUG 121 int esp_debug = 0; 122 #define DPRINTF(x) if (esp_debug) printf x; 123 #else 124 #define DPRINTF(x) 125 #endif 126 127 128 void espattach_intio __P((struct device *, struct device *, void *)); 129 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 130 131 /* DMA callbacks */ 132 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 133 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 134 void esp_dmacb_shutdown __P((void *arg)); 135 136 #ifdef ESP_DEBUG 137 char esp_dma_dump[5*1024] = ""; 138 struct ncr53c9x_softc *esp_debug_sc = 0; 139 void esp_dma_store __P((struct ncr53c9x_softc *sc)); 140 void esp_dma_print __P((struct ncr53c9x_softc *sc)); 141 int esp_dma_nest = 0; 142 #endif 143 144 145 /* Linkup to the rest of the kernel */ 146 struct cfattach esp_ca = { 147 sizeof(struct esp_softc), espmatch_intio, espattach_intio 148 }; 149 150 struct scsipi_device esp_dev = { 151 NULL, /* Use default error handler */ 152 NULL, /* have a queue, served by this */ 153 NULL, /* have no async handler */ 154 NULL, /* Use default 'done' routine */ 155 }; 156 157 /* 158 * Functions and the switch for the MI code. 159 */ 160 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 161 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 162 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 163 void esp_dma_reset __P((struct ncr53c9x_softc *)); 164 int esp_dma_intr __P((struct ncr53c9x_softc *)); 165 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 166 size_t *, int, size_t *)); 167 void esp_dma_go __P((struct ncr53c9x_softc *)); 168 void esp_dma_stop __P((struct ncr53c9x_softc *)); 169 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 170 171 struct ncr53c9x_glue esp_glue = { 172 esp_read_reg, 173 esp_write_reg, 174 esp_dma_isintr, 175 esp_dma_reset, 176 esp_dma_intr, 177 esp_dma_setup, 178 esp_dma_go, 179 esp_dma_stop, 180 esp_dma_isactive, 181 NULL, /* gl_clear_latched_intr */ 182 }; 183 184 #ifdef ESP_DEBUG 185 #define XCHR(x) "0123456789abcdef"[(x) & 0xf] 186 static void 187 esp_hex_dump(unsigned char *pkt, size_t len) 188 { 189 size_t i, j; 190 191 printf("00000000 "); 192 for(i=0; i<len; i++) { 193 printf("%c%c ", XCHR(pkt[i]>>4), XCHR(pkt[i])); 194 if ((i+1) % 16 == 8) { 195 printf(" "); 196 } 197 if ((i+1) % 16 == 0) { 198 printf(" %c", '|'); 199 for(j=0; j<16; j++) { 200 printf("%c", pkt[i-15+j]>=32 && pkt[i-15+j]<127?pkt[i-15+j]:'.'); 201 } 202 printf("%c\n%c%c%c%c%c%c%c%c ", '|', 203 XCHR((i+1)>>28),XCHR((i+1)>>24),XCHR((i+1)>>20),XCHR((i+1)>>16), 204 XCHR((i+1)>>12), XCHR((i+1)>>8), XCHR((i+1)>>4), XCHR(i+1)); 205 } 206 } 207 printf("\n"); 208 } 209 #endif 210 211 int 212 espmatch_intio(parent, cf, aux) 213 struct device *parent; 214 struct cfdata *cf; 215 void *aux; 216 { 217 /* should probably probe here */ 218 /* Should also probably set up data from config */ 219 220 return(1); 221 } 222 223 void 224 espattach_intio(parent, self, aux) 225 struct device *parent, *self; 226 void *aux; 227 { 228 struct esp_softc *esc = (void *)self; 229 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 230 231 #ifdef ESP_DEBUG 232 esp_debug_sc = sc; 233 #endif 234 235 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 236 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 237 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 238 panic("\n%s: can't map ncr53c90 registers", 239 sc->sc_dev.dv_xname); 240 } 241 242 sc->sc_id = 7; 243 sc->sc_freq = 20; /* Mhz */ 244 245 /* 246 * Set up glue for MI code early; we use some of it here. 247 */ 248 sc->sc_glue = &esp_glue; 249 250 /* 251 * XXX More of this should be in ncr53c9x_attach(), but 252 * XXX should we really poke around the chip that much in 253 * XXX the MI code? Think about this more... 254 */ 255 256 /* 257 * It is necessary to try to load the 2nd config register here, 258 * to find out what rev the esp chip is, else the ncr53c9x_reset 259 * will not set up the defaults correctly. 260 */ 261 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 262 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 263 sc->sc_cfg3 = NCRCFG3_CDB; 264 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 265 266 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 267 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 268 sc->sc_rev = NCR_VARIANT_ESP100; 269 } else { 270 sc->sc_cfg2 = NCRCFG2_SCSI2; 271 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 272 sc->sc_cfg3 = 0; 273 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 274 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 275 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 276 if (NCR_READ_REG(sc, NCR_CFG3) != 277 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 278 sc->sc_rev = NCR_VARIANT_ESP100A; 279 } else { 280 /* NCRCFG2_FE enables > 64K transfers */ 281 sc->sc_cfg2 |= NCRCFG2_FE; 282 sc->sc_cfg3 = 0; 283 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 284 sc->sc_rev = NCR_VARIANT_ESP200; 285 } 286 } 287 288 /* 289 * XXX minsync and maxxfer _should_ be set up in MI code, 290 * XXX but it appears to have some dependency on what sort 291 * XXX of DMA we're hooked up to, etc. 292 */ 293 294 /* 295 * This is the value used to start sync negotiations 296 * Note that the NCR register "SYNCTP" is programmed 297 * in "clocks per byte", and has a minimum value of 4. 298 * The SCSI period used in negotiation is one-fourth 299 * of the time (in nanoseconds) needed to transfer one byte. 300 * Since the chip's clock is given in MHz, we have the following 301 * formula: 4 * period = (1000 / freq) * 4 302 */ 303 sc->sc_minsync = 1000 / sc->sc_freq; 304 305 /* 306 * Alas, we must now modify the value a bit, because it's 307 * only valid when can switch on FASTCLK and FASTSCSI bits 308 * in config register 3... 309 */ 310 switch (sc->sc_rev) { 311 case NCR_VARIANT_ESP100: 312 sc->sc_maxxfer = 64 * 1024; 313 sc->sc_minsync = 0; /* No synch on old chip? */ 314 break; 315 316 case NCR_VARIANT_ESP100A: 317 sc->sc_maxxfer = 64 * 1024; 318 /* Min clocks/byte is 5 */ 319 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 320 break; 321 322 case NCR_VARIANT_ESP200: 323 sc->sc_maxxfer = 16 * 1024 * 1024; 324 /* XXX - do actually set FAST* bits */ 325 break; 326 } 327 328 /* @@@ Some ESP_DCTL bits probably need setting */ 329 NCR_WRITE_REG(sc, ESP_DCTL, 330 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 331 DELAY(10); 332 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 333 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 334 DELAY(10); 335 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 336 337 /* Set up SCSI DMA */ 338 { 339 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 340 341 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 342 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 343 panic("\n%s: can't map scsi DMA registers", 344 sc->sc_dev.dv_xname); 345 } 346 347 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 348 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 349 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 350 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 351 esc->sc_scsi_dma.nd_cb_arg = sc; 352 nextdma_config(&esc->sc_scsi_dma); 353 nextdma_init(&esc->sc_scsi_dma); 354 355 #if 0 356 /* Turn on target selection using the `dma' method */ 357 ncr53c9x_dmaselect = 1; 358 #else 359 ncr53c9x_dmaselect = 0; 360 #endif 361 362 esc->sc_datain = -1; 363 esc->sc_dmaaddr = 0; 364 esc->sc_dmalen = 0; 365 esc->sc_dmasize = 0; 366 367 esc->sc_loaded = 0; 368 369 esc->sc_begin = 0; 370 esc->sc_begin_size = 0; 371 372 { 373 int error; 374 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 375 sc->sc_maxxfer, sc->sc_maxxfer/NBPG, sc->sc_maxxfer, 376 0, BUS_DMA_ALLOCNOW, &esc->sc_main_dmamap)) != 0) { 377 panic("%s: can't create main i/o DMA map, error = %d", 378 sc->sc_dev.dv_xname,error); 379 } 380 } 381 esc->sc_main = 0; 382 esc->sc_main_size = 0; 383 384 { 385 int error; 386 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 387 ESP_DMA_TAILBUFSIZE, 388 1, ESP_DMA_TAILBUFSIZE, 389 0, BUS_DMA_ALLOCNOW, &esc->sc_tail_dmamap)) != 0) { 390 panic("%s: can't create tail i/o DMA map, error = %d", 391 sc->sc_dev.dv_xname,error); 392 } 393 } 394 esc->sc_tail = 0; 395 esc->sc_tail_size = 0; 396 397 } 398 399 /* Establish interrupt channel */ 400 isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc, 401 NEXT_I_IPL(NEXT_I_SCSI), 0); 402 INTR_ENABLE(NEXT_I_SCSI); 403 404 /* register interrupt stats */ 405 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 406 sc->sc_dev.dv_xname, "intr"); 407 408 /* Do the common parts of attachment. */ 409 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 410 sc->sc_adapter.scsipi_minphys = minphys; 411 ncr53c9x_attach(sc, &esp_dev); 412 } 413 414 /* 415 * Glue functions. 416 */ 417 418 u_char 419 esp_read_reg(sc, reg) 420 struct ncr53c9x_softc *sc; 421 int reg; 422 { 423 struct esp_softc *esc = (struct esp_softc *)sc; 424 425 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 426 } 427 428 void 429 esp_write_reg(sc, reg, val) 430 struct ncr53c9x_softc *sc; 431 int reg; 432 u_char val; 433 { 434 struct esp_softc *esc = (struct esp_softc *)sc; 435 436 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 437 } 438 439 int 440 esp_dma_isintr(sc) 441 struct ncr53c9x_softc *sc; 442 { 443 struct esp_softc *esc = (struct esp_softc *)sc; 444 445 int r = (INTR_OCCURRED(NEXT_I_SCSI)); 446 447 if (r) { 448 449 { 450 int flushcount; 451 int s; 452 s = spldma(); 453 454 flushcount = 0; 455 456 #ifdef ESP_DEBUG 457 esp_dma_nest++; 458 #endif 459 460 DPRINTF(("esp_dma_isintr = 0x%b\n", 461 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS)); 462 463 while (esp_dma_isactive(sc)) { 464 flushcount++; 465 466 #ifdef DIAGNOSTIC 467 r = (INTR_OCCURRED(NEXT_I_SCSI)); 468 if (!r) panic("esp intr enabled but dma failed to flush"); 469 #endif 470 #ifdef DIAGNOSTIC 471 #if 0 472 if ((esc->sc_loaded & (ESP_LOADED_TAIL/* |ESP_UNLOADED_MAIN */)) 473 != (ESP_LOADED_TAIL /* |ESP_UNLOADED_MAIN */)) { 474 if (esc->sc_datain) { 475 NCR_WRITE_REG(sc, ESP_DCTL, 476 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 477 } else { 478 NCR_WRITE_REG(sc, ESP_DCTL, 479 ESPDCTL_20MHZ | ESPDCTL_INTENB); 480 } 481 next_dma_print(&esc->sc_scsi_dma); 482 esp_dma_print(sc); 483 printf("%s: unexpected flush: tc=0x%06x\n", 484 sc->sc_dev.dv_xname, 485 (((sc->sc_cfg2 & NCRCFG2_FE) 486 ? NCR_READ_REG(sc, NCR_TCH) : 0)<<16)| 487 (NCR_READ_REG(sc, NCR_TCM)<<8)| 488 NCR_READ_REG(sc, NCR_TCL)); 489 ncr53c9x_readregs(sc); 490 printf("%s: readregs[intr=%02x,stat=%02x,step=%02x]\n", 491 sc->sc_dev.dv_xname, 492 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep); 493 panic("%s: flushing flushing non-tail dma\n", 494 sc->sc_dev.dv_xname); 495 } 496 #endif 497 #endif 498 DPRINTF(("%s: flushing dma, count = %d\n", sc->sc_dev.dv_xname,flushcount)); 499 if (esc->sc_datain) { 500 NCR_WRITE_REG(sc, ESP_DCTL, 501 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD | ESPDCTL_FLUSH); 502 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 503 NCR_WRITE_REG(sc, ESP_DCTL, 504 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 505 } else { 506 NCR_WRITE_REG(sc, ESP_DCTL, 507 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_FLUSH); 508 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 509 NCR_WRITE_REG(sc, ESP_DCTL, 510 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 511 } 512 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 513 514 { 515 int nr; 516 nr = nextdma_intr(&esc->sc_scsi_dma); 517 if (nr) { 518 DPRINTF(("nextma_intr = %d\n",nr)); 519 #ifdef DIAGNOSTIC 520 #if 0 521 if (flushcount > 16) { 522 printf("%s: unexpected flushcount %d\n",sc->sc_dev.dv_xname,flushcount); 523 } 524 #endif 525 #endif 526 #ifdef DIAGNOSTIC 527 #if 0 528 if (esp_dma_isactive(sc)) { 529 esp_dma_print(sc); 530 printf("%s: dma still active after a flush with count %d\n", 531 sc->sc_dev.dv_xname,flushcount); 532 533 } 534 #endif 535 #endif 536 flushcount = 0; 537 } 538 } 539 } 540 541 #ifdef ESP_DEBUG 542 esp_dma_nest--; 543 #endif 544 545 splx(s); 546 } 547 548 #ifdef DIAGNOSTIC 549 r = (INTR_OCCURRED(NEXT_I_SCSI)); 550 if (!r) panic("esp intr not enabled after dma flush"); 551 #endif 552 553 /* Clear the DMAMOD bit in the DCTL register, since if this 554 * routine returns true, then the ncr53c9x_intr handler will 555 * be called and needs access to the scsi registers. 556 */ 557 if (esc->sc_datain) { 558 NCR_WRITE_REG(sc, ESP_DCTL, 559 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 560 } else { 561 NCR_WRITE_REG(sc, ESP_DCTL, 562 ESPDCTL_20MHZ | ESPDCTL_INTENB); 563 } 564 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 565 566 } 567 568 return (r); 569 } 570 571 void 572 esp_dma_reset(sc) 573 struct ncr53c9x_softc *sc; 574 { 575 struct esp_softc *esc = (struct esp_softc *)sc; 576 577 DPRINTF(("esp dma reset\n")); 578 579 #ifdef ESP_DEBUG 580 if (esp_debug) { 581 printf(" *intrstat = 0x%b\n", 582 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS); 583 printf(" *intrmask = 0x%b\n", 584 (*(volatile u_long *)IIOV(NEXT_P_INTRMASK)),NEXT_INTR_BITS); 585 } 586 #endif 587 588 /* Clear the DMAMOD bit in the DCTL register: */ 589 NCR_WRITE_REG(sc, ESP_DCTL, 590 ESPDCTL_20MHZ | ESPDCTL_INTENB); 591 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 592 593 nextdma_reset(&esc->sc_scsi_dma); 594 595 esc->sc_datain = -1; 596 esc->sc_dmaaddr = 0; 597 esc->sc_dmalen = 0; 598 esc->sc_dmasize = 0; 599 600 esc->sc_loaded = 0; 601 602 esc->sc_begin = 0; 603 esc->sc_begin_size = 0; 604 605 if (esc->sc_main_dmamap->dm_mapsize) { 606 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 607 } 608 esc->sc_main = 0; 609 esc->sc_main_size = 0; 610 611 if (esc->sc_tail_dmamap->dm_mapsize) { 612 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 613 } 614 esc->sc_tail = 0; 615 esc->sc_tail_size = 0; 616 } 617 618 int 619 esp_dma_intr(sc) 620 struct ncr53c9x_softc *sc; 621 { 622 #ifdef DIAGNOSTIC 623 panic("%s: esp_dma_intr shouldn't be invoked.\n", sc->sc_dev.dv_xname); 624 #endif 625 626 return -1; 627 } 628 629 /* it appears that: 630 * addr and len arguments to this need to be kept up to date 631 * with the status of the transfter. 632 * the dmasize of this is the actual length of the transfer 633 * request, which is guaranteed to be less than maxxfer. 634 * (len may be > maxxfer) 635 */ 636 637 int 638 esp_dma_setup(sc, addr, len, datain, dmasize) 639 struct ncr53c9x_softc *sc; 640 caddr_t *addr; 641 size_t *len; 642 int datain; 643 size_t *dmasize; 644 { 645 struct esp_softc *esc = (struct esp_softc *)sc; 646 647 #ifdef DIAGNOSTIC 648 #ifdef ESP_DEBUG 649 /* if this is a read DMA, pre-fill the buffer with 0xdeadbeef 650 * to identify bogus reads 651 */ 652 if (datain) { 653 int *v = (int *)(*addr); 654 int i; 655 for(i=0;i<((*len)/4);i++) v[i] = 0xdeadbeef; 656 v = (int *)(&(esc->sc_tailbuf[0])); 657 for(i=0;i<((sizeof(esc->sc_tailbuf)/4));i++) v[i] = 0xdeaffeed; 658 } else { 659 int *v; 660 int i; 661 v = (int *)(&(esc->sc_tailbuf[0])); 662 for(i=0;i<((sizeof(esc->sc_tailbuf)/4));i++) v[i] = 0xfeeb1eed; 663 } 664 #endif 665 #endif 666 667 DPRINTF(("esp_dma_setup(0x%08lx,0x%08lx,0x%08lx)\n",*addr,*len,*dmasize)); 668 669 #if 0 670 #ifdef DIAGNOSTIC /* @@@ this is ok sometimes. verify that we handle it ok 671 * and then remove this check 672 */ 673 if (*len != *dmasize) { 674 panic("esp dmalen 0x%lx != size 0x%lx",*len,*dmasize); 675 } 676 #endif 677 #endif 678 679 #ifdef DIAGNOSTIC 680 if ((esc->sc_datain != -1) || 681 (esc->sc_main_dmamap->dm_mapsize != 0) || 682 (esc->sc_tail_dmamap->dm_mapsize != 0) || 683 (esc->sc_dmasize != 0)) { 684 panic("%s: map already loaded in esp_dma_setup\n" 685 "\tdatain = %d\n\tmain_mapsize=%d\n\tail_mapsize=%d\n\tdmasize = %d", 686 sc->sc_dev.dv_xname, esc->sc_datain, 687 esc->sc_main_dmamap->dm_mapsize, 688 esc->sc_tail_dmamap->dm_mapsize, 689 esc->sc_dmasize); 690 } 691 #endif 692 693 /* we are sometimes asked to dma zero bytes, that's easy */ 694 if (*dmasize <= 0) { 695 return(0); 696 } 697 698 /* Save these in case we have to abort DMA */ 699 esc->sc_datain = datain; 700 esc->sc_dmaaddr = addr; 701 esc->sc_dmalen = len; 702 esc->sc_dmasize = *dmasize; 703 704 esc->sc_loaded = 0; 705 706 #define DMA_SCSI_ALIGNMENT 16 707 #define DMA_SCSI_ALIGN(type, addr) \ 708 ((type)(((unsigned)(addr)+DMA_SCSI_ALIGNMENT-1) \ 709 &~(DMA_SCSI_ALIGNMENT-1))) 710 #define DMA_SCSI_ALIGNED(addr) \ 711 (((unsigned)(addr)&(DMA_SCSI_ALIGNMENT-1))==0) 712 713 { 714 size_t slop_bgn_size; /* # bytes to be fifo'd at beginning */ 715 size_t slop_end_size; /* # bytes to be transferred in tail buffer */ 716 717 { 718 u_long bgn = (u_long)(*esc->sc_dmaaddr); 719 u_long end = (u_long)(*esc->sc_dmaaddr+esc->sc_dmasize); 720 721 slop_bgn_size = DMA_SCSI_ALIGNMENT-(bgn % DMA_SCSI_ALIGNMENT); 722 if (slop_bgn_size == DMA_SCSI_ALIGNMENT) slop_bgn_size = 0; 723 slop_end_size = (end % DMA_ENDALIGNMENT); 724 } 725 726 /* Force a minimum slop end size. This ensures that write 727 * requests will overrun, as required to get completion interrupts. 728 * In addition, since the tail buffer is guaranteed to be mapped 729 * in a single dma segment, the overrun won't accidentally 730 * end up in its own segment. 731 */ 732 if (!esc->sc_datain) { 733 #if 0 734 slop_end_size += ESP_DMA_MAXTAIL; 735 #else 736 slop_end_size += 0x10; 737 #endif 738 } 739 740 /* Check to make sure we haven't counted extra slop 741 * as would happen for a very short dma buffer, also 742 * for short buffers, just stuff the entire thing in the tail 743 */ 744 if ((slop_bgn_size+slop_end_size >= esc->sc_dmasize) 745 #if 0 746 || (esc->sc_dmasize <= ESP_DMA_MAXTAIL) 747 #endif 748 ) 749 { 750 slop_bgn_size = 0; 751 slop_end_size = esc->sc_dmasize; 752 } 753 754 /* initialize the fifo buffer */ 755 if (slop_bgn_size) { 756 esc->sc_begin = *esc->sc_dmaaddr; 757 esc->sc_begin_size = slop_bgn_size; 758 } else { 759 esc->sc_begin = 0; 760 esc->sc_begin_size = 0; 761 } 762 763 /* Load the normal DMA map */ 764 { 765 esc->sc_main = *esc->sc_dmaaddr+slop_bgn_size; 766 esc->sc_main_size = (esc->sc_dmasize)-(slop_end_size+slop_bgn_size); 767 768 if (esc->sc_main_size) { 769 int error; 770 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 771 esc->sc_main_dmamap, 772 esc->sc_main, esc->sc_main_size, 773 NULL, BUS_DMA_NOWAIT); 774 if (error) { 775 panic("%s: can't load main dma map. error = %d, addr=0x%08x, size=0x%08x", 776 sc->sc_dev.dv_xname, error,esc->sc_main,esc->sc_main_size); 777 } 778 #if 0 779 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 780 0, esc->sc_main_dmamap->dm_mapsize, 781 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 782 #endif 783 } else { 784 esc->sc_main = 0; 785 } 786 } 787 788 /* Load the tail DMA map */ 789 if (slop_end_size) { 790 esc->sc_tail = DMA_ENDALIGN(caddr_t,esc->sc_tailbuf+slop_end_size)-slop_end_size; 791 /* If the beginning of the tail is not correctly aligned, 792 * we have no choice but to align the start, which might then unalign the end. 793 */ 794 esc->sc_tail = DMA_SCSI_ALIGN(caddr_t,esc->sc_tail); 795 /* So therefore, we change the tail size to be end aligned again. */ 796 esc->sc_tail_size = DMA_ENDALIGN(caddr_t,esc->sc_tail+slop_end_size)-esc->sc_tail; 797 798 /* @@@ next dma overrun lossage */ 799 if (!esc->sc_datain) { 800 esc->sc_tail_size += ESP_DMA_OVERRUN; 801 } 802 803 { 804 int error; 805 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 806 esc->sc_tail_dmamap, 807 esc->sc_tail, esc->sc_tail_size, 808 NULL, BUS_DMA_NOWAIT); 809 if (error) { 810 panic("%s: can't load tail dma map. error = %d, addr=0x%08x, size=0x%08x", 811 sc->sc_dev.dv_xname, error,esc->sc_tail,esc->sc_tail_size); 812 } 813 #if 0 814 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 815 0, esc->sc_tail_dmamap->dm_mapsize, 816 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 817 #endif 818 } 819 } 820 } 821 822 return (0); 823 } 824 825 #ifdef ESP_DEBUG 826 /* For debugging */ 827 void 828 esp_dma_store(sc) 829 struct ncr53c9x_softc *sc; 830 { 831 struct esp_softc *esc = (struct esp_softc *)sc; 832 char *p = &esp_dma_dump[0]; 833 834 p += sprintf(p,"%s: sc_datain=%d\n",sc->sc_dev.dv_xname,esc->sc_datain); 835 p += sprintf(p,"%s: sc_loaded=0x%08x\n",sc->sc_dev.dv_xname,esc->sc_loaded); 836 837 if (esc->sc_dmaaddr) { 838 p += sprintf(p,"%s: sc_dmaaddr=0x%08lx\n",sc->sc_dev.dv_xname,*esc->sc_dmaaddr); 839 } else { 840 p += sprintf(p,"%s: sc_dmaaddr=NULL\n",sc->sc_dev.dv_xname); 841 } 842 if (esc->sc_dmalen) { 843 p += sprintf(p,"%s: sc_dmalen=0x%08lx\n",sc->sc_dev.dv_xname,*esc->sc_dmalen); 844 } else { 845 p += sprintf(p,"%s: sc_dmalen=NULL\n",sc->sc_dev.dv_xname); 846 } 847 p += sprintf(p,"%s: sc_dmasize=0x%08x\n",sc->sc_dev.dv_xname,esc->sc_dmasize); 848 849 p += sprintf(p,"%s: sc_begin = 0x%08x, sc_begin_size = 0x%08x\n", 850 sc->sc_dev.dv_xname, esc->sc_begin, esc->sc_begin_size); 851 p += sprintf(p,"%s: sc_main = 0x%08x, sc_main_size = 0x%08x\n", 852 sc->sc_dev.dv_xname, esc->sc_main, esc->sc_main_size); 853 { 854 int i; 855 bus_dmamap_t map = esc->sc_main_dmamap; 856 p += sprintf(p,"%s: sc_main_dmamap. mapsize = 0x%08x, nsegs = %d\n", 857 sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs); 858 for(i=0;i<map->dm_nsegs;i++) { 859 p += sprintf(p,"%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n", 860 sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len); 861 } 862 } 863 p += sprintf(p,"%s: sc_tail = 0x%08x, sc_tail_size = 0x%08x\n", 864 sc->sc_dev.dv_xname, esc->sc_tail, esc->sc_tail_size); 865 { 866 int i; 867 bus_dmamap_t map = esc->sc_tail_dmamap; 868 p += sprintf(p,"%s: sc_tail_dmamap. mapsize = 0x%08x, nsegs = %d\n", 869 sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs); 870 for(i=0;i<map->dm_nsegs;i++) { 871 p += sprintf(p,"%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n", 872 sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len); 873 } 874 } 875 } 876 877 void 878 esp_dma_print(sc) 879 struct ncr53c9x_softc *sc; 880 { 881 esp_dma_store(sc); 882 printf("%s",esp_dma_dump); 883 } 884 #endif 885 886 void 887 esp_dma_go(sc) 888 struct ncr53c9x_softc *sc; 889 { 890 struct esp_softc *esc = (struct esp_softc *)sc; 891 892 DPRINTF(("%s: esp_dma_go(datain = %d)\n", 893 sc->sc_dev.dv_xname, esc->sc_datain)); 894 895 #ifdef ESP_DEBUG 896 if (esp_debug) esp_dma_print(sc); 897 else esp_dma_store(sc); 898 #endif 899 900 #ifdef ESP_DEBUG 901 { 902 int n = NCR_READ_REG(sc, NCR_FFLAG); 903 DPRINTF(("%s: fifo size = %d, seq = 0x%x\n", 904 sc->sc_dev.dv_xname, 905 n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 906 } 907 #endif 908 909 /* zero length dma transfers are boring */ 910 if (esc->sc_dmasize == 0) { 911 return; 912 } 913 914 #if defined(DIAGNOSTIC) 915 if ((esc->sc_begin_size == 0) && 916 (esc->sc_main_dmamap->dm_mapsize == 0) && 917 (esc->sc_tail_dmamap->dm_mapsize == 0)) { 918 esp_dma_print(sc); 919 panic("%s: No DMA requested!",sc->sc_dev.dv_xname); 920 } 921 #endif 922 923 /* Stuff the fifo with the begin buffer */ 924 if (esc->sc_datain) { 925 int i; 926 DPRINTF(("%s: FIFO read of %d bytes:", 927 sc->sc_dev.dv_xname,esc->sc_begin_size)); 928 for(i=0;i<esc->sc_begin_size;i++) { 929 esc->sc_begin[i]=NCR_READ_REG(sc, NCR_FIFO); 930 DPRINTF((" %02x",esc->sc_begin[i]&0xff)); 931 } 932 DPRINTF(("\n")); 933 } else { 934 int i; 935 DPRINTF(("%s: FIFO write of %d bytes:", 936 sc->sc_dev.dv_xname,esc->sc_begin_size)); 937 for(i=0;i<esc->sc_begin_size;i++) { 938 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_begin[i]); 939 DPRINTF((" %02x",esc->sc_begin[i]&0xff)); 940 } 941 DPRINTF(("\n")); 942 } 943 944 /* if we are a dma write cycle, copy the end slop */ 945 if (esc->sc_datain == 0) { 946 memcpy(esc->sc_tail, 947 (*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size), 948 (esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size))); 949 } 950 951 if (esc->sc_main_dmamap->dm_mapsize) { 952 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 953 0, esc->sc_main_dmamap->dm_mapsize, 954 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 955 } 956 957 if (esc->sc_tail_dmamap->dm_mapsize) { 958 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 959 0, esc->sc_tail_dmamap->dm_mapsize, 960 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 961 } 962 963 nextdma_start(&esc->sc_scsi_dma, 964 (esc->sc_datain ? DMACSR_SETREAD : DMACSR_SETWRITE)); 965 966 if (esc->sc_datain) { 967 NCR_WRITE_REG(sc, ESP_DCTL, 968 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 969 } else { 970 NCR_WRITE_REG(sc, ESP_DCTL, 971 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 972 } 973 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 974 } 975 976 void 977 esp_dma_stop(sc) 978 struct ncr53c9x_softc *sc; 979 { 980 panic("Not yet implemented"); 981 } 982 983 int 984 esp_dma_isactive(sc) 985 struct ncr53c9x_softc *sc; 986 { 987 struct esp_softc *esc = (struct esp_softc *)sc; 988 int r = !nextdma_finished(&esc->sc_scsi_dma); 989 DPRINTF(("esp_dma_isactive = %d\n",r)); 990 return(r); 991 } 992 993 /****************************************************************/ 994 995 /* Internal dma callback routines */ 996 bus_dmamap_t 997 esp_dmacb_continue(arg) 998 void *arg; 999 { 1000 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1001 struct esp_softc *esc = (struct esp_softc *)sc; 1002 1003 DPRINTF(("%s: dma continue\n",sc->sc_dev.dv_xname)); 1004 1005 #ifdef DIAGNOSTIC 1006 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 1007 panic("%s: map not loaded in dma continue callback, datain = %d", 1008 sc->sc_dev.dv_xname,esc->sc_datain); 1009 } 1010 #endif 1011 1012 if ((!(esc->sc_loaded & ESP_LOADED_MAIN)) && 1013 (esc->sc_main_dmamap->dm_mapsize)) { 1014 DPRINTF(("%s: Loading main map\n",sc->sc_dev.dv_xname)); 1015 #if 0 1016 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 1017 0, esc->sc_main_dmamap->dm_mapsize, 1018 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1019 #endif 1020 esc->sc_loaded |= ESP_LOADED_MAIN; 1021 return(esc->sc_main_dmamap); 1022 } 1023 1024 if ((!(esc->sc_loaded & ESP_LOADED_TAIL)) && 1025 (esc->sc_tail_dmamap->dm_mapsize)) { 1026 DPRINTF(("%s: Loading tail map\n",sc->sc_dev.dv_xname)); 1027 #if 0 1028 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 1029 0, esc->sc_tail_dmamap->dm_mapsize, 1030 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1031 #endif 1032 esc->sc_loaded |= ESP_LOADED_TAIL; 1033 return(esc->sc_tail_dmamap); 1034 } 1035 1036 DPRINTF(("%s: not loading map\n",sc->sc_dev.dv_xname)); 1037 return(0); 1038 } 1039 1040 1041 void 1042 esp_dmacb_completed(map, arg) 1043 bus_dmamap_t map; 1044 void *arg; 1045 { 1046 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1047 struct esp_softc *esc = (struct esp_softc *)sc; 1048 1049 DPRINTF(("%s: dma completed\n",sc->sc_dev.dv_xname)); 1050 1051 #ifdef DIAGNOSTIC 1052 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 1053 panic("%s: invalid dma direction in completed callback, datain = %d", 1054 sc->sc_dev.dv_xname,esc->sc_datain); 1055 } 1056 #endif 1057 1058 if (map == esc->sc_main_dmamap) { 1059 #ifdef DIAGNOSTIC 1060 if ((esc->sc_loaded & ESP_UNLOADED_MAIN) || 1061 !(esc->sc_loaded & ESP_LOADED_MAIN)) { 1062 panic("%s: unexpected completed call for main map\n",sc->sc_dev.dv_xname); 1063 } 1064 #endif 1065 esc->sc_loaded |= ESP_UNLOADED_MAIN; 1066 } else if (map == esc->sc_tail_dmamap) { 1067 #ifdef DIAGNOSTIC 1068 if ((esc->sc_loaded & ESP_UNLOADED_TAIL) || 1069 !(esc->sc_loaded & ESP_LOADED_TAIL)) { 1070 panic("%s: unexpected completed call for tail map\n",sc->sc_dev.dv_xname); 1071 } 1072 #endif 1073 esc->sc_loaded |= ESP_UNLOADED_TAIL; 1074 } 1075 #ifdef DIAGNOSTIC 1076 else { 1077 panic("%s: unexpected completed map", sc->sc_dev.dv_xname); 1078 } 1079 #endif 1080 1081 #ifdef ESP_DEBUG 1082 if (esp_debug) { 1083 if (map == esc->sc_main_dmamap) { 1084 printf("%s: completed main map\n",sc->sc_dev.dv_xname); 1085 } else if (map == esc->sc_tail_dmamap) { 1086 printf("%s: completed tail map\n",sc->sc_dev.dv_xname); 1087 } 1088 } 1089 #endif 1090 1091 #if 0 1092 if ((map == esc->sc_tail_dmamap) || 1093 ((esc->sc_tail_size == 0) && (map == esc->sc_main_dmamap))) { 1094 1095 /* Clear the DMAMOD bit in the DCTL register to give control 1096 * back to the scsi chip. 1097 */ 1098 if (esc->sc_datain) { 1099 NCR_WRITE_REG(sc, ESP_DCTL, 1100 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 1101 } else { 1102 NCR_WRITE_REG(sc, ESP_DCTL, 1103 ESPDCTL_20MHZ | ESPDCTL_INTENB); 1104 } 1105 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 1106 } 1107 #endif 1108 1109 1110 #if 0 1111 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, map, 1112 0, map->dm_mapsize, 1113 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1114 #endif 1115 1116 } 1117 1118 void 1119 esp_dmacb_shutdown(arg) 1120 void *arg; 1121 { 1122 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1123 struct esp_softc *esc = (struct esp_softc *)sc; 1124 1125 DPRINTF(("%s: dma shutdown\n",sc->sc_dev.dv_xname)); 1126 1127 #if 0 1128 { 1129 /* Clear the DMAMOD bit in the DCTL register to give control 1130 * back to the scsi chip. 1131 */ 1132 if (esc->sc_datain) { 1133 NCR_WRITE_REG(sc, ESP_DCTL, 1134 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 1135 } else { 1136 NCR_WRITE_REG(sc, ESP_DCTL, 1137 ESPDCTL_20MHZ | ESPDCTL_INTENB); 1138 } 1139 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 1140 } 1141 #endif 1142 1143 DPRINTF(("%s: esp_dma_nest == %d\n",sc->sc_dev.dv_xname,esp_dma_nest)); 1144 1145 /* Stuff the end slop into fifo */ 1146 1147 #ifdef ESP_DEBUG 1148 if (esp_debug) { 1149 1150 int n = NCR_READ_REG(sc, NCR_FFLAG); 1151 DPRINTF(("%s: fifo size = %d, seq = 0x%x\n", 1152 sc->sc_dev.dv_xname,n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 1153 } 1154 #endif 1155 1156 if (esc->sc_main_dmamap->dm_mapsize) { 1157 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 1158 0, esc->sc_main_dmamap->dm_mapsize, 1159 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1160 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 1161 } 1162 1163 if (esc->sc_tail_dmamap->dm_mapsize) { 1164 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 1165 0, esc->sc_tail_dmamap->dm_mapsize, 1166 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1167 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 1168 } 1169 1170 /* copy the tail dma buffer data for read transfers */ 1171 if (esc->sc_datain == 1) { 1172 memcpy((*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size), 1173 esc->sc_tail, 1174 (esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size))); 1175 } 1176 1177 #ifdef ESP_DEBUG 1178 if (esp_debug) { 1179 printf("%s: dma_shutdown: addr=0x%08lx,len=0x%08lx,size=0x%08lx\n", 1180 sc->sc_dev.dv_xname, 1181 *esc->sc_dmaaddr, *esc->sc_dmalen, esc->sc_dmasize); 1182 if (esp_debug > 10) { 1183 esp_hex_dump(*(esc->sc_dmaaddr),esc->sc_dmasize); 1184 printf("%s: tail=0x%08lx,tailbuf=0x%08lx,tail_size=0x%08lx\n", 1185 sc->sc_dev.dv_xname, 1186 esc->sc_tail, &(esc->sc_tailbuf[0]), esc->sc_tail_size); 1187 esp_hex_dump(&(esc->sc_tailbuf[0]),sizeof(esc->sc_tailbuf)); 1188 } 1189 } 1190 #endif 1191 1192 *(esc->sc_dmaaddr) += esc->sc_dmasize; 1193 *(esc->sc_dmalen) -= esc->sc_dmasize; 1194 1195 esc->sc_main = 0; 1196 esc->sc_main_size = 0; 1197 esc->sc_tail = 0; 1198 esc->sc_tail_size = 0; 1199 1200 esc->sc_datain = -1; 1201 esc->sc_dmaaddr = 0; 1202 esc->sc_dmalen = 0; 1203 esc->sc_dmasize = 0; 1204 1205 esc->sc_loaded = 0; 1206 1207 esc->sc_begin = 0; 1208 esc->sc_begin_size = 0; 1209 1210 #ifdef ESP_DEBUG 1211 if (esp_debug) { 1212 printf(" *intrstat = 0x%b\n", 1213 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS); 1214 printf(" *intrmask = 0x%b\n", 1215 (*(volatile u_long *)IIOV(NEXT_P_INTRMASK)),NEXT_INTR_BITS); 1216 } 1217 #endif 1218 } 1219
Indexes created Fri Sep 26 08:10:20 GMT 2025