esp.c revision 1.29
1 /* $NetBSD: esp.c,v 1.29 2001/03/29 03:33:07 petrov Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Grabbed from the sparc port at revision 1.73 for the NeXT. 81 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 82 */ 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/device.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 #include <sys/user.h> 94 #include <sys/queue.h> 95 96 #include <dev/scsipi/scsi_all.h> 97 #include <dev/scsipi/scsipi_all.h> 98 #include <dev/scsipi/scsiconf.h> 99 #include <dev/scsipi/scsi_message.h> 100 101 #include <machine/bus.h> 102 #include <machine/autoconf.h> 103 #include <machine/cpu.h> 104 105 #include <dev/ic/ncr53c9xreg.h> 106 #include <dev/ic/ncr53c9xvar.h> 107 108 #include <next68k/next68k/isr.h> 109 110 #include <next68k/dev/nextdmareg.h> 111 #include <next68k/dev/nextdmavar.h> 112 113 #include "espreg.h" 114 #include "espvar.h" 115 116 #ifdef DEBUG 117 #define ESP_DEBUG 118 #endif 119 120 #ifdef ESP_DEBUG 121 int esp_debug = 0; 122 #define DPRINTF(x) if (esp_debug) printf x; 123 #else 124 #define DPRINTF(x) 125 #endif 126 127 128 void espattach_intio __P((struct device *, struct device *, void *)); 129 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 130 131 /* DMA callbacks */ 132 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 133 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 134 void esp_dmacb_shutdown __P((void *arg)); 135 136 #ifdef ESP_DEBUG 137 char esp_dma_dump[5*1024] = ""; 138 struct ncr53c9x_softc *esp_debug_sc = 0; 139 void esp_dma_store __P((struct ncr53c9x_softc *sc)); 140 void esp_dma_print __P((struct ncr53c9x_softc *sc)); 141 int esp_dma_nest = 0; 142 #endif 143 144 145 /* Linkup to the rest of the kernel */ 146 struct cfattach esp_ca = { 147 sizeof(struct esp_softc), espmatch_intio, espattach_intio 148 }; 149 150 /* 151 * Functions and the switch for the MI code. 152 */ 153 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 154 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 155 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 156 void esp_dma_reset __P((struct ncr53c9x_softc *)); 157 int esp_dma_intr __P((struct ncr53c9x_softc *)); 158 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 159 size_t *, int, size_t *)); 160 void esp_dma_go __P((struct ncr53c9x_softc *)); 161 void esp_dma_stop __P((struct ncr53c9x_softc *)); 162 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 163 164 struct ncr53c9x_glue esp_glue = { 165 esp_read_reg, 166 esp_write_reg, 167 esp_dma_isintr, 168 esp_dma_reset, 169 esp_dma_intr, 170 esp_dma_setup, 171 esp_dma_go, 172 esp_dma_stop, 173 esp_dma_isactive, 174 NULL, /* gl_clear_latched_intr */ 175 }; 176 177 #ifdef ESP_DEBUG 178 #define XCHR(x) "0123456789abcdef"[(x) & 0xf] 179 static void 180 esp_hex_dump(unsigned char *pkt, size_t len) 181 { 182 size_t i, j; 183 184 printf("00000000 "); 185 for(i=0; i<len; i++) { 186 printf("%c%c ", XCHR(pkt[i]>>4), XCHR(pkt[i])); 187 if ((i+1) % 16 == 8) { 188 printf(" "); 189 } 190 if ((i+1) % 16 == 0) { 191 printf(" %c", '|'); 192 for(j=0; j<16; j++) { 193 printf("%c", pkt[i-15+j]>=32 && pkt[i-15+j]<127?pkt[i-15+j]:'.'); 194 } 195 printf("%c\n%c%c%c%c%c%c%c%c ", '|', 196 XCHR((i+1)>>28),XCHR((i+1)>>24),XCHR((i+1)>>20),XCHR((i+1)>>16), 197 XCHR((i+1)>>12), XCHR((i+1)>>8), XCHR((i+1)>>4), XCHR(i+1)); 198 } 199 } 200 printf("\n"); 201 } 202 #endif 203 204 int 205 espmatch_intio(parent, cf, aux) 206 struct device *parent; 207 struct cfdata *cf; 208 void *aux; 209 { 210 /* should probably probe here */ 211 /* Should also probably set up data from config */ 212 213 return(1); 214 } 215 216 void 217 espattach_intio(parent, self, aux) 218 struct device *parent, *self; 219 void *aux; 220 { 221 struct esp_softc *esc = (void *)self; 222 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 223 224 #ifdef ESP_DEBUG 225 esp_debug_sc = sc; 226 #endif 227 228 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 229 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 230 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 231 panic("\n%s: can't map ncr53c90 registers", 232 sc->sc_dev.dv_xname); 233 } 234 235 sc->sc_id = 7; 236 sc->sc_freq = 20; /* Mhz */ 237 238 /* 239 * Set up glue for MI code early; we use some of it here. 240 */ 241 sc->sc_glue = &esp_glue; 242 243 /* 244 * XXX More of this should be in ncr53c9x_attach(), but 245 * XXX should we really poke around the chip that much in 246 * XXX the MI code? Think about this more... 247 */ 248 249 /* 250 * It is necessary to try to load the 2nd config register here, 251 * to find out what rev the esp chip is, else the ncr53c9x_reset 252 * will not set up the defaults correctly. 253 */ 254 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 255 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 256 sc->sc_cfg3 = NCRCFG3_CDB; 257 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 258 259 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 260 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 261 sc->sc_rev = NCR_VARIANT_ESP100; 262 } else { 263 sc->sc_cfg2 = NCRCFG2_SCSI2; 264 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 265 sc->sc_cfg3 = 0; 266 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 267 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 268 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 269 if (NCR_READ_REG(sc, NCR_CFG3) != 270 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 271 sc->sc_rev = NCR_VARIANT_ESP100A; 272 } else { 273 /* NCRCFG2_FE enables > 64K transfers */ 274 sc->sc_cfg2 |= NCRCFG2_FE; 275 sc->sc_cfg3 = 0; 276 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 277 sc->sc_rev = NCR_VARIANT_ESP200; 278 } 279 } 280 281 /* 282 * XXX minsync and maxxfer _should_ be set up in MI code, 283 * XXX but it appears to have some dependency on what sort 284 * XXX of DMA we're hooked up to, etc. 285 */ 286 287 /* 288 * This is the value used to start sync negotiations 289 * Note that the NCR register "SYNCTP" is programmed 290 * in "clocks per byte", and has a minimum value of 4. 291 * The SCSI period used in negotiation is one-fourth 292 * of the time (in nanoseconds) needed to transfer one byte. 293 * Since the chip's clock is given in MHz, we have the following 294 * formula: 4 * period = (1000 / freq) * 4 295 */ 296 sc->sc_minsync = 1000 / sc->sc_freq; 297 298 /* 299 * Alas, we must now modify the value a bit, because it's 300 * only valid when can switch on FASTCLK and FASTSCSI bits 301 * in config register 3... 302 */ 303 switch (sc->sc_rev) { 304 case NCR_VARIANT_ESP100: 305 sc->sc_maxxfer = 64 * 1024; 306 sc->sc_minsync = 0; /* No synch on old chip? */ 307 break; 308 309 case NCR_VARIANT_ESP100A: 310 sc->sc_maxxfer = 64 * 1024; 311 /* Min clocks/byte is 5 */ 312 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 313 break; 314 315 case NCR_VARIANT_ESP200: 316 sc->sc_maxxfer = 16 * 1024 * 1024; 317 /* XXX - do actually set FAST* bits */ 318 break; 319 } 320 321 /* @@@ Some ESP_DCTL bits probably need setting */ 322 NCR_WRITE_REG(sc, ESP_DCTL, 323 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 324 DELAY(10); 325 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 326 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 327 DELAY(10); 328 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 329 330 /* Set up SCSI DMA */ 331 { 332 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 333 334 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 335 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 336 panic("\n%s: can't map scsi DMA registers", 337 sc->sc_dev.dv_xname); 338 } 339 340 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 341 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 342 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 343 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 344 esc->sc_scsi_dma.nd_cb_arg = sc; 345 nextdma_config(&esc->sc_scsi_dma); 346 nextdma_init(&esc->sc_scsi_dma); 347 348 #if 0 349 /* Turn on target selection using the `dma' method */ 350 sc->sc_features |= NCR_F_DMASELECT; 351 #endif 352 353 esc->sc_datain = -1; 354 esc->sc_dmaaddr = 0; 355 esc->sc_dmalen = 0; 356 esc->sc_dmasize = 0; 357 358 esc->sc_loaded = 0; 359 360 esc->sc_begin = 0; 361 esc->sc_begin_size = 0; 362 363 { 364 int error; 365 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 366 sc->sc_maxxfer, sc->sc_maxxfer/NBPG, sc->sc_maxxfer, 367 0, BUS_DMA_ALLOCNOW, &esc->sc_main_dmamap)) != 0) { 368 panic("%s: can't create main i/o DMA map, error = %d", 369 sc->sc_dev.dv_xname,error); 370 } 371 } 372 esc->sc_main = 0; 373 esc->sc_main_size = 0; 374 375 { 376 int error; 377 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 378 ESP_DMA_TAILBUFSIZE, 379 1, ESP_DMA_TAILBUFSIZE, 380 0, BUS_DMA_ALLOCNOW, &esc->sc_tail_dmamap)) != 0) { 381 panic("%s: can't create tail i/o DMA map, error = %d", 382 sc->sc_dev.dv_xname,error); 383 } 384 } 385 esc->sc_tail = 0; 386 esc->sc_tail_size = 0; 387 388 } 389 390 /* Establish interrupt channel */ 391 isrlink_autovec(ncr53c9x_intr, sc, NEXT_I_IPL(NEXT_I_SCSI), 0); 392 INTR_ENABLE(NEXT_I_SCSI); 393 394 /* register interrupt stats */ 395 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 396 sc->sc_dev.dv_xname, "intr"); 397 398 /* Do the common parts of attachment. */ 399 ncr53c9x_attach(sc, NULL, NULL); 400 } 401 402 /* 403 * Glue functions. 404 */ 405 406 u_char 407 esp_read_reg(sc, reg) 408 struct ncr53c9x_softc *sc; 409 int reg; 410 { 411 struct esp_softc *esc = (struct esp_softc *)sc; 412 413 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 414 } 415 416 void 417 esp_write_reg(sc, reg, val) 418 struct ncr53c9x_softc *sc; 419 int reg; 420 u_char val; 421 { 422 struct esp_softc *esc = (struct esp_softc *)sc; 423 424 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 425 } 426 427 int 428 esp_dma_isintr(sc) 429 struct ncr53c9x_softc *sc; 430 { 431 struct esp_softc *esc = (struct esp_softc *)sc; 432 433 int r = (INTR_OCCURRED(NEXT_I_SCSI)); 434 435 if (r) { 436 437 { 438 int flushcount; 439 int s; 440 s = spldma(); 441 442 flushcount = 0; 443 444 #ifdef ESP_DEBUG 445 esp_dma_nest++; 446 447 if (esp_debug) { 448 char sbuf[256]; 449 450 bitmask_snprintf((*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)), 451 NEXT_INTR_BITS, sbuf, sizeof(sbuf)); 452 printf("esp_dma_isintr = 0x%s\n", sbuf); 453 } 454 #endif 455 456 while (esp_dma_isactive(sc)) { 457 flushcount++; 458 459 #ifdef DIAGNOSTIC 460 r = (INTR_OCCURRED(NEXT_I_SCSI)); 461 if (!r) panic("esp intr enabled but dma failed to flush"); 462 #endif 463 #ifdef DIAGNOSTIC 464 #if 0 465 if ((esc->sc_loaded & (ESP_LOADED_TAIL/* |ESP_UNLOADED_MAIN */)) 466 != (ESP_LOADED_TAIL /* |ESP_UNLOADED_MAIN */)) { 467 if (esc->sc_datain) { 468 NCR_WRITE_REG(sc, ESP_DCTL, 469 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 470 } else { 471 NCR_WRITE_REG(sc, ESP_DCTL, 472 ESPDCTL_20MHZ | ESPDCTL_INTENB); 473 } 474 next_dma_print(&esc->sc_scsi_dma); 475 esp_dma_print(sc); 476 printf("%s: unexpected flush: tc=0x%06x\n", 477 sc->sc_dev.dv_xname, 478 (((sc->sc_cfg2 & NCRCFG2_FE) 479 ? NCR_READ_REG(sc, NCR_TCH) : 0)<<16)| 480 (NCR_READ_REG(sc, NCR_TCM)<<8)| 481 NCR_READ_REG(sc, NCR_TCL)); 482 ncr53c9x_readregs(sc); 483 printf("%s: readregs[intr=%02x,stat=%02x,step=%02x]\n", 484 sc->sc_dev.dv_xname, 485 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep); 486 panic("%s: flushing flushing non-tail dma\n", 487 sc->sc_dev.dv_xname); 488 } 489 #endif 490 #endif 491 DPRINTF(("%s: flushing dma, count = %d\n", sc->sc_dev.dv_xname,flushcount)); 492 if (esc->sc_datain) { 493 NCR_WRITE_REG(sc, ESP_DCTL, 494 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD | ESPDCTL_FLUSH); 495 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 496 NCR_WRITE_REG(sc, ESP_DCTL, 497 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 498 } else { 499 NCR_WRITE_REG(sc, ESP_DCTL, 500 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_FLUSH); 501 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 502 NCR_WRITE_REG(sc, ESP_DCTL, 503 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 504 } 505 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 506 507 { 508 int nr; 509 nr = nextdma_intr(&esc->sc_scsi_dma); 510 if (nr) { 511 DPRINTF(("nextma_intr = %d\n",nr)); 512 #ifdef DIAGNOSTIC 513 #if 0 514 if (flushcount > 16) { 515 printf("%s: unexpected flushcount %d\n",sc->sc_dev.dv_xname,flushcount); 516 } 517 #endif 518 #endif 519 #ifdef DIAGNOSTIC 520 #if 0 521 if (esp_dma_isactive(sc)) { 522 esp_dma_print(sc); 523 printf("%s: dma still active after a flush with count %d\n", 524 sc->sc_dev.dv_xname,flushcount); 525 526 } 527 #endif 528 #endif 529 flushcount = 0; 530 } 531 } 532 } 533 534 #ifdef ESP_DEBUG 535 esp_dma_nest--; 536 #endif 537 538 splx(s); 539 } 540 541 #ifdef DIAGNOSTIC 542 r = (INTR_OCCURRED(NEXT_I_SCSI)); 543 if (!r) panic("esp intr not enabled after dma flush"); 544 #endif 545 546 /* Clear the DMAMOD bit in the DCTL register, since if this 547 * routine returns true, then the ncr53c9x_intr handler will 548 * be called and needs access to the scsi registers. 549 */ 550 if (esc->sc_datain) { 551 NCR_WRITE_REG(sc, ESP_DCTL, 552 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 553 } else { 554 NCR_WRITE_REG(sc, ESP_DCTL, 555 ESPDCTL_20MHZ | ESPDCTL_INTENB); 556 } 557 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 558 559 } 560 561 return (r); 562 } 563 564 void 565 esp_dma_reset(sc) 566 struct ncr53c9x_softc *sc; 567 { 568 struct esp_softc *esc = (struct esp_softc *)sc; 569 570 DPRINTF(("esp dma reset\n")); 571 572 #ifdef ESP_DEBUG 573 if (esp_debug) { 574 char sbuf[256]; 575 576 bitmask_snprintf((*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)), 577 NEXT_INTR_BITS, sbuf, sizeof(sbuf)); 578 printf(" *intrstat = 0x%s\n", sbuf); 579 580 bitmask_snprintf((*(volatile u_long *)IIOV(NEXT_P_INTRMASK)), 581 NEXT_INTR_BITS, sbuf, sizeof(sbuf)); 582 printf(" *intrmask = 0x%s\n", sbuf); 583 } 584 #endif 585 586 /* Clear the DMAMOD bit in the DCTL register: */ 587 NCR_WRITE_REG(sc, ESP_DCTL, 588 ESPDCTL_20MHZ | ESPDCTL_INTENB); 589 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 590 591 nextdma_reset(&esc->sc_scsi_dma); 592 593 esc->sc_datain = -1; 594 esc->sc_dmaaddr = 0; 595 esc->sc_dmalen = 0; 596 esc->sc_dmasize = 0; 597 598 esc->sc_loaded = 0; 599 600 esc->sc_begin = 0; 601 esc->sc_begin_size = 0; 602 603 if (esc->sc_main_dmamap->dm_mapsize) { 604 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 605 } 606 esc->sc_main = 0; 607 esc->sc_main_size = 0; 608 609 if (esc->sc_tail_dmamap->dm_mapsize) { 610 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 611 } 612 esc->sc_tail = 0; 613 esc->sc_tail_size = 0; 614 } 615 616 int 617 esp_dma_intr(sc) 618 struct ncr53c9x_softc *sc; 619 { 620 #ifdef DIAGNOSTIC 621 panic("%s: esp_dma_intr shouldn't be invoked.\n", sc->sc_dev.dv_xname); 622 #endif 623 624 return -1; 625 } 626 627 /* it appears that: 628 * addr and len arguments to this need to be kept up to date 629 * with the status of the transfter. 630 * the dmasize of this is the actual length of the transfer 631 * request, which is guaranteed to be less than maxxfer. 632 * (len may be > maxxfer) 633 */ 634 635 int 636 esp_dma_setup(sc, addr, len, datain, dmasize) 637 struct ncr53c9x_softc *sc; 638 caddr_t *addr; 639 size_t *len; 640 int datain; 641 size_t *dmasize; 642 { 643 struct esp_softc *esc = (struct esp_softc *)sc; 644 645 #ifdef DIAGNOSTIC 646 #ifdef ESP_DEBUG 647 /* if this is a read DMA, pre-fill the buffer with 0xdeadbeef 648 * to identify bogus reads 649 */ 650 if (datain) { 651 int *v = (int *)(*addr); 652 int i; 653 for(i=0;i<((*len)/4);i++) v[i] = 0xdeadbeef; 654 v = (int *)(&(esc->sc_tailbuf[0])); 655 for(i=0;i<((sizeof(esc->sc_tailbuf)/4));i++) v[i] = 0xdeaffeed; 656 } else { 657 int *v; 658 int i; 659 v = (int *)(&(esc->sc_tailbuf[0])); 660 for(i=0;i<((sizeof(esc->sc_tailbuf)/4));i++) v[i] = 0xfeeb1eed; 661 } 662 #endif 663 #endif 664 665 DPRINTF(("esp_dma_setup(0x%08lx,0x%08lx,0x%08lx)\n",*addr,*len,*dmasize)); 666 667 #if 0 668 #ifdef DIAGNOSTIC /* @@@ this is ok sometimes. verify that we handle it ok 669 * and then remove this check 670 */ 671 if (*len != *dmasize) { 672 panic("esp dmalen 0x%lx != size 0x%lx",*len,*dmasize); 673 } 674 #endif 675 #endif 676 677 #ifdef DIAGNOSTIC 678 if ((esc->sc_datain != -1) || 679 (esc->sc_main_dmamap->dm_mapsize != 0) || 680 (esc->sc_tail_dmamap->dm_mapsize != 0) || 681 (esc->sc_dmasize != 0)) { 682 panic("%s: map already loaded in esp_dma_setup\n" 683 "\tdatain = %d\n\tmain_mapsize=%d\n\tail_mapsize=%d\n\tdmasize = %d", 684 sc->sc_dev.dv_xname, esc->sc_datain, 685 esc->sc_main_dmamap->dm_mapsize, 686 esc->sc_tail_dmamap->dm_mapsize, 687 esc->sc_dmasize); 688 } 689 #endif 690 691 /* we are sometimes asked to dma zero bytes, that's easy */ 692 if (*dmasize <= 0) { 693 return(0); 694 } 695 696 /* Save these in case we have to abort DMA */ 697 esc->sc_datain = datain; 698 esc->sc_dmaaddr = addr; 699 esc->sc_dmalen = len; 700 esc->sc_dmasize = *dmasize; 701 702 esc->sc_loaded = 0; 703 704 #define DMA_SCSI_ALIGNMENT 16 705 #define DMA_SCSI_ALIGN(type, addr) \ 706 ((type)(((unsigned)(addr)+DMA_SCSI_ALIGNMENT-1) \ 707 &~(DMA_SCSI_ALIGNMENT-1))) 708 #define DMA_SCSI_ALIGNED(addr) \ 709 (((unsigned)(addr)&(DMA_SCSI_ALIGNMENT-1))==0) 710 711 { 712 size_t slop_bgn_size; /* # bytes to be fifo'd at beginning */ 713 size_t slop_end_size; /* # bytes to be transferred in tail buffer */ 714 715 { 716 u_long bgn = (u_long)(*esc->sc_dmaaddr); 717 u_long end = (u_long)(*esc->sc_dmaaddr+esc->sc_dmasize); 718 719 slop_bgn_size = DMA_SCSI_ALIGNMENT-(bgn % DMA_SCSI_ALIGNMENT); 720 if (slop_bgn_size == DMA_SCSI_ALIGNMENT) slop_bgn_size = 0; 721 slop_end_size = (end % DMA_ENDALIGNMENT); 722 } 723 724 /* Force a minimum slop end size. This ensures that write 725 * requests will overrun, as required to get completion interrupts. 726 * In addition, since the tail buffer is guaranteed to be mapped 727 * in a single dma segment, the overrun won't accidentally 728 * end up in its own segment. 729 */ 730 if (!esc->sc_datain) { 731 #if 0 732 slop_end_size += ESP_DMA_MAXTAIL; 733 #else 734 slop_end_size += 0x10; 735 #endif 736 } 737 738 /* Check to make sure we haven't counted extra slop 739 * as would happen for a very short dma buffer, also 740 * for short buffers, just stuff the entire thing in the tail 741 */ 742 if ((slop_bgn_size+slop_end_size >= esc->sc_dmasize) 743 #if 0 744 || (esc->sc_dmasize <= ESP_DMA_MAXTAIL) 745 #endif 746 ) 747 { 748 slop_bgn_size = 0; 749 slop_end_size = esc->sc_dmasize; 750 } 751 752 /* initialize the fifo buffer */ 753 if (slop_bgn_size) { 754 esc->sc_begin = *esc->sc_dmaaddr; 755 esc->sc_begin_size = slop_bgn_size; 756 } else { 757 esc->sc_begin = 0; 758 esc->sc_begin_size = 0; 759 } 760 761 /* Load the normal DMA map */ 762 { 763 esc->sc_main = *esc->sc_dmaaddr+slop_bgn_size; 764 esc->sc_main_size = (esc->sc_dmasize)-(slop_end_size+slop_bgn_size); 765 766 if (esc->sc_main_size) { 767 int error; 768 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 769 esc->sc_main_dmamap, 770 esc->sc_main, esc->sc_main_size, 771 NULL, BUS_DMA_NOWAIT); 772 if (error) { 773 panic("%s: can't load main dma map. error = %d, addr=0x%08x, size=0x%08x", 774 sc->sc_dev.dv_xname, error,esc->sc_main,esc->sc_main_size); 775 } 776 #if 0 777 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 778 0, esc->sc_main_dmamap->dm_mapsize, 779 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 780 #endif 781 } else { 782 esc->sc_main = 0; 783 } 784 } 785 786 /* Load the tail DMA map */ 787 if (slop_end_size) { 788 esc->sc_tail = DMA_ENDALIGN(caddr_t,esc->sc_tailbuf+slop_end_size)-slop_end_size; 789 /* If the beginning of the tail is not correctly aligned, 790 * we have no choice but to align the start, which might then unalign the end. 791 */ 792 esc->sc_tail = DMA_SCSI_ALIGN(caddr_t,esc->sc_tail); 793 /* So therefore, we change the tail size to be end aligned again. */ 794 esc->sc_tail_size = DMA_ENDALIGN(caddr_t,esc->sc_tail+slop_end_size)-esc->sc_tail; 795 796 /* @@@ next dma overrun lossage */ 797 if (!esc->sc_datain) { 798 esc->sc_tail_size += ESP_DMA_OVERRUN; 799 } 800 801 { 802 int error; 803 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 804 esc->sc_tail_dmamap, 805 esc->sc_tail, esc->sc_tail_size, 806 NULL, BUS_DMA_NOWAIT); 807 if (error) { 808 panic("%s: can't load tail dma map. error = %d, addr=0x%08x, size=0x%08x", 809 sc->sc_dev.dv_xname, error,esc->sc_tail,esc->sc_tail_size); 810 } 811 #if 0 812 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 813 0, esc->sc_tail_dmamap->dm_mapsize, 814 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 815 #endif 816 } 817 } 818 } 819 820 return (0); 821 } 822 823 #ifdef ESP_DEBUG 824 /* For debugging */ 825 void 826 esp_dma_store(sc) 827 struct ncr53c9x_softc *sc; 828 { 829 struct esp_softc *esc = (struct esp_softc *)sc; 830 char *p = &esp_dma_dump[0]; 831 832 p += sprintf(p,"%s: sc_datain=%d\n",sc->sc_dev.dv_xname,esc->sc_datain); 833 p += sprintf(p,"%s: sc_loaded=0x%08x\n",sc->sc_dev.dv_xname,esc->sc_loaded); 834 835 if (esc->sc_dmaaddr) { 836 p += sprintf(p,"%s: sc_dmaaddr=0x%08lx\n",sc->sc_dev.dv_xname,*esc->sc_dmaaddr); 837 } else { 838 p += sprintf(p,"%s: sc_dmaaddr=NULL\n",sc->sc_dev.dv_xname); 839 } 840 if (esc->sc_dmalen) { 841 p += sprintf(p,"%s: sc_dmalen=0x%08lx\n",sc->sc_dev.dv_xname,*esc->sc_dmalen); 842 } else { 843 p += sprintf(p,"%s: sc_dmalen=NULL\n",sc->sc_dev.dv_xname); 844 } 845 p += sprintf(p,"%s: sc_dmasize=0x%08x\n",sc->sc_dev.dv_xname,esc->sc_dmasize); 846 847 p += sprintf(p,"%s: sc_begin = 0x%08x, sc_begin_size = 0x%08x\n", 848 sc->sc_dev.dv_xname, esc->sc_begin, esc->sc_begin_size); 849 p += sprintf(p,"%s: sc_main = 0x%08x, sc_main_size = 0x%08x\n", 850 sc->sc_dev.dv_xname, esc->sc_main, esc->sc_main_size); 851 { 852 int i; 853 bus_dmamap_t map = esc->sc_main_dmamap; 854 p += sprintf(p,"%s: sc_main_dmamap. mapsize = 0x%08x, nsegs = %d\n", 855 sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs); 856 for(i=0;i<map->dm_nsegs;i++) { 857 p += sprintf(p,"%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n", 858 sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len); 859 } 860 } 861 p += sprintf(p,"%s: sc_tail = 0x%08x, sc_tail_size = 0x%08x\n", 862 sc->sc_dev.dv_xname, esc->sc_tail, esc->sc_tail_size); 863 { 864 int i; 865 bus_dmamap_t map = esc->sc_tail_dmamap; 866 p += sprintf(p,"%s: sc_tail_dmamap. mapsize = 0x%08x, nsegs = %d\n", 867 sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs); 868 for(i=0;i<map->dm_nsegs;i++) { 869 p += sprintf(p,"%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n", 870 sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len); 871 } 872 } 873 } 874 875 void 876 esp_dma_print(sc) 877 struct ncr53c9x_softc *sc; 878 { 879 esp_dma_store(sc); 880 printf("%s",esp_dma_dump); 881 } 882 #endif 883 884 void 885 esp_dma_go(sc) 886 struct ncr53c9x_softc *sc; 887 { 888 struct esp_softc *esc = (struct esp_softc *)sc; 889 890 DPRINTF(("%s: esp_dma_go(datain = %d)\n", 891 sc->sc_dev.dv_xname, esc->sc_datain)); 892 893 #ifdef ESP_DEBUG 894 if (esp_debug) esp_dma_print(sc); 895 else esp_dma_store(sc); 896 #endif 897 898 #ifdef ESP_DEBUG 899 { 900 int n = NCR_READ_REG(sc, NCR_FFLAG); 901 DPRINTF(("%s: fifo size = %d, seq = 0x%x\n", 902 sc->sc_dev.dv_xname, 903 n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 904 } 905 #endif 906 907 /* zero length dma transfers are boring */ 908 if (esc->sc_dmasize == 0) { 909 return; 910 } 911 912 #if defined(DIAGNOSTIC) 913 if ((esc->sc_begin_size == 0) && 914 (esc->sc_main_dmamap->dm_mapsize == 0) && 915 (esc->sc_tail_dmamap->dm_mapsize == 0)) { 916 esp_dma_print(sc); 917 panic("%s: No DMA requested!",sc->sc_dev.dv_xname); 918 } 919 #endif 920 921 /* Stuff the fifo with the begin buffer */ 922 if (esc->sc_datain) { 923 int i; 924 DPRINTF(("%s: FIFO read of %d bytes:", 925 sc->sc_dev.dv_xname,esc->sc_begin_size)); 926 for(i=0;i<esc->sc_begin_size;i++) { 927 esc->sc_begin[i]=NCR_READ_REG(sc, NCR_FIFO); 928 DPRINTF((" %02x",esc->sc_begin[i]&0xff)); 929 } 930 DPRINTF(("\n")); 931 } else { 932 int i; 933 DPRINTF(("%s: FIFO write of %d bytes:", 934 sc->sc_dev.dv_xname,esc->sc_begin_size)); 935 for(i=0;i<esc->sc_begin_size;i++) { 936 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_begin[i]); 937 DPRINTF((" %02x",esc->sc_begin[i]&0xff)); 938 } 939 DPRINTF(("\n")); 940 } 941 942 /* if we are a dma write cycle, copy the end slop */ 943 if (esc->sc_datain == 0) { 944 memcpy(esc->sc_tail, 945 (*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size), 946 (esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size))); 947 } 948 949 if (esc->sc_main_dmamap->dm_mapsize) { 950 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 951 0, esc->sc_main_dmamap->dm_mapsize, 952 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 953 } 954 955 if (esc->sc_tail_dmamap->dm_mapsize) { 956 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 957 0, esc->sc_tail_dmamap->dm_mapsize, 958 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 959 } 960 961 nextdma_start(&esc->sc_scsi_dma, 962 (esc->sc_datain ? DMACSR_SETREAD : DMACSR_SETWRITE)); 963 964 if (esc->sc_datain) { 965 NCR_WRITE_REG(sc, ESP_DCTL, 966 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 967 } else { 968 NCR_WRITE_REG(sc, ESP_DCTL, 969 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 970 } 971 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 972 } 973 974 void 975 esp_dma_stop(sc) 976 struct ncr53c9x_softc *sc; 977 { 978 panic("Not yet implemented"); 979 } 980 981 int 982 esp_dma_isactive(sc) 983 struct ncr53c9x_softc *sc; 984 { 985 struct esp_softc *esc = (struct esp_softc *)sc; 986 int r = !nextdma_finished(&esc->sc_scsi_dma); 987 DPRINTF(("esp_dma_isactive = %d\n",r)); 988 return(r); 989 } 990 991 /****************************************************************/ 992 993 /* Internal dma callback routines */ 994 bus_dmamap_t 995 esp_dmacb_continue(arg) 996 void *arg; 997 { 998 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 999 struct esp_softc *esc = (struct esp_softc *)sc; 1000 1001 DPRINTF(("%s: dma continue\n",sc->sc_dev.dv_xname)); 1002 1003 #ifdef DIAGNOSTIC 1004 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 1005 panic("%s: map not loaded in dma continue callback, datain = %d", 1006 sc->sc_dev.dv_xname,esc->sc_datain); 1007 } 1008 #endif 1009 1010 if ((!(esc->sc_loaded & ESP_LOADED_MAIN)) && 1011 (esc->sc_main_dmamap->dm_mapsize)) { 1012 DPRINTF(("%s: Loading main map\n",sc->sc_dev.dv_xname)); 1013 #if 0 1014 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 1015 0, esc->sc_main_dmamap->dm_mapsize, 1016 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1017 #endif 1018 esc->sc_loaded |= ESP_LOADED_MAIN; 1019 return(esc->sc_main_dmamap); 1020 } 1021 1022 if ((!(esc->sc_loaded & ESP_LOADED_TAIL)) && 1023 (esc->sc_tail_dmamap->dm_mapsize)) { 1024 DPRINTF(("%s: Loading tail map\n",sc->sc_dev.dv_xname)); 1025 #if 0 1026 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 1027 0, esc->sc_tail_dmamap->dm_mapsize, 1028 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1029 #endif 1030 esc->sc_loaded |= ESP_LOADED_TAIL; 1031 return(esc->sc_tail_dmamap); 1032 } 1033 1034 DPRINTF(("%s: not loading map\n",sc->sc_dev.dv_xname)); 1035 return(0); 1036 } 1037 1038 1039 void 1040 esp_dmacb_completed(map, arg) 1041 bus_dmamap_t map; 1042 void *arg; 1043 { 1044 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1045 struct esp_softc *esc = (struct esp_softc *)sc; 1046 1047 DPRINTF(("%s: dma completed\n",sc->sc_dev.dv_xname)); 1048 1049 #ifdef DIAGNOSTIC 1050 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 1051 panic("%s: invalid dma direction in completed callback, datain = %d", 1052 sc->sc_dev.dv_xname,esc->sc_datain); 1053 } 1054 #endif 1055 1056 if (map == esc->sc_main_dmamap) { 1057 #ifdef DIAGNOSTIC 1058 if ((esc->sc_loaded & ESP_UNLOADED_MAIN) || 1059 !(esc->sc_loaded & ESP_LOADED_MAIN)) { 1060 panic("%s: unexpected completed call for main map\n",sc->sc_dev.dv_xname); 1061 } 1062 #endif 1063 esc->sc_loaded |= ESP_UNLOADED_MAIN; 1064 } else if (map == esc->sc_tail_dmamap) { 1065 #ifdef DIAGNOSTIC 1066 if ((esc->sc_loaded & ESP_UNLOADED_TAIL) || 1067 !(esc->sc_loaded & ESP_LOADED_TAIL)) { 1068 panic("%s: unexpected completed call for tail map\n",sc->sc_dev.dv_xname); 1069 } 1070 #endif 1071 esc->sc_loaded |= ESP_UNLOADED_TAIL; 1072 } 1073 #ifdef DIAGNOSTIC 1074 else { 1075 panic("%s: unexpected completed map", sc->sc_dev.dv_xname); 1076 } 1077 #endif 1078 1079 #ifdef ESP_DEBUG 1080 if (esp_debug) { 1081 if (map == esc->sc_main_dmamap) { 1082 printf("%s: completed main map\n",sc->sc_dev.dv_xname); 1083 } else if (map == esc->sc_tail_dmamap) { 1084 printf("%s: completed tail map\n",sc->sc_dev.dv_xname); 1085 } 1086 } 1087 #endif 1088 1089 #if 0 1090 if ((map == esc->sc_tail_dmamap) || 1091 ((esc->sc_tail_size == 0) && (map == esc->sc_main_dmamap))) { 1092 1093 /* Clear the DMAMOD bit in the DCTL register to give control 1094 * back to the scsi chip. 1095 */ 1096 if (esc->sc_datain) { 1097 NCR_WRITE_REG(sc, ESP_DCTL, 1098 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 1099 } else { 1100 NCR_WRITE_REG(sc, ESP_DCTL, 1101 ESPDCTL_20MHZ | ESPDCTL_INTENB); 1102 } 1103 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 1104 } 1105 #endif 1106 1107 1108 #if 0 1109 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, map, 1110 0, map->dm_mapsize, 1111 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1112 #endif 1113 1114 } 1115 1116 void 1117 esp_dmacb_shutdown(arg) 1118 void *arg; 1119 { 1120 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1121 struct esp_softc *esc = (struct esp_softc *)sc; 1122 1123 DPRINTF(("%s: dma shutdown\n",sc->sc_dev.dv_xname)); 1124 1125 #if 0 1126 { 1127 /* Clear the DMAMOD bit in the DCTL register to give control 1128 * back to the scsi chip. 1129 */ 1130 if (esc->sc_datain) { 1131 NCR_WRITE_REG(sc, ESP_DCTL, 1132 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 1133 } else { 1134 NCR_WRITE_REG(sc, ESP_DCTL, 1135 ESPDCTL_20MHZ | ESPDCTL_INTENB); 1136 } 1137 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 1138 } 1139 #endif 1140 1141 DPRINTF(("%s: esp_dma_nest == %d\n",sc->sc_dev.dv_xname,esp_dma_nest)); 1142 1143 /* Stuff the end slop into fifo */ 1144 1145 #ifdef ESP_DEBUG 1146 if (esp_debug) { 1147 1148 int n = NCR_READ_REG(sc, NCR_FFLAG); 1149 DPRINTF(("%s: fifo size = %d, seq = 0x%x\n", 1150 sc->sc_dev.dv_xname,n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 1151 } 1152 #endif 1153 1154 if (esc->sc_main_dmamap->dm_mapsize) { 1155 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 1156 0, esc->sc_main_dmamap->dm_mapsize, 1157 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1158 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 1159 } 1160 1161 if (esc->sc_tail_dmamap->dm_mapsize) { 1162 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 1163 0, esc->sc_tail_dmamap->dm_mapsize, 1164 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1165 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 1166 } 1167 1168 /* copy the tail dma buffer data for read transfers */ 1169 if (esc->sc_datain == 1) { 1170 memcpy((*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size), 1171 esc->sc_tail, 1172 (esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size))); 1173 } 1174 1175 #ifdef ESP_DEBUG 1176 if (esp_debug) { 1177 printf("%s: dma_shutdown: addr=0x%08lx,len=0x%08lx,size=0x%08lx\n", 1178 sc->sc_dev.dv_xname, 1179 *esc->sc_dmaaddr, *esc->sc_dmalen, esc->sc_dmasize); 1180 if (esp_debug > 10) { 1181 esp_hex_dump(*(esc->sc_dmaaddr),esc->sc_dmasize); 1182 printf("%s: tail=0x%08lx,tailbuf=0x%08lx,tail_size=0x%08lx\n", 1183 sc->sc_dev.dv_xname, 1184 esc->sc_tail, &(esc->sc_tailbuf[0]), esc->sc_tail_size); 1185 esp_hex_dump(&(esc->sc_tailbuf[0]),sizeof(esc->sc_tailbuf)); 1186 } 1187 } 1188 #endif 1189 1190 *(esc->sc_dmaaddr) += esc->sc_dmasize; 1191 *(esc->sc_dmalen) -= esc->sc_dmasize; 1192 1193 esc->sc_main = 0; 1194 esc->sc_main_size = 0; 1195 esc->sc_tail = 0; 1196 esc->sc_tail_size = 0; 1197 1198 esc->sc_datain = -1; 1199 esc->sc_dmaaddr = 0; 1200 esc->sc_dmalen = 0; 1201 esc->sc_dmasize = 0; 1202 1203 esc->sc_loaded = 0; 1204 1205 esc->sc_begin = 0; 1206 esc->sc_begin_size = 0; 1207 1208 #ifdef ESP_DEBUG 1209 if (esp_debug) { 1210 char sbuf[256]; 1211 1212 bitmask_snprintf((*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)), 1213 NEXT_INTR_BITS, sbuf, sizeof(sbuf)); 1214 printf(" *intrstat = 0x%s\n", sbuf); 1215 1216 bitmask_snprintf((*(volatile u_long *)IIOV(NEXT_P_INTRMASK)), 1217 NEXT_INTR_BITS, sbuf, sizeof(sbuf)); 1218 printf(" *intrmask = 0x%s\n", sbuf); 1219 } 1220 #endif 1221 } 1222
Indexes created Thu Sep 25 16:09:42 GMT 2025