esp.c revision 1.3
1 /* $NetBSD: esp.c,v 1.3 1998/07/19 21:41:16 dbj Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Charles M. Hannum. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * Copyright (c) 1994 Peter Galbavy 71 * Copyright (c) 1995 Paul Kranenburg 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 3. All advertising materials mentioning features or use of this software 83 * must display the following acknowledgement: 84 * This product includes software developed by Peter Galbavy 85 * 4. The name of the author may not be used to endorse or promote products 86 * derived from this software without specific prior written permission. 87 * 88 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 89 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 90 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 91 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 92 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 93 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 94 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 95 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 96 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 97 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 98 * POSSIBILITY OF SUCH DAMAGE. 99 */ 100 101 /* 102 * Based on aic6360 by Jarle Greipsland 103 * 104 * Acknowledgements: Many of the algorithms used in this driver are 105 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 106 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 107 */ 108 109 /* 110 * Grabbed from the sparc port at revision 1.73 for the NeXT. 111 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 112 */ 113 114 #include <sys/types.h> 115 #include <sys/param.h> 116 #include <sys/systm.h> 117 #include <sys/kernel.h> 118 #include <sys/errno.h> 119 #include <sys/ioctl.h> 120 #include <sys/device.h> 121 #include <sys/buf.h> 122 #include <sys/proc.h> 123 #include <sys/user.h> 124 #include <sys/queue.h> 125 126 #include <dev/scsipi/scsi_all.h> 127 #include <dev/scsipi/scsipi_all.h> 128 #include <dev/scsipi/scsiconf.h> 129 #include <dev/scsipi/scsi_message.h> 130 131 #include <machine/bus.h> 132 #include <machine/autoconf.h> 133 #include <machine/cpu.h> 134 135 #include <dev/ic/ncr53c9xreg.h> 136 #include <dev/ic/ncr53c9xvar.h> 137 138 #include <next68k/next68k/isr.h> 139 140 #include <next68k/dev/nextdmareg.h> 141 #include <next68k/dev/nextdmavar.h> 142 143 #include "espreg.h" 144 #include "espvar.h" 145 146 void espattach_intio __P((struct device *, struct device *, void *)); 147 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 148 149 /* DMA callbacks */ 150 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 151 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 152 void esp_dmacb_shutdown __P((void *arg)); 153 154 /* Linkup to the rest of the kernel */ 155 struct cfattach esp_ca = { 156 sizeof(struct esp_softc), espmatch_intio, espattach_intio 157 }; 158 159 struct scsipi_adapter esp_switch = { 160 ncr53c9x_scsi_cmd, 161 minphys, /* no max at this level; handled by DMA code */ 162 NULL, 163 NULL, 164 }; 165 166 struct scsipi_device esp_dev = { 167 NULL, /* Use default error handler */ 168 NULL, /* have a queue, served by this */ 169 NULL, /* have no async handler */ 170 NULL, /* Use default 'done' routine */ 171 }; 172 173 /* 174 * Functions and the switch for the MI code. 175 */ 176 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 177 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 178 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 179 void esp_dma_reset __P((struct ncr53c9x_softc *)); 180 int esp_dma_intr __P((struct ncr53c9x_softc *)); 181 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 182 size_t *, int, size_t *)); 183 void esp_dma_go __P((struct ncr53c9x_softc *)); 184 void esp_dma_stop __P((struct ncr53c9x_softc *)); 185 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 186 187 struct ncr53c9x_glue esp_glue = { 188 esp_read_reg, 189 esp_write_reg, 190 esp_dma_isintr, 191 esp_dma_reset, 192 esp_dma_intr, 193 esp_dma_setup, 194 esp_dma_go, 195 esp_dma_stop, 196 esp_dma_isactive, 197 NULL, /* gl_clear_latched_intr */ 198 }; 199 200 int 201 espmatch_intio(parent, cf, aux) 202 struct device *parent; 203 struct cfdata *cf; 204 void *aux; 205 { 206 /* should probably probe here */ 207 /* Should also probably set up data from config */ 208 209 #if 1 210 /* this code isn't working yet, don't match on it */ 211 return(0); 212 #else 213 return(1); 214 #endif 215 } 216 217 void 218 espattach_intio(parent, self, aux) 219 struct device *parent, *self; 220 void *aux; 221 { 222 struct esp_softc *esc = (void *)self; 223 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 224 225 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 226 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 227 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 228 panic("\n%s: can't map ncr53c90 registers", 229 sc->sc_dev.dv_xname); 230 } 231 232 sc->sc_id = 7; 233 sc->sc_freq = 20; /* Mhz */ 234 235 /* 236 * Set up glue for MI code early; we use some of it here. 237 */ 238 sc->sc_glue = &esp_glue; 239 240 /* 241 * XXX More of this should be in ncr53c9x_attach(), but 242 * XXX should we really poke around the chip that much in 243 * XXX the MI code? Think about this more... 244 */ 245 246 /* 247 * It is necessary to try to load the 2nd config register here, 248 * to find out what rev the esp chip is, else the ncr53c9x_reset 249 * will not set up the defaults correctly. 250 */ 251 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 252 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 253 sc->sc_cfg3 = NCRCFG3_CDB; 254 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 255 256 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 257 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 258 sc->sc_rev = NCR_VARIANT_ESP100; 259 } else { 260 sc->sc_cfg2 = NCRCFG2_SCSI2; 261 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 262 sc->sc_cfg3 = 0; 263 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 264 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 265 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 266 if (NCR_READ_REG(sc, NCR_CFG3) != 267 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 268 sc->sc_rev = NCR_VARIANT_ESP100A; 269 } else { 270 /* NCRCFG2_FE enables > 64K transfers */ 271 sc->sc_cfg2 |= NCRCFG2_FE; 272 sc->sc_cfg3 = 0; 273 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 274 sc->sc_rev = NCR_VARIANT_ESP200; 275 } 276 } 277 278 /* 279 * XXX minsync and maxxfer _should_ be set up in MI code, 280 * XXX but it appears to have some dependency on what sort 281 * XXX of DMA we're hooked up to, etc. 282 */ 283 284 /* 285 * This is the value used to start sync negotiations 286 * Note that the NCR register "SYNCTP" is programmed 287 * in "clocks per byte", and has a minimum value of 4. 288 * The SCSI period used in negotiation is one-fourth 289 * of the time (in nanoseconds) needed to transfer one byte. 290 * Since the chip's clock is given in MHz, we have the following 291 * formula: 4 * period = (1000 / freq) * 4 292 */ 293 sc->sc_minsync = 1000 / sc->sc_freq; 294 295 /* 296 * Alas, we must now modify the value a bit, because it's 297 * only valid when can switch on FASTCLK and FASTSCSI bits 298 * in config register 3... 299 */ 300 switch (sc->sc_rev) { 301 case NCR_VARIANT_ESP100: 302 sc->sc_maxxfer = 64 * 1024; 303 sc->sc_minsync = 0; /* No synch on old chip? */ 304 break; 305 306 case NCR_VARIANT_ESP100A: 307 sc->sc_maxxfer = 64 * 1024; 308 /* Min clocks/byte is 5 */ 309 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 310 break; 311 312 case NCR_VARIANT_ESP200: 313 sc->sc_maxxfer = 16 * 1024 * 1024; 314 /* XXX - do actually set FAST* bits */ 315 break; 316 } 317 318 /* @@@ Some ESP_DCTL bits probably need setting */ 319 NCR_WRITE_REG(sc, ESP_DCTL, 320 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 321 DELAY(10); 322 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 323 DELAY(10); 324 325 /* Set up SCSI DMA */ 326 { 327 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 328 329 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 330 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 331 panic("\n%s: can't map scsi DMA registers", 332 sc->sc_dev.dv_xname); 333 } 334 335 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 336 esc->sc_scsi_dma.nd_chaining_flag = 0; 337 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 338 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 339 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 340 esc->sc_scsi_dma.nd_cb_arg = sc; 341 nextdma_config(&esc->sc_scsi_dma); 342 nextdma_init(&esc->sc_scsi_dma); 343 344 { 345 int error; 346 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 347 sc->sc_maxxfer, 1, sc->sc_maxxfer, 348 0, BUS_DMA_ALLOCNOW, &esc->sc_dmamap)) != 0) { 349 panic("%s: can't create i/o DMA map, error = %d", 350 sc->sc_dev.dv_xname,error); 351 } 352 } 353 } 354 355 /* register interrupt stats */ 356 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 357 358 /* Do the common parts of attachment. */ 359 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 360 361 #if 0 362 /* Turn on target selection using the `dma' method */ 363 ncr53c9x_dmaselect = 1; 364 #else 365 ncr53c9x_dmaselect = 0; 366 #endif 367 368 esc->sc_slop_bgn_addr = 0; 369 esc->sc_slop_bgn_size = 0; 370 esc->sc_slop_end_addr = 0; 371 esc->sc_slop_end_size = 0; 372 esc->sc_datain = -1; 373 374 /* Establish interrupt channel */ 375 isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc, 376 NEXT_I_IPL(NEXT_I_SCSI), 0); 377 INTR_ENABLE(NEXT_I_SCSI); 378 } 379 380 /* 381 * Glue functions. 382 */ 383 384 u_char 385 esp_read_reg(sc, reg) 386 struct ncr53c9x_softc *sc; 387 int reg; 388 { 389 struct esp_softc *esc = (struct esp_softc *)sc; 390 391 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 392 } 393 394 void 395 esp_write_reg(sc, reg, val) 396 struct ncr53c9x_softc *sc; 397 int reg; 398 u_char val; 399 { 400 struct esp_softc *esc = (struct esp_softc *)sc; 401 402 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 403 } 404 405 int 406 esp_dma_isintr(sc) 407 struct ncr53c9x_softc *sc; 408 { 409 return (INTR_OCCURRED(NEXT_I_SCSI)); 410 } 411 412 void 413 esp_dma_reset(sc) 414 struct ncr53c9x_softc *sc; 415 { 416 struct esp_softc *esc = (struct esp_softc *)sc; 417 418 if (esc->sc_dmamap->dm_mapsize != 0) { 419 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap); 420 } 421 422 nextdma_reset(&esc->sc_scsi_dma); 423 424 esc->sc_slop_bgn_addr = 0; 425 esc->sc_slop_bgn_size = 0; 426 esc->sc_slop_end_addr = 0; 427 esc->sc_slop_end_size = 0; 428 esc->sc_datain = -1; 429 } 430 431 int 432 esp_dma_intr(sc) 433 struct ncr53c9x_softc *sc; 434 { 435 /* Do nothing here, since the DMA has real interrupts 436 * of its own. 437 */ 438 return (0); 439 } 440 441 int 442 esp_dma_setup(sc, addr, len, datain, dmasize) 443 struct ncr53c9x_softc *sc; 444 caddr_t *addr; 445 size_t *len; 446 int datain; 447 size_t *dmasize; 448 { 449 struct esp_softc *esc = (struct esp_softc *)sc; 450 451 #ifdef DIAGNOSTIC 452 if ((esc->sc_datain != -1) || 453 (esc->sc_dmamap->dm_mapsize != 0)) { 454 panic("%s: map already loaded in esp_dma_setup\n" 455 "\tdatain = %d\n\tmapsize=%d", 456 sc->sc_dev.dv_xname,esc->sc_datain,esc->sc_dmamap->dm_mapsize); 457 } 458 #endif 459 460 /* Deal with DMA alignment issues, by stuffing the FIFO. 461 * This assumes that if bus_dmamap_load is given an aligned 462 * buffer, then it will generate aligned hardware addresses 463 * to give to the device. Perhaps that is not a good assumption, 464 * but it is probably true. [dbj (at) netbsd.org:19980719.0135EDT] 465 */ 466 { 467 int slop_bgn_size; /* # bytes to be fifo'd at beginning */ 468 int slop_end_size; /* # bytes to be fifo'd at end */ 469 470 { 471 u_long bgn = (u_long)(*addr); 472 u_long end = (u_long)(*addr+*dmasize); 473 474 slop_bgn_size = DMA_BEGINALIGNMENT-(bgn % DMA_BEGINALIGNMENT); 475 slop_end_size = end % DMA_ENDALIGNMENT; 476 } 477 478 /* Check to make sure we haven't counted the slop twice 479 * as would happen for a very short dma buffer */ 480 if (slop_bgn_size+slop_end_size > *dmasize) { 481 #if defined(DIAGNOSTIC) 482 if ((slop_bgn_size != *dmasize) || 483 (slop_end_size != *dmasize)) { 484 printf("slop_bgn_size %d",slop_bgn_size); 485 printf("slop_end_size %d",slop_bgn_size); 486 panic("%s: confused alignment calculation\n" 487 "\tslop_bgn_size %d\n\tslop_end_size %d\n\tdmasize %d", 488 sc->sc_dev.dv_xname,slop_bgn_size,slop_end_size,*dmasize); 489 } 490 #endif 491 slop_end_size = 0; 492 } 493 494 if (slop_bgn_size+slop_end_size < *dmasize) { 495 int error; 496 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 497 esc->sc_dmamap, 498 *addr+slop_bgn_size, 499 *dmasize-(slop_bgn_size+slop_end_size), 500 NULL, BUS_DMA_NOWAIT); 501 if (error) { 502 panic("%s: can't load dma map. error = %d",error); 503 } 504 505 } else { 506 /* If there's no DMA, then coalesce the fifo buffers */ 507 slop_bgn_size += slop_end_size; 508 slop_end_size = 0; 509 } 510 511 esc->sc_slop_bgn_addr = *addr; 512 esc->sc_slop_bgn_size = slop_bgn_size; 513 esc->sc_slop_end_addr = (*addr+*dmasize)-slop_end_size; 514 esc->sc_slop_end_size = slop_end_size; 515 } 516 517 esc->sc_datain = datain; 518 519 return (0); 520 } 521 522 void 523 esp_dma_go(sc) 524 struct ncr53c9x_softc *sc; 525 { 526 struct esp_softc *esc = (struct esp_softc *)sc; 527 528 /* @@@ Stuff the bgn slop into fifo */ 529 530 if (esc->sc_dmamap->dm_mapsize != 0) { 531 nextdma_start(&esc->sc_scsi_dma, 532 (esc->sc_datain ? DMACSR_READ : DMACSR_WRITE)); 533 } else { 534 #if defined(DIAGNOSTIC) 535 /* @@@ verify that end slop is 0, since the shutdown 536 * callback will not be called. 537 */ 538 #endif 539 esc->sc_slop_bgn_addr = 0; 540 esc->sc_slop_bgn_size = 0; 541 esc->sc_slop_end_addr = 0; 542 esc->sc_slop_end_size = 0; 543 } 544 } 545 546 void 547 esp_dma_stop(sc) 548 struct ncr53c9x_softc *sc; 549 { 550 panic("Not yet implemented"); 551 } 552 553 int 554 esp_dma_isactive(sc) 555 struct ncr53c9x_softc *sc; 556 { 557 struct esp_softc *esc = (struct esp_softc *)sc; 558 return( !nextdma_finished(&esc->sc_scsi_dma)); 559 } 560 561 /****************************************************************/ 562 563 /* Internal dma callback routines */ 564 bus_dmamap_t 565 esp_dmacb_continue(arg) 566 void *arg; 567 { 568 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 569 struct esp_softc *esc = (struct esp_softc *)sc; 570 571 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap, 572 0, esc->sc_dmamap->dm_mapsize, 573 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 574 575 #ifdef DIAGNOSTIC 576 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 577 panic("%s: map not loaded in dma continue callback, datain = %d", 578 sc->sc_dev.dv_xname,esc->sc_datain); 579 } 580 #endif 581 582 return(esc->sc_dmamap); 583 } 584 585 void 586 esp_dmacb_completed(map, arg) 587 bus_dmamap_t map; 588 void *arg; 589 { 590 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 591 struct esp_softc *esc = (struct esp_softc *)sc; 592 593 #ifdef DIAGNOSTIC 594 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 595 panic("%s: map not loaded in dma completed callback, datain = %d", 596 sc->sc_dev.dv_xname,esc->sc_datain); 597 } 598 if (map != esc->sc_dmamap) { 599 panic("%s: unexpected tx completed map", sc->sc_dev.dv_xname); 600 } 601 #endif 602 603 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap, 604 0, esc->sc_dmamap->dm_mapsize, 605 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 606 } 607 608 void 609 esp_dmacb_shutdown(arg) 610 void *arg; 611 { 612 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 613 struct esp_softc *esc = (struct esp_softc *)sc; 614 615 #ifdef DIAGNOSTIC 616 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 617 panic("%s: map not loaded in dma shutdown callback, datain = %d", 618 sc->sc_dev.dv_xname,esc->sc_datain); 619 } 620 #endif 621 622 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap); 623 624 /* @@@ Stuff the end slop into fifo */ 625 626 esc->sc_datain = -1; 627 esc->sc_slop_bgn_addr = 0; 628 esc->sc_slop_bgn_size = 0; 629 esc->sc_slop_end_addr = 0; 630 esc->sc_slop_end_size = 0; 631 } 632
Indexes created Wed Sep 24 05:09:52 GMT 2025