esp.c revision 1.37
1 /* $NetBSD: esp.c,v 1.37 2002/07/11 16:03:10 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Grabbed from the sparc port at revision 1.73 for the NeXT. 81 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 82 */ 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/device.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 #include <sys/user.h> 94 #include <sys/queue.h> 95 96 #include <dev/scsipi/scsi_all.h> 97 #include <dev/scsipi/scsipi_all.h> 98 #include <dev/scsipi/scsiconf.h> 99 #include <dev/scsipi/scsi_message.h> 100 101 #include <machine/bus.h> 102 #include <machine/autoconf.h> 103 #include <machine/cpu.h> 104 105 #include <dev/ic/ncr53c9xreg.h> 106 #include <dev/ic/ncr53c9xvar.h> 107 108 #include <next68k/next68k/isr.h> 109 110 #include <next68k/dev/nextdmareg.h> 111 #include <next68k/dev/nextdmavar.h> 112 113 #include "espreg.h" 114 #include "espvar.h" 115 116 #ifdef DEBUG 117 #define ESP_DEBUG 118 #endif 119 120 #ifdef ESP_DEBUG 121 int esp_debug = 0; 122 #define DPRINTF(x) if (esp_debug) printf x; 123 int esplogshow = 0; 124 char esplog[8192+100]; 125 char *esplogp = esplog; 126 #define ESPLOGIF 10 && (esplogp < (esplog + 8192)) 127 #else 128 #define DPRINTF(x) 129 #endif 130 #define PRINTF(x) printf x; 131 132 133 void espattach_intio __P((struct device *, struct device *, void *)); 134 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 135 136 /* DMA callbacks */ 137 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 138 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 139 void esp_dmacb_shutdown __P((void *arg)); 140 141 #ifdef ESP_DEBUG 142 char esp_dma_dump[5*1024] = ""; 143 struct ncr53c9x_softc *esp_debug_sc = 0; 144 void esp_dma_store __P((struct ncr53c9x_softc *sc)); 145 void esp_dma_print __P((struct ncr53c9x_softc *sc)); 146 int esp_dma_nest = 0; 147 #endif 148 149 150 /* Linkup to the rest of the kernel */ 151 struct cfattach esp_ca = { 152 sizeof(struct esp_softc), espmatch_intio, espattach_intio 153 }; 154 155 /* 156 * Functions and the switch for the MI code. 157 */ 158 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 159 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 160 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 161 void esp_dma_reset __P((struct ncr53c9x_softc *)); 162 int esp_dma_intr __P((struct ncr53c9x_softc *)); 163 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 164 size_t *, int, size_t *)); 165 void esp_dma_go __P((struct ncr53c9x_softc *)); 166 void esp_dma_stop __P((struct ncr53c9x_softc *)); 167 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 168 169 struct ncr53c9x_glue esp_glue = { 170 esp_read_reg, 171 esp_write_reg, 172 esp_dma_isintr, 173 esp_dma_reset, 174 esp_dma_intr, 175 esp_dma_setup, 176 esp_dma_go, 177 esp_dma_stop, 178 esp_dma_isactive, 179 NULL, /* gl_clear_latched_intr */ 180 }; 181 182 #ifdef ESP_DEBUG 183 #define XCHR(x) "0123456789abcdef"[(x) & 0xf] 184 static void 185 esp_hex_dump(unsigned char *pkt, size_t len) 186 { 187 size_t i, j; 188 189 printf("00000000 "); 190 for(i=0; i<len; i++) { 191 printf("%c%c ", XCHR(pkt[i]>>4), XCHR(pkt[i])); 192 if ((i+1) % 16 == 8) { 193 printf(" "); 194 } 195 if ((i+1) % 16 == 0) { 196 printf(" %c", '|'); 197 for(j=0; j<16; j++) { 198 printf("%c", pkt[i-15+j]>=32 && pkt[i-15+j]<127?pkt[i-15+j]:'.'); 199 } 200 printf("%c\n%c%c%c%c%c%c%c%c ", '|', 201 XCHR((i+1)>>28),XCHR((i+1)>>24),XCHR((i+1)>>20),XCHR((i+1)>>16), 202 XCHR((i+1)>>12), XCHR((i+1)>>8), XCHR((i+1)>>4), XCHR(i+1)); 203 } 204 } 205 printf("\n"); 206 } 207 #endif 208 209 int 210 espmatch_intio(parent, cf, aux) 211 struct device *parent; 212 struct cfdata *cf; 213 void *aux; 214 { 215 /* should probably probe here */ 216 /* Should also probably set up data from config */ 217 218 return(1); 219 } 220 221 void 222 espattach_intio(parent, self, aux) 223 struct device *parent, *self; 224 void *aux; 225 { 226 struct esp_softc *esc = (void *)self; 227 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 228 229 #ifdef ESP_DEBUG 230 esp_debug_sc = sc; 231 #endif 232 233 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 234 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 235 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 236 panic("\n%s: can't map ncr53c90 registers", 237 sc->sc_dev.dv_xname); 238 } 239 240 sc->sc_id = 7; 241 sc->sc_freq = 20; /* Mhz */ 242 243 /* 244 * Set up glue for MI code early; we use some of it here. 245 */ 246 sc->sc_glue = &esp_glue; 247 248 /* 249 * XXX More of this should be in ncr53c9x_attach(), but 250 * XXX should we really poke around the chip that much in 251 * XXX the MI code? Think about this more... 252 */ 253 254 /* 255 * It is necessary to try to load the 2nd config register here, 256 * to find out what rev the esp chip is, else the ncr53c9x_reset 257 * will not set up the defaults correctly. 258 */ 259 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 260 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 261 sc->sc_cfg3 = NCRCFG3_CDB; 262 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 263 264 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 265 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 266 sc->sc_rev = NCR_VARIANT_ESP100; 267 } else { 268 sc->sc_cfg2 = NCRCFG2_SCSI2; 269 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 270 sc->sc_cfg3 = 0; 271 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 272 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 273 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 274 if (NCR_READ_REG(sc, NCR_CFG3) != 275 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 276 sc->sc_rev = NCR_VARIANT_ESP100A; 277 } else { 278 /* NCRCFG2_FE enables > 64K transfers */ 279 sc->sc_cfg2 |= NCRCFG2_FE; 280 sc->sc_cfg3 = 0; 281 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 282 sc->sc_rev = NCR_VARIANT_ESP200; 283 } 284 } 285 286 /* 287 * XXX minsync and maxxfer _should_ be set up in MI code, 288 * XXX but it appears to have some dependency on what sort 289 * XXX of DMA we're hooked up to, etc. 290 */ 291 292 /* 293 * This is the value used to start sync negotiations 294 * Note that the NCR register "SYNCTP" is programmed 295 * in "clocks per byte", and has a minimum value of 4. 296 * The SCSI period used in negotiation is one-fourth 297 * of the time (in nanoseconds) needed to transfer one byte. 298 * Since the chip's clock is given in MHz, we have the following 299 * formula: 4 * period = (1000 / freq) * 4 300 */ 301 sc->sc_minsync = 1000 / sc->sc_freq; 302 303 /* 304 * Alas, we must now modify the value a bit, because it's 305 * only valid when can switch on FASTCLK and FASTSCSI bits 306 * in config register 3... 307 */ 308 switch (sc->sc_rev) { 309 case NCR_VARIANT_ESP100: 310 sc->sc_maxxfer = 64 * 1024; 311 sc->sc_minsync = 0; /* No synch on old chip? */ 312 break; 313 314 case NCR_VARIANT_ESP100A: 315 sc->sc_maxxfer = 64 * 1024; 316 /* Min clocks/byte is 5 */ 317 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 318 break; 319 320 case NCR_VARIANT_ESP200: 321 sc->sc_maxxfer = 16 * 1024 * 1024; 322 /* XXX - do actually set FAST* bits */ 323 break; 324 } 325 326 /* @@@ Some ESP_DCTL bits probably need setting */ 327 NCR_WRITE_REG(sc, ESP_DCTL, 328 ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 329 DELAY(10); 330 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 331 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_16MHZ | ESPDCTL_INTENB); 332 DELAY(10); 333 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 334 335 /* Set up SCSI DMA */ 336 { 337 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 338 339 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 340 DD_SIZE,0, &esc->sc_scsi_dma.nd_bsh)) { 341 panic("\n%s: can't map scsi DMA registers", 342 sc->sc_dev.dv_xname); 343 } 344 345 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 346 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 347 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 348 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 349 esc->sc_scsi_dma.nd_cb_arg = sc; 350 nextdma_config(&esc->sc_scsi_dma); 351 nextdma_init(&esc->sc_scsi_dma); 352 353 #if 0 354 /* Turn on target selection using the `dma' method */ 355 sc->sc_features |= NCR_F_DMASELECT; 356 #endif 357 358 esc->sc_datain = -1; 359 esc->sc_dmaaddr = 0; 360 esc->sc_dmalen = 0; 361 esc->sc_dmasize = 0; 362 363 esc->sc_loaded = 0; 364 365 esc->sc_begin = 0; 366 esc->sc_begin_size = 0; 367 368 { 369 int error; 370 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 371 sc->sc_maxxfer, sc->sc_maxxfer/NBPG+1, sc->sc_maxxfer, 372 0, BUS_DMA_ALLOCNOW, &esc->sc_main_dmamap)) != 0) { 373 panic("%s: can't create main i/o DMA map, error = %d", 374 sc->sc_dev.dv_xname,error); 375 } 376 } 377 esc->sc_main = 0; 378 esc->sc_main_size = 0; 379 380 { 381 int error; 382 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 383 ESP_DMA_TAILBUFSIZE, 384 1, ESP_DMA_TAILBUFSIZE, 385 0, BUS_DMA_ALLOCNOW, &esc->sc_tail_dmamap)) != 0) { 386 panic("%s: can't create tail i/o DMA map, error = %d", 387 sc->sc_dev.dv_xname,error); 388 } 389 } 390 esc->sc_tail = 0; 391 esc->sc_tail_size = 0; 392 393 } 394 395 /* Establish interrupt channel */ 396 isrlink_autovec(ncr53c9x_intr, sc, NEXT_I_IPL(NEXT_I_SCSI), 0); 397 INTR_ENABLE(NEXT_I_SCSI); 398 399 /* register interrupt stats */ 400 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 401 sc->sc_dev.dv_xname, "intr"); 402 403 /* Do the common parts of attachment. */ 404 sc->sc_adapter.adapt_minphys = minphys; 405 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 406 ncr53c9x_attach(sc); 407 } 408 409 /* 410 * Glue functions. 411 */ 412 413 u_char 414 esp_read_reg(sc, reg) 415 struct ncr53c9x_softc *sc; 416 int reg; 417 { 418 struct esp_softc *esc = (struct esp_softc *)sc; 419 420 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 421 } 422 423 void 424 esp_write_reg(sc, reg, val) 425 struct ncr53c9x_softc *sc; 426 int reg; 427 u_char val; 428 { 429 struct esp_softc *esc = (struct esp_softc *)sc; 430 431 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 432 } 433 434 volatile u_int32_t save1; 435 436 #define xADDR 0x0211a000 437 int doze __P((volatile int)); 438 int 439 doze(c) 440 volatile int c; 441 { 442 /* static int tmp1; */ 443 u_int32_t tmp1; 444 volatile u_int8_t tmp2; 445 volatile u_int8_t *reg = (volatile u_int8_t *)IIOV(xADDR); 446 if (c > 244) return (0); 447 if (c == 0) return (0); 448 /* ((*(volatile u_long *)IIOV(NEXT_P_INTRMASK))&=(~NEXT_I_BIT(x))) */ 449 (*reg) = 0; 450 (*reg) = 0; 451 do { 452 save1 = (*reg); 453 tmp2 = *(reg + 3); 454 tmp1 = tmp2; 455 } while (tmp1 <= c); 456 return (0); 457 } 458 459 int 460 esp_dma_isintr(sc) 461 struct ncr53c9x_softc *sc; 462 { 463 struct esp_softc *esc = (struct esp_softc *)sc; 464 if (INTR_OCCURRED(NEXT_I_SCSI)) { 465 if (ESPLOGIF) *esplogp++ = 'i'; 466 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_16MHZ | ESPDCTL_INTENB | (esc->sc_datain ? ESPDCTL_DMARD : 0)); 467 return (1); 468 } else { 469 return (0); 470 } 471 } 472 473 int 474 esp_dma_intr(sc) 475 struct ncr53c9x_softc *sc; 476 { 477 struct esp_softc *esc = (struct esp_softc *)sc; 478 479 int r = (INTR_OCCURRED(NEXT_I_SCSI)); 480 int flushcount; 481 r = 1; 482 483 if (ESPLOGIF) *esplogp++ = 'I'; 484 if (r) { 485 /* printf ("esp_dma_isintr start\n"); */ 486 { 487 int s = spldma(); 488 void *ndmap = esc->sc_scsi_dma._nd_map; 489 int ndidx = esc->sc_scsi_dma._nd_idx; 490 splx(s); 491 492 flushcount = 0; 493 494 #ifdef ESP_DEBUG 495 /* esp_dma_nest++; */ 496 497 if (esp_debug) { 498 char sbuf[256]; 499 500 bitmask_snprintf((*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)), 501 NEXT_INTR_BITS, sbuf, sizeof(sbuf)); 502 printf("esp_dma_isintr = 0x%s\n", sbuf); 503 } 504 #endif 505 506 while (!nextdma_finished(&esc->sc_scsi_dma)) { /* esp_dma_isactive(sc)) { */ 507 if (ESPLOGIF) *esplogp++ = 'w'; 508 if (ESPLOGIF) { 509 sprintf (esplogp, "f%dm%dl%dw", NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF, 510 NCR_READ_REG((sc), NCR_TCM), NCR_READ_REG((sc), NCR_TCL)); 511 esplogp += strlen (esplogp); 512 } 513 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) 514 flushcount=5; 515 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | 516 (esc->sc_datain ? ESPDCTL_DMARD : 0)); 517 518 s = spldma(); 519 while (ndmap == esc->sc_scsi_dma._nd_map && ndidx == esc->sc_scsi_dma._nd_idx && 520 !(bus_space_read_4(esc->sc_scsi_dma.nd_bst, esc->sc_scsi_dma.nd_bsh, DD_CSR) 521 & 0x08000000) && 522 ++flushcount < 5) { 523 splx(s); 524 if (flushcount < 10) if (ESPLOGIF) *esplogp++ = 'F'; 525 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_FLUSH | 526 ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | 527 (esc->sc_datain ? ESPDCTL_DMARD : 0)); 528 doze(0x32); 529 NCR_WRITE_REG(sc, ESP_DCTL, 530 ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | 531 (esc->sc_datain ? ESPDCTL_DMARD : 0)); 532 doze(0x32); 533 s = spldma(); 534 } 535 if (ESPLOGIF) *esplogp++ = '0' + flushcount; 536 if (flushcount > 4) { 537 int next; 538 int onext = 0; 539 splx(s); 540 DPRINTF (("DMA reset\n")); 541 while (((next = bus_space_read_4(esc->sc_scsi_dma.nd_bst, esc->sc_scsi_dma.nd_bsh, DD_NEXT)) != 542 (bus_space_read_4(esc->sc_scsi_dma.nd_bst, esc->sc_scsi_dma.nd_bsh, DD_LIMIT) & 0x7FFFFFFF)) && 543 onext != next) { 544 onext = next; 545 DELAY(50); 546 } 547 if (ESPLOGIF) *esplogp++ = 'R'; 548 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_16MHZ | ESPDCTL_INTENB); 549 if (ESPLOGIF) { 550 sprintf (esplogp, "ff:%d tcm:%d tcl:%d ", 551 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF, 552 NCR_READ_REG((sc), NCR_TCM), NCR_READ_REG((sc), NCR_TCL)); 553 esplogp += strlen (esplogp); 554 } 555 s = spldma(); 556 nextdma_reset (&esc->sc_scsi_dma); 557 splx(s); 558 goto out; 559 } 560 splx(s); 561 562 #ifdef DIAGNOSTIC 563 if (flushcount > 4) { 564 if (ESPLOGIF) *esplogp++ = '+'; 565 printf("%s: unexpected flushcount %d on %s\n",sc->sc_dev.dv_xname, 566 flushcount, esc->sc_datain ? "read" : "write"); 567 } 568 #endif 569 570 if (!nextdma_finished(&esc->sc_scsi_dma)) { /* esp_dma_isactive(sc)) { */ 571 if (ESPLOGIF) *esplogp++ = '1'; 572 } 573 flushcount = 0; 574 s = spldma(); 575 ndmap = esc->sc_scsi_dma._nd_map; 576 ndidx = esc->sc_scsi_dma._nd_idx; 577 splx(s); 578 579 goto loop; 580 581 loop: 582 } 583 goto out; 584 out: 585 586 #ifdef ESP_DEBUG 587 /* esp_dma_nest--; */ 588 #endif 589 590 } 591 592 doze (0x32); 593 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_16MHZ | ESPDCTL_INTENB | (esc->sc_datain ? ESPDCTL_DMARD : 0)); 594 if (ESPLOGIF) *esplogp++ = 'b'; 595 596 while (esc->sc_datain != -1) DELAY(50); 597 598 if (esc->sc_dmaaddr) { 599 bus_size_t xfer_len = 0; 600 int resid; 601 602 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_16MHZ | ESPDCTL_INTENB); 603 if (esc->sc_scsi_dma.dm_xfer_exception == 0) { 604 resid = NCR_READ_REG((sc), NCR_TCL) + (NCR_READ_REG((sc), NCR_TCM) << 8); 605 if (resid) { 606 resid += (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 607 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) 608 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) != 16 || NCR_READ_REG((sc), NCR_TCL) != 240) 609 esplogshow++; 610 } 611 xfer_len = esc->sc_dmasize - resid; 612 } else { 613 /*static*/ void ncr53c9x_abort(struct ncr53c9x_softc *, struct ncr53c9x_ecb *); 614 #define ncr53c9x_sched_msgout(m) \ 615 do { \ 616 NCR_MISC(("ncr53c9x_sched_msgout %x %d", m, __LINE__)); \ 617 NCRCMD(sc, NCRCMD_SETATN); \ 618 sc->sc_flags |= NCR_ATN; \ 619 sc->sc_msgpriq |= (m); \ 620 } while (0) 621 int i; 622 xfer_len = esc->sc_scsi_dma.dm_xfer_len; 623 resid = 0; 624 printf ("X\n"); 625 for (i = 0; i < 16; i++) { 626 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_FLUSH | 627 ESPDCTL_16MHZ | ESPDCTL_INTENB | 628 (esc->sc_datain ? ESPDCTL_DMARD : 0)); 629 NCR_WRITE_REG(sc, ESP_DCTL, 630 ESPDCTL_16MHZ | ESPDCTL_INTENB | 631 (esc->sc_datain ? ESPDCTL_DMARD : 0)); 632 } 633 #if 0 634 printf ("ff:%02x tcm:%d tcl:%d esp_dstat:%02x stat:%02x step: %02x intr:%02x new stat:%02X\n", 635 NCR_READ_REG(sc, NCR_FFLAG), 636 NCR_READ_REG((sc), NCR_TCM), NCR_READ_REG((sc), NCR_TCL), 637 NCR_READ_REG(sc, ESP_DSTAT), 638 sc->sc_espstat, sc->sc_espstep, 639 sc->sc_espintr, NCR_READ_REG(sc, NCR_STAT)); 640 printf ("sc->sc_state: %x sc->sc_phase: %x sc->sc_espstep:%x sc->sc_prevphase:%x sc->sc_flags:%x\n", 641 sc->sc_state, sc->sc_phase, sc->sc_espstep, sc->sc_prevphase, sc->sc_flags); 642 #endif 643 /* sc->sc_flags &= ~NCR_ICCS; */ 644 sc->sc_nexus->flags |= ECB_ABORT; 645 if (sc->sc_phase == MESSAGE_IN_PHASE) { 646 /* ncr53c9x_sched_msgout(SEND_ABORT); */ 647 ncr53c9x_abort(sc, sc->sc_nexus); 648 } else if (sc->sc_phase != STATUS_PHASE) { 649 printf ("ATTENTION!!! not message/status phase: %d\n", sc->sc_phase); 650 } 651 } 652 653 if (ESPLOGIF) { 654 sprintf (esplogp, "f%dm%dl%ds%dx%dr%dS", NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF, NCR_READ_REG((sc), NCR_TCM), 655 NCR_READ_REG((sc), NCR_TCL), esc->sc_dmasize, (int)xfer_len, resid); 656 esplogp += strlen (esplogp); 657 } 658 659 *(esc->sc_dmaaddr) += xfer_len; 660 *(esc->sc_dmalen) -= xfer_len; 661 esc->sc_dmaaddr = 0; 662 esc->sc_dmalen = 0; 663 esc->sc_dmasize = 0; 664 } 665 666 if (ESPLOGIF) *esplogp++ = 'B'; 667 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT) | (sc->sc_espstat & NCRSTAT_INT); 668 669 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 670 /* printf ("esp_dma_isintr DONE\n"); */ 671 672 } 673 674 return (r); 675 } 676 677 void 678 esp_dma_reset(sc) 679 struct ncr53c9x_softc *sc; 680 { 681 struct esp_softc *esc = (struct esp_softc *)sc; 682 683 DPRINTF(("esp dma reset\n")); 684 685 #ifdef ESP_DEBUG 686 if (esp_debug) { 687 char sbuf[256]; 688 689 bitmask_snprintf((*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)), 690 NEXT_INTR_BITS, sbuf, sizeof(sbuf)); 691 printf(" *intrstat = 0x%s\n", sbuf); 692 693 bitmask_snprintf((*(volatile u_long *)IIOV(NEXT_P_INTRMASK)), 694 NEXT_INTR_BITS, sbuf, sizeof(sbuf)); 695 printf(" *intrmask = 0x%s\n", sbuf); 696 } 697 #endif 698 699 /* Clear the DMAMOD bit in the DCTL register: */ 700 NCR_WRITE_REG(sc, ESP_DCTL, 701 ESPDCTL_16MHZ | ESPDCTL_INTENB); 702 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 703 704 nextdma_reset(&esc->sc_scsi_dma); 705 nextdma_init(&esc->sc_scsi_dma); 706 707 esc->sc_datain = -1; 708 esc->sc_dmaaddr = 0; 709 esc->sc_dmalen = 0; 710 esc->sc_dmasize = 0; 711 712 esc->sc_loaded = 0; 713 714 esc->sc_begin = 0; 715 esc->sc_begin_size = 0; 716 717 if (esc->sc_main_dmamap->dm_mapsize) { 718 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 719 } 720 esc->sc_main = 0; 721 esc->sc_main_size = 0; 722 723 if (esc->sc_tail_dmamap->dm_mapsize) { 724 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 725 } 726 esc->sc_tail = 0; 727 esc->sc_tail_size = 0; 728 } 729 730 /* it appears that: 731 * addr and len arguments to this need to be kept up to date 732 * with the status of the transfter. 733 * the dmasize of this is the actual length of the transfer 734 * request, which is guaranteed to be less than maxxfer. 735 * (len may be > maxxfer) 736 */ 737 738 int 739 esp_dma_setup(sc, addr, len, datain, dmasize) 740 struct ncr53c9x_softc *sc; 741 caddr_t *addr; 742 size_t *len; 743 int datain; 744 size_t *dmasize; 745 { 746 struct esp_softc *esc = (struct esp_softc *)sc; 747 748 if (ESPLOGIF) *esplogp++ = 'h'; 749 #ifdef DIAGNOSTIC 750 #ifdef ESP_DEBUG 751 /* if this is a read DMA, pre-fill the buffer with 0xdeadbeef 752 * to identify bogus reads 753 */ 754 if (datain) { 755 int *v = (int *)(*addr); 756 int i; 757 for(i=0;i<((*len)/4);i++) v[i] = 0xdeadbeef; 758 v = (int *)(&(esc->sc_tailbuf[0])); 759 for(i=0;i<((sizeof(esc->sc_tailbuf)/4));i++) v[i] = 0xdeafbeef; 760 } else { 761 int *v; 762 int i; 763 v = (int *)(&(esc->sc_tailbuf[0])); 764 for(i=0;i<((sizeof(esc->sc_tailbuf)/4));i++) v[i] = 0xfeeb1eed; 765 } 766 #endif 767 #endif 768 769 DPRINTF(("esp_dma_setup(%p,0x%08x,0x%08x)\n",*addr,*len,*dmasize)); 770 771 #if 0 772 #ifdef DIAGNOSTIC /* @@@ this is ok sometimes. verify that we handle it ok 773 * and then remove this check 774 */ 775 if (*len != *dmasize) { 776 panic("esp dmalen 0x%lx != size 0x%lx",*len,*dmasize); 777 } 778 #endif 779 #endif 780 781 #ifdef DIAGNOSTIC 782 if ((esc->sc_datain != -1) || 783 (esc->sc_main_dmamap->dm_mapsize != 0) || 784 (esc->sc_tail_dmamap->dm_mapsize != 0) || 785 (esc->sc_dmasize != 0)) { 786 panic("%s: map already loaded in esp_dma_setup\n" 787 "\tdatain = %d\n\tmain_mapsize=%ld\n\tail_mapsize=%ld\n\tdmasize = %d", 788 sc->sc_dev.dv_xname, esc->sc_datain, 789 esc->sc_main_dmamap->dm_mapsize, 790 esc->sc_tail_dmamap->dm_mapsize, 791 esc->sc_dmasize); 792 } 793 #endif 794 795 /* we are sometimes asked to dma zero bytes, that's easy */ 796 if (*dmasize <= 0) { 797 return(0); 798 } 799 800 if (*dmasize > ESP_MAX_DMASIZE) 801 *dmasize = ESP_MAX_DMASIZE; 802 803 /* Save these in case we have to abort DMA */ 804 esc->sc_datain = datain; 805 esc->sc_dmaaddr = addr; 806 esc->sc_dmalen = len; 807 esc->sc_dmasize = *dmasize; 808 809 esc->sc_loaded = 0; 810 811 #define DMA_SCSI_ALIGNMENT 16 812 #define DMA_SCSI_ALIGN(type, addr) \ 813 ((type)(((unsigned)(addr)+DMA_SCSI_ALIGNMENT-1) \ 814 &~(DMA_SCSI_ALIGNMENT-1))) 815 #define DMA_SCSI_ALIGNED(addr) \ 816 (((unsigned)(addr)&(DMA_SCSI_ALIGNMENT-1))==0) 817 818 { 819 size_t slop_bgn_size; /* # bytes to be fifo'd at beginning */ 820 size_t slop_end_size; /* # bytes to be transferred in tail buffer */ 821 822 { 823 u_long bgn = (u_long)(*esc->sc_dmaaddr); 824 u_long end = (u_long)(*esc->sc_dmaaddr+esc->sc_dmasize); 825 826 slop_bgn_size = DMA_SCSI_ALIGNMENT-(bgn % DMA_SCSI_ALIGNMENT); 827 if (slop_bgn_size == DMA_SCSI_ALIGNMENT) slop_bgn_size = 0; 828 slop_end_size = (end % DMA_ENDALIGNMENT); 829 } 830 831 /* Force a minimum slop end size. This ensures that write 832 * requests will overrun, as required to get completion interrupts. 833 * In addition, since the tail buffer is guaranteed to be mapped 834 * in a single dma segment, the overrun won't accidentally 835 * end up in its own segment. 836 */ 837 if (!esc->sc_datain) { 838 #if 0 839 slop_end_size += ESP_DMA_MAXTAIL; 840 #else 841 slop_end_size += 0x10; 842 #endif 843 } 844 845 /* Check to make sure we haven't counted extra slop 846 * as would happen for a very short dma buffer, also 847 * for short buffers, just stuff the entire thing in the tail 848 */ 849 if ((slop_bgn_size+slop_end_size >= esc->sc_dmasize) 850 #if 0 851 || (esc->sc_dmasize <= ESP_DMA_MAXTAIL) 852 #endif 853 ) 854 { 855 slop_bgn_size = 0; 856 slop_end_size = esc->sc_dmasize; 857 } 858 859 /* initialize the fifo buffer */ 860 if (slop_bgn_size) { 861 esc->sc_begin = *esc->sc_dmaaddr; 862 esc->sc_begin_size = slop_bgn_size; 863 } else { 864 esc->sc_begin = 0; 865 esc->sc_begin_size = 0; 866 } 867 868 #if 01 869 /* Load the normal DMA map */ 870 { 871 esc->sc_main = *esc->sc_dmaaddr+slop_bgn_size; 872 esc->sc_main_size = (esc->sc_dmasize)-(slop_end_size+slop_bgn_size); 873 874 if (esc->sc_main_size) { 875 int error; 876 877 if (!esc->sc_datain || DMA_ENDALIGNED(esc->sc_main_size + slop_end_size)) { 878 KASSERT(DMA_SCSI_ALIGNMENT == DMA_ENDALIGNMENT); 879 KASSERT(DMA_BEGINALIGNMENT == DMA_ENDALIGNMENT); 880 esc->sc_main_size += slop_end_size; 881 slop_end_size = 0; 882 if (!esc->sc_datain) { 883 esc->sc_main_size = DMA_ENDALIGN(caddr_t,esc->sc_main+esc->sc_main_size)-esc->sc_main; 884 } 885 } 886 887 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 888 esc->sc_main_dmamap, 889 esc->sc_main, esc->sc_main_size, 890 NULL, BUS_DMA_NOWAIT); 891 if (error) { 892 #ifdef ESP_DEBUG 893 printf("%s: esc->sc_main_dmamap->_dm_size = %ld\n", 894 sc->sc_dev.dv_xname,esc->sc_main_dmamap->_dm_size); 895 printf("%s: esc->sc_main_dmamap->_dm_segcnt = %d\n", 896 sc->sc_dev.dv_xname,esc->sc_main_dmamap->_dm_segcnt); 897 printf("%s: esc->sc_main_dmamap->_dm_maxsegsz = %ld\n", 898 sc->sc_dev.dv_xname,esc->sc_main_dmamap->_dm_maxsegsz); 899 printf("%s: esc->sc_main_dmamap->_dm_boundary = %ld\n", 900 sc->sc_dev.dv_xname,esc->sc_main_dmamap->_dm_boundary); 901 esp_dma_print(sc); 902 #endif 903 panic("%s: can't load main dma map. error = %d, addr=%p, size=0x%08x", 904 sc->sc_dev.dv_xname, error,esc->sc_main,esc->sc_main_size); 905 } 906 if (!esc->sc_datain) { /* patch the dma map for write overrun */ 907 esc->sc_main_dmamap->dm_mapsize += ESP_DMA_OVERRUN; 908 esc->sc_main_dmamap->dm_segs[esc->sc_main_dmamap->dm_nsegs - 1].ds_len += 909 ESP_DMA_OVERRUN; 910 } 911 #if 0 912 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 913 0, esc->sc_main_dmamap->dm_mapsize, 914 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 915 esc->sc_main_dmamap->dm_xfer_len = 0; 916 #endif 917 } else { 918 esc->sc_main = 0; 919 } 920 } 921 922 /* Load the tail DMA map */ 923 if (slop_end_size) { 924 esc->sc_tail = DMA_ENDALIGN(caddr_t,esc->sc_tailbuf+slop_end_size)-slop_end_size; 925 /* If the beginning of the tail is not correctly aligned, 926 * we have no choice but to align the start, which might then unalign the end. 927 */ 928 esc->sc_tail = DMA_SCSI_ALIGN(caddr_t,esc->sc_tail); 929 /* So therefore, we change the tail size to be end aligned again. */ 930 esc->sc_tail_size = DMA_ENDALIGN(caddr_t,esc->sc_tail+slop_end_size)-esc->sc_tail; 931 932 /* @@@ next dma overrun lossage */ 933 if (!esc->sc_datain) { 934 esc->sc_tail_size += ESP_DMA_OVERRUN; 935 } 936 937 { 938 int error; 939 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 940 esc->sc_tail_dmamap, 941 esc->sc_tail, esc->sc_tail_size, 942 NULL, BUS_DMA_NOWAIT); 943 if (error) { 944 panic("%s: can't load tail dma map. error = %d, addr=%p, size=0x%08x", 945 sc->sc_dev.dv_xname, error,esc->sc_tail,esc->sc_tail_size); 946 } 947 #if 0 948 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 949 0, esc->sc_tail_dmamap->dm_mapsize, 950 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 951 esc->sc_tail_dmamap->dm_xfer_len = 0; 952 #endif 953 } 954 } 955 #else 956 957 esc->sc_begin = *esc->sc_dmaaddr; 958 slop_bgn_size = DMA_SCSI_ALIGNMENT-((ulong)esc->sc_begin % DMA_SCSI_ALIGNMENT); 959 if (slop_bgn_size == DMA_SCSI_ALIGNMENT) slop_bgn_size = 0; 960 slop_end_size = esc->sc_dmasize - slop_bgn_size; 961 962 if (slop_bgn_size < esc->sc_dmasize) { 963 int error; 964 965 esc->sc_tail = 0; 966 esc->sc_tail_size = 0; 967 968 esc->sc_begin_size = slop_bgn_size; 969 esc->sc_main = *esc->sc_dmaaddr+slop_bgn_size; 970 esc->sc_main_size = DMA_ENDALIGN(caddr_t,esc->sc_main+esc->sc_dmasize-slop_bgn_size)-esc->sc_main; 971 972 if (!esc->sc_datain) { 973 esc->sc_main_size += ESP_DMA_OVERRUN; 974 } 975 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 976 esc->sc_main_dmamap, 977 esc->sc_main, esc->sc_main_size, 978 NULL, BUS_DMA_NOWAIT); 979 if (error) { 980 panic("%s: can't load main dma map. error = %d, addr=%p, size=0x%08x", 981 sc->sc_dev.dv_xname, error,esc->sc_main,esc->sc_main_size); 982 } 983 } else { 984 esc->sc_begin = 0; 985 esc->sc_begin_size = 0; 986 esc->sc_main = 0; 987 esc->sc_main_size = 0; 988 989 #if 0 990 esc->sc_tail = DMA_ENDALIGN(caddr_t,esc->sc_tailbuf+slop_bgn_size)-slop_bgn_size; 991 /* If the beginning of the tail is not correctly aligned, 992 * we have no choice but to align the start, which might then unalign the end. 993 */ 994 #endif 995 esc->sc_tail = DMA_SCSI_ALIGN(caddr_t,esc->sc_tailbuf); 996 /* So therefore, we change the tail size to be end aligned again. */ 997 esc->sc_tail_size = DMA_ENDALIGN(caddr_t,esc->sc_tail+esc->sc_dmasize)-esc->sc_tail; 998 999 /* @@@ next dma overrun lossage */ 1000 if (!esc->sc_datain) { 1001 esc->sc_tail_size += ESP_DMA_OVERRUN; 1002 } 1003 1004 { 1005 int error; 1006 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 1007 esc->sc_tail_dmamap, 1008 esc->sc_tail, esc->sc_tail_size, 1009 NULL, BUS_DMA_NOWAIT); 1010 if (error) { 1011 panic("%s: can't load tail dma map. error = %d, addr=%p, size=0x%08x", 1012 sc->sc_dev.dv_xname, error,esc->sc_tail,esc->sc_tail_size); 1013 } 1014 } 1015 } 1016 #endif 1017 1018 DPRINTF(("%s: setup: %8p %d %8p %d %8p %d %8p %d\n", sc->sc_dev.dv_xname, 1019 *esc->sc_dmaaddr, esc->sc_dmasize, esc->sc_begin, 1020 esc->sc_begin_size, esc->sc_main, esc->sc_main_size, esc->sc_tail, 1021 esc->sc_tail_size)); 1022 } 1023 1024 return (0); 1025 } 1026 1027 #ifdef ESP_DEBUG 1028 /* For debugging */ 1029 void 1030 esp_dma_store(sc) 1031 struct ncr53c9x_softc *sc; 1032 { 1033 struct esp_softc *esc = (struct esp_softc *)sc; 1034 char *p = &esp_dma_dump[0]; 1035 1036 p += sprintf(p,"%s: sc_datain=%d\n",sc->sc_dev.dv_xname,esc->sc_datain); 1037 p += sprintf(p,"%s: sc_loaded=0x%08x\n",sc->sc_dev.dv_xname,esc->sc_loaded); 1038 1039 if (esc->sc_dmaaddr) { 1040 p += sprintf(p,"%s: sc_dmaaddr=%p\n",sc->sc_dev.dv_xname,*esc->sc_dmaaddr); 1041 } else { 1042 p += sprintf(p,"%s: sc_dmaaddr=NULL\n",sc->sc_dev.dv_xname); 1043 } 1044 if (esc->sc_dmalen) { 1045 p += sprintf(p,"%s: sc_dmalen=0x%08x\n",sc->sc_dev.dv_xname,*esc->sc_dmalen); 1046 } else { 1047 p += sprintf(p,"%s: sc_dmalen=NULL\n",sc->sc_dev.dv_xname); 1048 } 1049 p += sprintf(p,"%s: sc_dmasize=0x%08x\n",sc->sc_dev.dv_xname,esc->sc_dmasize); 1050 1051 p += sprintf(p,"%s: sc_begin = %p, sc_begin_size = 0x%08x\n", 1052 sc->sc_dev.dv_xname, esc->sc_begin, esc->sc_begin_size); 1053 p += sprintf(p,"%s: sc_main = %p, sc_main_size = 0x%08x\n", 1054 sc->sc_dev.dv_xname, esc->sc_main, esc->sc_main_size); 1055 /* if (esc->sc_main) */ { 1056 int i; 1057 bus_dmamap_t map = esc->sc_main_dmamap; 1058 p += sprintf(p,"%s: sc_main_dmamap. mapsize = 0x%08lx, nsegs = %d\n", 1059 sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs); 1060 for(i=0;i<map->dm_nsegs;i++) { 1061 p += sprintf(p,"%s: map->dm_segs[%d].ds_addr = 0x%08lx, len = 0x%08lx\n", 1062 sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len); 1063 } 1064 } 1065 p += sprintf(p,"%s: sc_tail = %p, sc_tail_size = 0x%08x\n", 1066 sc->sc_dev.dv_xname, esc->sc_tail, esc->sc_tail_size); 1067 /* if (esc->sc_tail) */ { 1068 int i; 1069 bus_dmamap_t map = esc->sc_tail_dmamap; 1070 p += sprintf(p,"%s: sc_tail_dmamap. mapsize = 0x%08lx, nsegs = %d\n", 1071 sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs); 1072 for(i=0;i<map->dm_nsegs;i++) { 1073 p += sprintf(p,"%s: map->dm_segs[%d].ds_addr = 0x%08lx, len = 0x%08lx\n", 1074 sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len); 1075 } 1076 } 1077 } 1078 1079 void 1080 esp_dma_print(sc) 1081 struct ncr53c9x_softc *sc; 1082 { 1083 esp_dma_store(sc); 1084 printf("%s",esp_dma_dump); 1085 } 1086 #endif 1087 1088 void 1089 esp_dma_go(sc) 1090 struct ncr53c9x_softc *sc; 1091 { 1092 struct esp_softc *esc = (struct esp_softc *)sc; 1093 /* int s = spldma(); */ 1094 1095 if (esplogp != esplog) { 1096 if (esplogshow) { 1097 *esplogp = '\0'; 1098 printf ("esplog: %s\n", esplog); 1099 esplogshow = 0; 1100 } else { 1101 DPRINTF (("X")); 1102 } 1103 esplogp = esplog; 1104 } 1105 1106 DPRINTF(("%s: esp_dma_go(datain = %d)\n", 1107 sc->sc_dev.dv_xname, esc->sc_datain)); 1108 1109 #ifdef ESP_DEBUG 1110 if (esp_debug) esp_dma_print(sc); 1111 else esp_dma_store(sc); 1112 #endif 1113 1114 #ifdef ESP_DEBUG 1115 { 1116 int n = NCR_READ_REG(sc, NCR_FFLAG); 1117 DPRINTF(("%s: fifo size = %d, seq = 0x%x\n", 1118 sc->sc_dev.dv_xname, 1119 n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 1120 } 1121 #endif 1122 1123 /* zero length dma transfers are boring */ 1124 if (esc->sc_dmasize == 0) { 1125 /* splx(s); */ 1126 return; 1127 } 1128 1129 #if defined(DIAGNOSTIC) 1130 if ((esc->sc_begin_size == 0) && 1131 (esc->sc_main_dmamap->dm_mapsize == 0) && 1132 (esc->sc_tail_dmamap->dm_mapsize == 0)) { 1133 esp_dma_print(sc); 1134 panic("%s: No DMA requested!",sc->sc_dev.dv_xname); 1135 } 1136 #endif 1137 1138 /* Stuff the fifo with the begin buffer */ 1139 if (esc->sc_datain) { 1140 int i; 1141 DPRINTF(("%s: FIFO read of %d bytes:", 1142 sc->sc_dev.dv_xname,esc->sc_begin_size)); 1143 for(i=0;i<esc->sc_begin_size;i++) { 1144 esc->sc_begin[i]=NCR_READ_REG(sc, NCR_FIFO); 1145 DPRINTF((" %02x",esc->sc_begin[i]&0xff)); 1146 } 1147 DPRINTF(("\n")); 1148 } else { 1149 int i; 1150 DPRINTF(("%s: FIFO write of %d bytes:", 1151 sc->sc_dev.dv_xname,esc->sc_begin_size)); 1152 for(i=0;i<esc->sc_begin_size;i++) { 1153 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_begin[i]); 1154 DPRINTF((" %02x",esc->sc_begin[i]&0xff)); 1155 } 1156 DPRINTF(("\n")); 1157 } 1158 1159 if (esc->sc_main_dmamap->dm_mapsize) { 1160 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 1161 0, esc->sc_main_dmamap->dm_mapsize, 1162 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1163 esc->sc_main_dmamap->dm_xfer_len = 0; 1164 } 1165 1166 if (esc->sc_tail_dmamap->dm_mapsize) { 1167 /* if we are a dma write cycle, copy the end slop */ 1168 if (!esc->sc_datain) { 1169 memcpy(esc->sc_tail, *esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size, 1170 esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size)); 1171 } 1172 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 1173 0, esc->sc_tail_dmamap->dm_mapsize, 1174 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1175 esc->sc_tail_dmamap->dm_xfer_len = 0; 1176 } 1177 1178 esc->sc_scsi_dma.dm_xfer_len = 0; 1179 esc->sc_scsi_dma.dm_xfer_exception = 0; 1180 nextdma_start(&esc->sc_scsi_dma, 1181 (esc->sc_datain ? DMACSR_SETREAD : DMACSR_SETWRITE)); 1182 1183 if (esc->sc_datain) { 1184 NCR_WRITE_REG(sc, ESP_DCTL, 1185 ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 1186 } else { 1187 NCR_WRITE_REG(sc, ESP_DCTL, 1188 ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 1189 } 1190 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 1191 1192 if (esc->sc_begin_size) if (ESPLOGIF) { *esplogp++ = '1'; *esplogp++ = 'A' + esc->sc_begin_size; } 1193 if (esc->sc_main_size) if (ESPLOGIF) { *esplogp++ = '2'; *esplogp++ = '0' + esc->sc_main_dmamap->dm_nsegs; } 1194 if (esc->sc_tail_size) if (ESPLOGIF) { *esplogp++ = '3'; *esplogp++ = 'A' + esc->sc_tail_size; } 1195 1196 /* splx(s); */ 1197 } 1198 1199 void 1200 esp_dma_stop(sc) 1201 struct ncr53c9x_softc *sc; 1202 { 1203 struct esp_softc *esc = (struct esp_softc *)sc; 1204 next_dma_print(&esc->sc_scsi_dma); 1205 esp_dma_print(sc); 1206 #if 1 1207 panic("%s: stop not yet implemented\n",sc->sc_dev.dv_xname); 1208 #endif 1209 } 1210 1211 int 1212 esp_dma_isactive(sc) 1213 struct ncr53c9x_softc *sc; 1214 { 1215 struct esp_softc *esc = (struct esp_softc *)sc; 1216 int r = (esc->sc_dmaaddr != NULL); /* !nextdma_finished(&esc->sc_scsi_dma); */ 1217 DPRINTF(("esp_dma_isactive = %d\n",r)); 1218 return(r); 1219 } 1220 1221 /****************************************************************/ 1222 1223 int esp_dma_int __P((void *)); 1224 int esp_dma_int(arg) 1225 void *arg; 1226 { 1227 void next_dma_rotate __P((struct nextdma_config *)); 1228 void next_dma_setup_curr_regs __P((struct nextdma_config *)); 1229 void next_dma_setup_cont_regs __P((struct nextdma_config *)); 1230 1231 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1232 struct esp_softc *esc = (struct esp_softc *)sc; 1233 unsigned int state; 1234 unsigned int ds_len; 1235 struct nextdma_config *nd = &esc->sc_scsi_dma; 1236 1237 if (ESPLOGIF) *esplogp++ = 'E'; 1238 1239 state = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_CSR); 1240 1241 #if 1 1242 if (state & DMACSR_COMPLETE) if (ESPLOGIF) *esplogp++ = 'c'; 1243 if (state & DMACSR_ENABLE) if (ESPLOGIF) *esplogp++ = 'e'; 1244 if (state & DMACSR_BUSEXC) if (ESPLOGIF) *esplogp++ = 'b'; 1245 if (state & DMACSR_READ) if (ESPLOGIF) *esplogp++ = 'r'; 1246 if (state & DMACSR_SUPDATE) if (ESPLOGIF) *esplogp++ = 's'; 1247 1248 if (ESPLOGIF) *esplogp++ = 'E'; 1249 1250 if (0) if ((state & DMACSR_BUSEXC) && (state & DMACSR_ENABLE)) esplogshow++; 1251 if (0) if ((state & DMACSR_SUPDATE)) esplogshow++; 1252 #endif 1253 1254 ds_len = nd->_nd_map->dm_segs[nd->_nd_idx].ds_len; 1255 1256 if ((nd->_nd_idx+1) == nd->_nd_map->dm_nsegs) { 1257 if (nd->nd_completed_cb) 1258 (*nd->nd_completed_cb)(nd->_nd_map, nd->nd_cb_arg); 1259 } 1260 next_dma_rotate(nd); 1261 1262 if ((state & DMACSR_COMPLETE) && (state & DMACSR_ENABLE)) { 1263 #if 0 1264 int l = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT) & 0x7FFFFFFF; 1265 int s = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_STOP); 1266 #endif 1267 /* next_dma_setup_cont_regs(nd); */ 1268 if (nd->_nd_map_cont) { 1269 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_START, 1270 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr); 1271 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_STOP, 1272 (nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr + 1273 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_len) | 0/* x80000000 */); 1274 } 1275 1276 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 1277 DMACSR_CLRCOMPLETE | (state & DMACSR_READ ? DMACSR_SETREAD : DMACSR_SETWRITE) | 1278 (nd->_nd_map_cont ? DMACSR_SETSUPDATE : 0)); 1279 1280 if (nd->dm_xfer_exception == 0) { 1281 nd->dm_xfer_len += ds_len; 1282 } 1283 1284 #if 0 1285 if (state & DMACSR_BUSEXC) { 1286 sprintf (esplogp, "CE/BUSEXC: %08lX %08X %08X\n", 1287 (nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr + nd->_nd_map->dm_segs[nd->_nd_idx].ds_len), 1288 l, s); 1289 esplogp += strlen (esplogp); 1290 } 1291 #endif 1292 } else { 1293 #if 0 1294 if (state & DMACSR_BUSEXC) { 1295 while (bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT) != 1296 (bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT) & 0x7FFFFFFF)) 1297 printf ("Y"); /* DELAY(50); */ 1298 state = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_CSR); 1299 } 1300 #endif 1301 1302 if (!(state & DMACSR_SUPDATE)) { 1303 next_dma_rotate(nd); 1304 } else { 1305 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, DMACSR_CLRCOMPLETE | 1306 DMACSR_INITBUF | DMACSR_RESET | 1307 (state & DMACSR_READ ? DMACSR_SETREAD : DMACSR_SETWRITE)); 1308 1309 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_NEXT, nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr); 1310 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT, 1311 (nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr + 1312 nd->_nd_map->dm_segs[nd->_nd_idx].ds_len) | 0/* x80000000 */); 1313 if (nd->_nd_map_cont) { 1314 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_START, 1315 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr); 1316 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_STOP, 1317 (nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr + 1318 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_len) | 0/* x80000000 */); 1319 } 1320 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, DMACSR_SETENABLE | 1321 DMACSR_CLRCOMPLETE | (state & DMACSR_READ ? DMACSR_SETREAD : DMACSR_SETWRITE) | 1322 (nd->_nd_map_cont ? DMACSR_SETSUPDATE : 0)); 1323 #if 1 1324 sprintf (esplogp, "supdate "); 1325 esplogp += strlen (esplogp); 1326 sprintf (esplogp, "%08X %08X %08X %08X ", 1327 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT), 1328 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT) & 0x7FFFFFFF, 1329 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_START), 1330 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_STOP) & 0x7FFFFFFF); 1331 esplogp += strlen (esplogp); 1332 #endif 1333 nd->dm_xfer_exception++; 1334 return(1); 1335 /* NCR_WRITE_REG(sc, ESP_DCTL, ctl); */ 1336 goto restart; 1337 } 1338 1339 if (nd->_nd_map) { 1340 #if 1 1341 sprintf (esplogp, "%08X %08X %08X %08X ", 1342 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT), 1343 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT) & 0x7FFFFFFF, 1344 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_START), 1345 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_STOP) & 0x7FFFFFFF); 1346 esplogp += strlen (esplogp); 1347 #endif 1348 1349 #if 0 1350 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, DMACSR_CLRCOMPLETE | DMACSR_RESET); 1351 1352 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 0); 1353 #endif 1354 #if 1 1355 /* 6/2 */ 1356 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, DMACSR_CLRCOMPLETE | 1357 DMACSR_INITBUF | DMACSR_RESET | 1358 (state & DMACSR_READ ? DMACSR_SETREAD : DMACSR_SETWRITE)); 1359 1360 /* next_dma_setup_curr_regs(nd); */ 1361 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_NEXT, nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr); 1362 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT, 1363 (nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr + 1364 nd->_nd_map->dm_segs[nd->_nd_idx].ds_len) | 0/* x80000000 */); 1365 /* next_dma_setup_cont_regs(nd); */ 1366 if (nd->_nd_map_cont) { 1367 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_START, 1368 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr); 1369 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_STOP, 1370 (nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr + 1371 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_len) | 0/* x80000000 */); 1372 } 1373 1374 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 1375 DMACSR_SETENABLE | (nd->_nd_map_cont ? DMACSR_SETSUPDATE : 0) | 1376 (state & DMACSR_READ ? DMACSR_SETREAD : DMACSR_SETWRITE)); 1377 /* esplogshow++; */ 1378 nd->dm_xfer_exception++; 1379 return(1); 1380 #endif 1381 /* NCR_WRITE_REG(sc, ESP_DCTL, ctl); */ 1382 goto restart; 1383 restart: 1384 #if 1 1385 sprintf (esplogp, "restart %08lX %08lX\n", 1386 nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr, 1387 nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr + 1388 nd->_nd_map->dm_segs[nd->_nd_idx].ds_len); 1389 if (nd->_nd_map_cont) { 1390 sprintf (esplogp + strlen(esplogp) - 1, " %08lX %08lX\n", 1391 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr, 1392 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr + 1393 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_len); 1394 } 1395 esplogp += strlen (esplogp); 1396 #endif 1397 next_dma_print(nd); 1398 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_16MHZ | ESPDCTL_INTENB); 1399 printf ("ff:%02x tcm:%d tcl:%d esp_dstat:%02x state:%02x step: %02x intr:%02x state:%08X\n", 1400 NCR_READ_REG(sc, NCR_FFLAG), 1401 NCR_READ_REG((sc), NCR_TCM), NCR_READ_REG((sc), NCR_TCL), 1402 NCR_READ_REG(sc, ESP_DSTAT), 1403 NCR_READ_REG(sc, NCR_STAT), NCR_READ_REG(sc, NCR_STEP), 1404 NCR_READ_REG(sc, NCR_INTR), state); 1405 *esplogp = '\0'; 1406 printf ("esplog: %s\n", esplog); 1407 panic("%s: busexc/supdate occured. Please email this output to chris (at) pin.lu.", 1408 sc->sc_dev.dv_xname); 1409 esplogshow++; 1410 } else { 1411 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, DMACSR_CLRCOMPLETE | DMACSR_RESET); 1412 if (nd->nd_shutdown_cb) (*nd->nd_shutdown_cb)(nd->nd_cb_arg); 1413 } 1414 } 1415 return (1); 1416 } 1417 1418 /* Internal dma callback routines */ 1419 bus_dmamap_t 1420 esp_dmacb_continue(arg) 1421 void *arg; 1422 { 1423 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1424 struct esp_softc *esc = (struct esp_softc *)sc; 1425 1426 if (ESPLOGIF) *esplogp++ = 'x'; 1427 DPRINTF(("%s: dma continue\n",sc->sc_dev.dv_xname)); 1428 1429 #ifdef DIAGNOSTIC 1430 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 1431 panic("%s: map not loaded in dma continue callback, datain = %d", 1432 sc->sc_dev.dv_xname,esc->sc_datain); 1433 } 1434 #endif 1435 1436 if ((!(esc->sc_loaded & ESP_LOADED_MAIN)) && 1437 (esc->sc_main_dmamap->dm_mapsize)) { 1438 DPRINTF(("%s: Loading main map\n",sc->sc_dev.dv_xname)); 1439 #if 0 1440 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 1441 0, esc->sc_main_dmamap->dm_mapsize, 1442 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1443 esc->sc_main_dmamap->dm_xfer_len = 0; 1444 #endif 1445 esc->sc_loaded |= ESP_LOADED_MAIN; 1446 return(esc->sc_main_dmamap); 1447 } 1448 1449 if ((!(esc->sc_loaded & ESP_LOADED_TAIL)) && 1450 (esc->sc_tail_dmamap->dm_mapsize)) { 1451 DPRINTF(("%s: Loading tail map\n",sc->sc_dev.dv_xname)); 1452 #if 0 1453 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 1454 0, esc->sc_tail_dmamap->dm_mapsize, 1455 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1456 esc->sc_tail_dmamap->dm_xfer_len = 0; 1457 #endif 1458 esc->sc_loaded |= ESP_LOADED_TAIL; 1459 return(esc->sc_tail_dmamap); 1460 } 1461 1462 DPRINTF(("%s: not loading map\n",sc->sc_dev.dv_xname)); 1463 return(0); 1464 } 1465 1466 1467 void 1468 esp_dmacb_completed(map, arg) 1469 bus_dmamap_t map; 1470 void *arg; 1471 { 1472 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1473 struct esp_softc *esc = (struct esp_softc *)sc; 1474 1475 if (ESPLOGIF) *esplogp++ = 'X'; 1476 DPRINTF(("%s: dma completed\n",sc->sc_dev.dv_xname)); 1477 1478 #ifdef DIAGNOSTIC 1479 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 1480 panic("%s: invalid dma direction in completed callback, datain = %d", 1481 sc->sc_dev.dv_xname,esc->sc_datain); 1482 } 1483 #endif 1484 1485 #if defined(DIAGNOSTIC) && 0 1486 { 1487 int i; 1488 for(i=0;i<map->dm_nsegs;i++) { 1489 if (map->dm_xfer_len != map->dm_mapsize) { 1490 printf("%s: map->dm_mapsize = %d\n", sc->sc_dev.dv_xname,map->dm_mapsize); 1491 printf("%s: map->dm_nsegs = %d\n", sc->sc_dev.dv_xname,map->dm_nsegs); 1492 printf("%s: map->dm_xfer_len = %d\n", sc->sc_dev.dv_xname,map->dm_xfer_len); 1493 for(i=0;i<map->dm_nsegs;i++) { 1494 printf("%s: map->dm_segs[%d].ds_addr = 0x%08lx\n", 1495 sc->sc_dev.dv_xname,i,map->dm_segs[i].ds_addr); 1496 printf("%s: map->dm_segs[%d].ds_len = %d\n", 1497 sc->sc_dev.dv_xname,i,map->dm_segs[i].ds_len); 1498 } 1499 panic("%s: incomplete dma transfer\n",sc->sc_dev.dv_xname); 1500 } 1501 } 1502 } 1503 #endif 1504 1505 if (map == esc->sc_main_dmamap) { 1506 #ifdef DIAGNOSTIC 1507 if ((esc->sc_loaded & ESP_UNLOADED_MAIN) || 1508 !(esc->sc_loaded & ESP_LOADED_MAIN)) { 1509 panic("%s: unexpected completed call for main map\n",sc->sc_dev.dv_xname); 1510 } 1511 #endif 1512 esc->sc_loaded |= ESP_UNLOADED_MAIN; 1513 } else if (map == esc->sc_tail_dmamap) { 1514 #ifdef DIAGNOSTIC 1515 if ((esc->sc_loaded & ESP_UNLOADED_TAIL) || 1516 !(esc->sc_loaded & ESP_LOADED_TAIL)) { 1517 panic("%s: unexpected completed call for tail map\n",sc->sc_dev.dv_xname); 1518 } 1519 #endif 1520 esc->sc_loaded |= ESP_UNLOADED_TAIL; 1521 } 1522 #ifdef DIAGNOSTIC 1523 else { 1524 panic("%s: unexpected completed map", sc->sc_dev.dv_xname); 1525 } 1526 #endif 1527 1528 #ifdef ESP_DEBUG 1529 if (esp_debug) { 1530 if (map == esc->sc_main_dmamap) { 1531 printf("%s: completed main map\n",sc->sc_dev.dv_xname); 1532 } else if (map == esc->sc_tail_dmamap) { 1533 printf("%s: completed tail map\n",sc->sc_dev.dv_xname); 1534 } 1535 } 1536 #endif 1537 1538 #if 0 1539 if ((map == esc->sc_tail_dmamap) || 1540 ((esc->sc_tail_size == 0) && (map == esc->sc_main_dmamap))) { 1541 1542 /* Clear the DMAMOD bit in the DCTL register to give control 1543 * back to the scsi chip. 1544 */ 1545 if (esc->sc_datain) { 1546 NCR_WRITE_REG(sc, ESP_DCTL, 1547 ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 1548 } else { 1549 NCR_WRITE_REG(sc, ESP_DCTL, 1550 ESPDCTL_16MHZ | ESPDCTL_INTENB); 1551 } 1552 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 1553 } 1554 #endif 1555 1556 1557 #if 0 1558 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, map, 1559 0, map->dm_mapsize, 1560 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1561 #endif 1562 1563 } 1564 1565 void 1566 esp_dmacb_shutdown(arg) 1567 void *arg; 1568 { 1569 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1570 struct esp_softc *esc = (struct esp_softc *)sc; 1571 1572 if (ESPLOGIF) *esplogp++ = 'S'; 1573 DPRINTF(("%s: dma shutdown\n",sc->sc_dev.dv_xname)); 1574 1575 if (esc->sc_loaded == 0) 1576 return; 1577 1578 #if 0 1579 { 1580 /* Clear the DMAMOD bit in the DCTL register to give control 1581 * back to the scsi chip. 1582 */ 1583 if (esc->sc_datain) { 1584 NCR_WRITE_REG(sc, ESP_DCTL, 1585 ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 1586 } else { 1587 NCR_WRITE_REG(sc, ESP_DCTL, 1588 ESPDCTL_16MHZ | ESPDCTL_INTENB); 1589 } 1590 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 1591 } 1592 #endif 1593 1594 DPRINTF(("%s: esp_dma_nest == %d\n",sc->sc_dev.dv_xname,esp_dma_nest)); 1595 1596 /* Stuff the end slop into fifo */ 1597 1598 #ifdef ESP_DEBUG 1599 if (esp_debug) { 1600 1601 int n = NCR_READ_REG(sc, NCR_FFLAG); 1602 DPRINTF(("%s: fifo size = %d, seq = 0x%x\n", 1603 sc->sc_dev.dv_xname,n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5)); 1604 } 1605 #endif 1606 1607 if (esc->sc_main_dmamap->dm_mapsize) { 1608 if (!esc->sc_datain) { /* unpatch the dma map for write overrun */ 1609 esc->sc_main_dmamap->dm_mapsize -= ESP_DMA_OVERRUN; 1610 esc->sc_main_dmamap->dm_segs[esc->sc_main_dmamap->dm_nsegs - 1].ds_len -= 1611 ESP_DMA_OVERRUN; 1612 } 1613 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap, 1614 0, esc->sc_main_dmamap->dm_mapsize, 1615 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1616 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap); 1617 if (ESPLOGIF) { 1618 sprintf (esplogp, "m%ld", esc->sc_main_dmamap->dm_xfer_len); 1619 esplogp += strlen (esplogp); 1620 } 1621 } 1622 1623 if (esc->sc_tail_dmamap->dm_mapsize) { 1624 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap, 1625 0, esc->sc_tail_dmamap->dm_mapsize, 1626 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1627 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap); 1628 /* copy the tail dma buffer data for read transfers */ 1629 if (esc->sc_datain) { 1630 memcpy(*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size, 1631 esc->sc_tail, esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size)); 1632 } 1633 if (ESPLOGIF) { 1634 sprintf (esplogp, "t%ld", esc->sc_tail_dmamap->dm_xfer_len); 1635 esplogp += strlen (esplogp); 1636 } 1637 } 1638 1639 #ifdef ESP_DEBUG 1640 if (esp_debug) { 1641 printf("%s: dma_shutdown: addr=%p,len=0x%08x,size=0x%08x\n", 1642 sc->sc_dev.dv_xname, 1643 *esc->sc_dmaaddr, *esc->sc_dmalen, esc->sc_dmasize); 1644 if (esp_debug > 10) { 1645 esp_hex_dump(*(esc->sc_dmaaddr),esc->sc_dmasize); 1646 printf("%s: tail=%p,tailbuf=%p,tail_size=0x%08x\n", 1647 sc->sc_dev.dv_xname, 1648 esc->sc_tail, &(esc->sc_tailbuf[0]), esc->sc_tail_size); 1649 esp_hex_dump(&(esc->sc_tailbuf[0]),sizeof(esc->sc_tailbuf)); 1650 } 1651 } 1652 #endif 1653 1654 esc->sc_main = 0; 1655 esc->sc_main_size = 0; 1656 esc->sc_tail = 0; 1657 esc->sc_tail_size = 0; 1658 1659 esc->sc_datain = -1; 1660 /* esc->sc_dmaaddr = 0; */ 1661 /* esc->sc_dmalen = 0; */ 1662 /* esc->sc_dmasize = 0; */ 1663 1664 esc->sc_loaded = 0; 1665 1666 esc->sc_begin = 0; 1667 esc->sc_begin_size = 0; 1668 1669 #ifdef ESP_DEBUG 1670 if (esp_debug) { 1671 char sbuf[256]; 1672 1673 bitmask_snprintf((*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)), 1674 NEXT_INTR_BITS, sbuf, sizeof(sbuf)); 1675 printf(" *intrstat = 0x%s\n", sbuf); 1676 1677 bitmask_snprintf((*(volatile u_long *)IIOV(NEXT_P_INTRMASK)), 1678 NEXT_INTR_BITS, sbuf, sizeof(sbuf)); 1679 printf(" *intrmask = 0x%s\n", sbuf); 1680 } 1681 #endif 1682 } 1683
Indexes created Tue Sep 23 07:09:52 GMT 2025