esp.c revision 1.4
1 /* $NetBSD: esp.c,v 1.4 1998/07/21 06:17:35 dbj Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Charles M. Hannum. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * Copyright (c) 1994 Peter Galbavy 71 * Copyright (c) 1995 Paul Kranenburg 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 3. All advertising materials mentioning features or use of this software 83 * must display the following acknowledgement: 84 * This product includes software developed by Peter Galbavy 85 * 4. The name of the author may not be used to endorse or promote products 86 * derived from this software without specific prior written permission. 87 * 88 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 89 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 90 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 91 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 92 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 93 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 94 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 95 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 96 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 97 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 98 * POSSIBILITY OF SUCH DAMAGE. 99 */ 100 101 /* 102 * Based on aic6360 by Jarle Greipsland 103 * 104 * Acknowledgements: Many of the algorithms used in this driver are 105 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 106 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 107 */ 108 109 /* 110 * Grabbed from the sparc port at revision 1.73 for the NeXT. 111 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 112 */ 113 114 #include <sys/types.h> 115 #include <sys/param.h> 116 #include <sys/systm.h> 117 #include <sys/kernel.h> 118 #include <sys/errno.h> 119 #include <sys/ioctl.h> 120 #include <sys/device.h> 121 #include <sys/buf.h> 122 #include <sys/proc.h> 123 #include <sys/user.h> 124 #include <sys/queue.h> 125 126 #include <dev/scsipi/scsi_all.h> 127 #include <dev/scsipi/scsipi_all.h> 128 #include <dev/scsipi/scsiconf.h> 129 #include <dev/scsipi/scsi_message.h> 130 131 #include <machine/bus.h> 132 #include <machine/autoconf.h> 133 #include <machine/cpu.h> 134 135 #include <dev/ic/ncr53c9xreg.h> 136 #include <dev/ic/ncr53c9xvar.h> 137 138 #include <next68k/next68k/isr.h> 139 140 #include <next68k/dev/nextdmareg.h> 141 #include <next68k/dev/nextdmavar.h> 142 143 #include "espreg.h" 144 #include "espvar.h" 145 146 #if 1 147 #define ESP_DEBUG 148 #endif 149 150 #ifdef ESP_DEBUG 151 #define DPRINTF(x) printf x; 152 #else 153 #define DPRINTF(x) 154 #endif 155 156 157 void espattach_intio __P((struct device *, struct device *, void *)); 158 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 159 160 /* DMA callbacks */ 161 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 162 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 163 void esp_dmacb_shutdown __P((void *arg)); 164 165 /* Linkup to the rest of the kernel */ 166 struct cfattach esp_ca = { 167 sizeof(struct esp_softc), espmatch_intio, espattach_intio 168 }; 169 170 struct scsipi_adapter esp_switch = { 171 ncr53c9x_scsi_cmd, 172 minphys, /* no max at this level; handled by DMA code */ 173 NULL, 174 NULL, 175 }; 176 177 struct scsipi_device esp_dev = { 178 NULL, /* Use default error handler */ 179 NULL, /* have a queue, served by this */ 180 NULL, /* have no async handler */ 181 NULL, /* Use default 'done' routine */ 182 }; 183 184 /* 185 * Functions and the switch for the MI code. 186 */ 187 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 188 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 189 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 190 void esp_dma_reset __P((struct ncr53c9x_softc *)); 191 int esp_dma_intr __P((struct ncr53c9x_softc *)); 192 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 193 size_t *, int, size_t *)); 194 void esp_dma_go __P((struct ncr53c9x_softc *)); 195 void esp_dma_stop __P((struct ncr53c9x_softc *)); 196 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 197 198 struct ncr53c9x_glue esp_glue = { 199 esp_read_reg, 200 esp_write_reg, 201 esp_dma_isintr, 202 esp_dma_reset, 203 esp_dma_intr, 204 esp_dma_setup, 205 esp_dma_go, 206 esp_dma_stop, 207 esp_dma_isactive, 208 NULL, /* gl_clear_latched_intr */ 209 }; 210 211 int 212 espmatch_intio(parent, cf, aux) 213 struct device *parent; 214 struct cfdata *cf; 215 void *aux; 216 { 217 /* should probably probe here */ 218 /* Should also probably set up data from config */ 219 220 #if 1 221 /* this code isn't working yet, don't match on it */ 222 return(0); 223 #else 224 return(1); 225 #endif 226 } 227 228 void 229 espattach_intio(parent, self, aux) 230 struct device *parent, *self; 231 void *aux; 232 { 233 struct esp_softc *esc = (void *)self; 234 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 235 236 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 237 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 238 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 239 panic("\n%s: can't map ncr53c90 registers", 240 sc->sc_dev.dv_xname); 241 } 242 243 sc->sc_id = 7; 244 sc->sc_freq = 20; /* Mhz */ 245 246 /* 247 * Set up glue for MI code early; we use some of it here. 248 */ 249 sc->sc_glue = &esp_glue; 250 251 /* 252 * XXX More of this should be in ncr53c9x_attach(), but 253 * XXX should we really poke around the chip that much in 254 * XXX the MI code? Think about this more... 255 */ 256 257 /* 258 * It is necessary to try to load the 2nd config register here, 259 * to find out what rev the esp chip is, else the ncr53c9x_reset 260 * will not set up the defaults correctly. 261 */ 262 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 263 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 264 sc->sc_cfg3 = NCRCFG3_CDB; 265 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 266 267 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 268 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 269 sc->sc_rev = NCR_VARIANT_ESP100; 270 } else { 271 sc->sc_cfg2 = NCRCFG2_SCSI2; 272 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 273 sc->sc_cfg3 = 0; 274 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 275 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 276 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 277 if (NCR_READ_REG(sc, NCR_CFG3) != 278 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 279 sc->sc_rev = NCR_VARIANT_ESP100A; 280 } else { 281 /* NCRCFG2_FE enables > 64K transfers */ 282 sc->sc_cfg2 |= NCRCFG2_FE; 283 sc->sc_cfg3 = 0; 284 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 285 sc->sc_rev = NCR_VARIANT_ESP200; 286 } 287 } 288 289 /* 290 * XXX minsync and maxxfer _should_ be set up in MI code, 291 * XXX but it appears to have some dependency on what sort 292 * XXX of DMA we're hooked up to, etc. 293 */ 294 295 /* 296 * This is the value used to start sync negotiations 297 * Note that the NCR register "SYNCTP" is programmed 298 * in "clocks per byte", and has a minimum value of 4. 299 * The SCSI period used in negotiation is one-fourth 300 * of the time (in nanoseconds) needed to transfer one byte. 301 * Since the chip's clock is given in MHz, we have the following 302 * formula: 4 * period = (1000 / freq) * 4 303 */ 304 sc->sc_minsync = 1000 / sc->sc_freq; 305 306 /* 307 * Alas, we must now modify the value a bit, because it's 308 * only valid when can switch on FASTCLK and FASTSCSI bits 309 * in config register 3... 310 */ 311 switch (sc->sc_rev) { 312 case NCR_VARIANT_ESP100: 313 sc->sc_maxxfer = 64 * 1024; 314 sc->sc_minsync = 0; /* No synch on old chip? */ 315 break; 316 317 case NCR_VARIANT_ESP100A: 318 sc->sc_maxxfer = 64 * 1024; 319 /* Min clocks/byte is 5 */ 320 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 321 break; 322 323 case NCR_VARIANT_ESP200: 324 sc->sc_maxxfer = 16 * 1024 * 1024; 325 /* XXX - do actually set FAST* bits */ 326 break; 327 } 328 329 /* @@@ Some ESP_DCTL bits probably need setting */ 330 NCR_WRITE_REG(sc, ESP_DCTL, 331 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 332 DELAY(10); 333 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 334 DELAY(10); 335 336 /* Set up SCSI DMA */ 337 { 338 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 339 340 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 341 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 342 panic("\n%s: can't map scsi DMA registers", 343 sc->sc_dev.dv_xname); 344 } 345 346 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 347 esc->sc_scsi_dma.nd_chaining_flag = 0; 348 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 349 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 350 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 351 esc->sc_scsi_dma.nd_cb_arg = sc; 352 nextdma_config(&esc->sc_scsi_dma); 353 nextdma_init(&esc->sc_scsi_dma); 354 355 { 356 int error; 357 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 358 sc->sc_maxxfer, 1, sc->sc_maxxfer, 359 0, BUS_DMA_ALLOCNOW, &esc->sc_dmamap)) != 0) { 360 panic("%s: can't create i/o DMA map, error = %d", 361 sc->sc_dev.dv_xname,error); 362 } 363 } 364 } 365 366 #if 0 367 /* Turn on target selection using the `dma' method */ 368 ncr53c9x_dmaselect = 1; 369 #else 370 ncr53c9x_dmaselect = 0; 371 #endif 372 373 esc->sc_slop_bgn_addr = 0; 374 esc->sc_slop_bgn_size = 0; 375 esc->sc_slop_end_addr = 0; 376 esc->sc_slop_end_size = 0; 377 esc->sc_datain = -1; 378 379 /* Establish interrupt channel */ 380 isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc, 381 NEXT_I_IPL(NEXT_I_SCSI), 0); 382 INTR_ENABLE(NEXT_I_SCSI); 383 384 /* register interrupt stats */ 385 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 386 387 /* Do the common parts of attachment. */ 388 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 389 } 390 391 /* 392 * Glue functions. 393 */ 394 395 u_char 396 esp_read_reg(sc, reg) 397 struct ncr53c9x_softc *sc; 398 int reg; 399 { 400 struct esp_softc *esc = (struct esp_softc *)sc; 401 402 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 403 } 404 405 void 406 esp_write_reg(sc, reg, val) 407 struct ncr53c9x_softc *sc; 408 int reg; 409 u_char val; 410 { 411 struct esp_softc *esc = (struct esp_softc *)sc; 412 413 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 414 } 415 416 int 417 esp_dma_isintr(sc) 418 struct ncr53c9x_softc *sc; 419 { 420 struct esp_softc *esc = (struct esp_softc *)sc; 421 422 int r = (INTR_OCCURRED(NEXT_I_SCSI)); 423 424 if (r) { 425 DPRINTF(("esp_dma_isintr = %d\n",r)); 426 427 if (esc->sc_datain) { 428 NCR_WRITE_REG(sc, ESP_DCTL, 429 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 430 } else { 431 NCR_WRITE_REG(sc, ESP_DCTL, 432 ESPDCTL_20MHZ | ESPDCTL_INTENB); 433 } 434 } 435 436 return (r); 437 } 438 439 void 440 esp_dma_reset(sc) 441 struct ncr53c9x_softc *sc; 442 { 443 struct esp_softc *esc = (struct esp_softc *)sc; 444 445 nextdma_reset(&esc->sc_scsi_dma); 446 447 if (esc->sc_dmamap->dm_mapsize != 0) { 448 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap); 449 } 450 451 esc->sc_slop_bgn_addr = 0; 452 esc->sc_slop_bgn_size = 0; 453 esc->sc_slop_end_addr = 0; 454 esc->sc_slop_end_size = 0; 455 esc->sc_datain = -1; 456 } 457 458 int 459 esp_dma_intr(sc) 460 struct ncr53c9x_softc *sc; 461 { 462 int trans; 463 int resid; 464 int datain; 465 struct esp_softc *esc = (struct esp_softc *)sc; 466 467 datain = esc->sc_datain; 468 469 DPRINTF(("esp_dma_intr resetting dma\n")); 470 471 /* If the dma hasn't finished when we are in a scsi 472 * interrupt. Then, "Houston, we have a problem." 473 * Stop DMA and figure out how many bytes were transferred 474 */ 475 esp_dma_reset(sc); 476 477 resid = 0; 478 479 /* 480 * If a transfer onto the SCSI bus gets interrupted by the device 481 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 482 * as residual since the ESP counter registers get decremented as 483 * bytes are clocked into the FIFO. 484 */ 485 486 if (! datain) { 487 resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 488 if (resid) { 489 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 490 NCRCMD(sc, NCRCMD_FLUSH); 491 DELAY(1); 492 } 493 } 494 495 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 496 /* 497 * `Terminal count' is off, so read the residue 498 * out of the ESP counter registers. 499 */ 500 resid += (NCR_READ_REG(sc, NCR_TCL) | 501 (NCR_READ_REG(sc, NCR_TCM) << 8) | 502 ((sc->sc_cfg2 & NCRCFG2_FE) 503 ? (NCR_READ_REG(sc, NCR_TCH) << 16) 504 : 0)); 505 506 if (resid == 0 && esc->sc_dmasize == 65536 && 507 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 508 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 509 resid = 65536; 510 } 511 512 trans = esc->sc_dmasize - resid; 513 if (trans < 0) { /* transferred < 0 ? */ 514 #if 0 515 /* 516 * This situation can happen in perfectly normal operation 517 * if the ESP is reselected while using DMA to select 518 * another target. As such, don't print the warning. 519 */ 520 printf("%s: xfer (%d) > req (%d)\n", 521 esc->sc_dev.dv_xname, trans, esc->sc_dmasize); 522 #endif 523 trans = esc->sc_dmasize; 524 } 525 526 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 527 NCR_READ_REG(sc, NCR_TCL), 528 NCR_READ_REG(sc, NCR_TCM), 529 (sc->sc_cfg2 & NCRCFG2_FE) 530 ? NCR_READ_REG(sc, NCR_TCH) : 0, 531 trans, resid)); 532 533 *esc->sc_dmalen -= trans; 534 *esc->sc_dmaaddr += trans; 535 536 return 0; 537 } 538 539 int 540 esp_dma_setup(sc, addr, len, datain, dmasize) 541 struct ncr53c9x_softc *sc; 542 caddr_t *addr; 543 size_t *len; 544 int datain; 545 size_t *dmasize; 546 { 547 struct esp_softc *esc = (struct esp_softc *)sc; 548 549 /* Save these in case we have to abort DMA */ 550 esc->sc_dmaaddr = addr; 551 esc->sc_dmalen = len; 552 esc->sc_dmasize = *dmasize; 553 554 DPRINTF(("esp_dma_setup(0x%08lx,0x%08lx)\n",*addr,*dmasize)); 555 556 #ifdef DIAGNOSTIC 557 if ((esc->sc_datain != -1) || 558 (esc->sc_dmamap->dm_mapsize != 0)) { 559 panic("%s: map already loaded in esp_dma_setup\n" 560 "\tdatain = %d\n\tmapsize=%d", 561 sc->sc_dev.dv_xname,esc->sc_datain,esc->sc_dmamap->dm_mapsize); 562 } 563 #endif 564 565 /* Deal with DMA alignment issues, by stuffing the FIFO. 566 * This assumes that if bus_dmamap_load is given an aligned 567 * buffer, then it will generate aligned hardware addresses 568 * to give to the device. Perhaps that is not a good assumption, 569 * but it is probably true. [dbj (at) netbsd.org:19980719.0135EDT] 570 */ 571 { 572 int slop_bgn_size; /* # bytes to be fifo'd at beginning */ 573 int slop_end_size; /* # bytes to be fifo'd at end */ 574 575 { 576 u_long bgn = (u_long)(*addr); 577 u_long end = (u_long)(*addr+*dmasize); 578 579 slop_bgn_size = DMA_BEGINALIGNMENT-(bgn % DMA_BEGINALIGNMENT); 580 if (slop_bgn_size == DMA_BEGINALIGNMENT) slop_bgn_size = 0; 581 slop_end_size = end % DMA_ENDALIGNMENT; 582 } 583 584 /* Check to make sure we haven't counted the slop twice 585 * as would happen for a very short dma buffer */ 586 if (slop_bgn_size+slop_end_size > *dmasize) { 587 #if defined(DIAGNOSTIC) 588 if ((slop_bgn_size != *dmasize) || 589 (slop_end_size != *dmasize)) { 590 panic("%s: confused alignment calculation\n" 591 "\tslop_bgn_size %d\n\tslop_end_size %d\n\tdmasize %d", 592 sc->sc_dev.dv_xname,slop_bgn_size,slop_end_size,*dmasize); 593 } 594 #endif 595 slop_end_size = 0; 596 } 597 598 if (slop_bgn_size+slop_end_size < *dmasize) { 599 int error; 600 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 601 esc->sc_dmamap, 602 *addr+slop_bgn_size, 603 *dmasize-(slop_bgn_size+slop_end_size), 604 NULL, BUS_DMA_NOWAIT); 605 if (error) { 606 panic("%s: can't load dma map. error = %d", 607 sc->sc_dev.dv_xname, error); 608 } 609 610 } else { 611 /* If there's no DMA, then coalesce the fifo buffers */ 612 slop_bgn_size += slop_end_size; 613 slop_end_size = 0; 614 } 615 616 esc->sc_slop_bgn_addr = *addr; 617 esc->sc_slop_bgn_size = slop_bgn_size; 618 esc->sc_slop_end_addr = (*addr+*dmasize)-slop_end_size; 619 esc->sc_slop_end_size = slop_end_size; 620 } 621 622 esc->sc_datain = datain; 623 624 return (0); 625 } 626 627 void 628 esp_dma_go(sc) 629 struct ncr53c9x_softc *sc; 630 { 631 struct esp_softc *esc = (struct esp_softc *)sc; 632 633 DPRINTF(("esp_dma_go(datain = %d)\n",esc->sc_datain)); 634 635 DPRINTF(("\tbgn slop = %d\n\tend slop = %d\n\tmapsize = %d\n", 636 esc->sc_slop_bgn_size,esc->sc_slop_end_size, 637 esc->sc_dmamap->dm_mapsize)); 638 639 DPRINTF(("esp fifo size = %d\n", 640 (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF))); 641 642 if (esc->sc_datain) { 643 NCR_WRITE_REG(sc, ESP_DCTL, 644 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 645 } else { 646 NCR_WRITE_REG(sc, ESP_DCTL, 647 ESPDCTL_20MHZ | ESPDCTL_INTENB); 648 } 649 650 if (esc->sc_datain) { 651 int i; 652 #ifdef DIAGNOSTIC 653 #if 0 /* This is a fine thing to happen */ 654 int n = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 655 if (n != esc->sc_slop_bgn_size) { 656 panic("%s: Unexpected data in fifo n = %d, expecting %d ", 657 sc->sc_dev.dv_xname, n, esc->sc_slop_bgn_size); 658 } 659 #endif 660 #endif 661 for(i=0;i<esc->sc_slop_bgn_size;i++) { 662 esc->sc_slop_bgn_addr[i]=NCR_READ_REG(sc, NCR_FIFO); 663 } 664 665 } else { 666 int i; 667 for(i=0;i<esc->sc_slop_bgn_size;i++) { 668 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_slop_bgn_addr[i]); 669 } 670 671 DPRINTF(("esp fifo size = %d\n", 672 (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF))); 673 } 674 675 if (esc->sc_dmamap->dm_mapsize != 0) { 676 if (esc->sc_datain) { 677 NCR_WRITE_REG(sc, ESP_DCTL, 678 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 679 } else { 680 NCR_WRITE_REG(sc, ESP_DCTL, 681 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 682 } 683 684 685 nextdma_start(&esc->sc_scsi_dma, 686 (esc->sc_datain ? DMACSR_READ : DMACSR_WRITE)); 687 } else { 688 #if defined(DIAGNOSTIC) 689 /* verify that end slop is 0, since the shutdown 690 * callback will not be called. 691 */ 692 if (esc->sc_slop_end_size != 0) { 693 panic("%s: Unexpected end slop with no DMA, slop = %d", 694 sc->sc_dev.dv_xname, esc->sc_slop_end_size); 695 } 696 #endif 697 #if 0 698 if (esc->sc_datain) { 699 NCR_WRITE_REG(sc, ESP_DCTL, 700 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD | ESPDCTL_FLUSH); 701 } else { 702 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 703 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_FLUSH); 704 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 705 } 706 #endif 707 708 esc->sc_datain = -1; 709 esc->sc_slop_bgn_addr = 0; 710 esc->sc_slop_bgn_size = 0; 711 esc->sc_slop_end_addr = 0; 712 esc->sc_slop_end_size = 0; 713 714 DPRINTF(("esp fifo size = %d\n", 715 (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF))); 716 } 717 } 718 719 void 720 esp_dma_stop(sc) 721 struct ncr53c9x_softc *sc; 722 { 723 panic("Not yet implemented"); 724 } 725 726 int 727 esp_dma_isactive(sc) 728 struct ncr53c9x_softc *sc; 729 { 730 struct esp_softc *esc = (struct esp_softc *)sc; 731 return( !nextdma_finished(&esc->sc_scsi_dma)); 732 } 733 734 /****************************************************************/ 735 736 /* Internal dma callback routines */ 737 bus_dmamap_t 738 esp_dmacb_continue(arg) 739 void *arg; 740 { 741 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 742 struct esp_softc *esc = (struct esp_softc *)sc; 743 744 DPRINTF(("esp dma continue\n")); 745 746 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap, 747 0, esc->sc_dmamap->dm_mapsize, 748 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 749 750 #ifdef DIAGNOSTIC 751 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 752 panic("%s: map not loaded in dma continue callback, datain = %d", 753 sc->sc_dev.dv_xname,esc->sc_datain); 754 } 755 #endif 756 757 return(esc->sc_dmamap); 758 } 759 760 void 761 esp_dmacb_completed(map, arg) 762 bus_dmamap_t map; 763 void *arg; 764 { 765 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 766 struct esp_softc *esc = (struct esp_softc *)sc; 767 768 DPRINTF(("esp dma completed\n")); 769 770 #ifdef DIAGNOSTIC 771 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 772 panic("%s: map not loaded in dma completed callback, datain = %d", 773 sc->sc_dev.dv_xname,esc->sc_datain); 774 } 775 if (map != esc->sc_dmamap) { 776 panic("%s: unexpected tx completed map", sc->sc_dev.dv_xname); 777 } 778 #endif 779 780 /* @@@ Flush the fifo? */ 781 782 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap, 783 0, esc->sc_dmamap->dm_mapsize, 784 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 785 } 786 787 void 788 esp_dmacb_shutdown(arg) 789 void *arg; 790 { 791 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 792 struct esp_softc *esc = (struct esp_softc *)sc; 793 794 DPRINTF(("esp dma shutdown\n")); 795 796 #ifdef DIAGNOSTIC 797 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 798 panic("%s: map not loaded in dma shutdown callback, datain = %d", 799 sc->sc_dev.dv_xname,esc->sc_datain); 800 } 801 #endif 802 803 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap); 804 805 /* Stuff the end slop into fifo */ 806 807 { 808 if (esc->sc_datain) { 809 NCR_WRITE_REG(sc, ESP_DCTL, 810 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 811 } else { 812 NCR_WRITE_REG(sc, ESP_DCTL, 813 ESPDCTL_20MHZ | ESPDCTL_INTENB); 814 } 815 816 if (esc->sc_datain) { 817 int i; 818 #ifdef DIAGNOSTIC 819 int n = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 820 if (n != esc->sc_slop_end_size) { 821 panic("%s: Unexpected data in fifo n = %d, expecting %d at end", 822 sc->sc_dev.dv_xname, n, esc->sc_slop_end_size); 823 } 824 #endif 825 for(i=0;i<esc->sc_slop_end_size;i++) { 826 esc->sc_slop_end_addr[i]=NCR_READ_REG(sc, NCR_FIFO); 827 } 828 829 } else { 830 int i; 831 for(i=0;i<esc->sc_slop_end_size;i++) { 832 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_slop_end_addr[i]); 833 } 834 } 835 } 836 837 838 esc->sc_datain = -1; 839 esc->sc_slop_bgn_addr = 0; 840 esc->sc_slop_bgn_size = 0; 841 esc->sc_slop_end_addr = 0; 842 esc->sc_slop_end_size = 0; 843 } 844
Indexes created Thu Sep 25 16:09:42 GMT 2025