esp.c revision 1.6
1 /* $NetBSD: esp.c,v 1.6 1998/08/15 05:16:43 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * Copyright (c) 1995 Paul Kranenburg 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by Peter Galbavy 56 * 4. The name of the author may not be used to endorse or promote products 57 * derived from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 61 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 62 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 67 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 68 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Based on aic6360 by Jarle Greipsland 74 * 75 * Acknowledgements: Many of the algorithms used in this driver are 76 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 77 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 78 */ 79 80 /* 81 * Grabbed from the sparc port at revision 1.73 for the NeXT. 82 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 83 */ 84 85 #include <sys/types.h> 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/kernel.h> 89 #include <sys/errno.h> 90 #include <sys/ioctl.h> 91 #include <sys/device.h> 92 #include <sys/buf.h> 93 #include <sys/proc.h> 94 #include <sys/user.h> 95 #include <sys/queue.h> 96 97 #include <dev/scsipi/scsi_all.h> 98 #include <dev/scsipi/scsipi_all.h> 99 #include <dev/scsipi/scsiconf.h> 100 #include <dev/scsipi/scsi_message.h> 101 102 #include <machine/bus.h> 103 #include <machine/autoconf.h> 104 #include <machine/cpu.h> 105 106 #include <dev/ic/ncr53c9xreg.h> 107 #include <dev/ic/ncr53c9xvar.h> 108 109 #include <next68k/next68k/isr.h> 110 111 #include <next68k/dev/nextdmareg.h> 112 #include <next68k/dev/nextdmavar.h> 113 114 #include "espreg.h" 115 #include "espvar.h" 116 117 #if 1 118 #define ESP_DEBUG 119 #endif 120 121 #ifdef ESP_DEBUG 122 #define DPRINTF(x) printf x; 123 #else 124 #define DPRINTF(x) 125 #endif 126 127 128 void espattach_intio __P((struct device *, struct device *, void *)); 129 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 130 131 /* DMA callbacks */ 132 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 133 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 134 void esp_dmacb_shutdown __P((void *arg)); 135 136 /* Linkup to the rest of the kernel */ 137 struct cfattach esp_ca = { 138 sizeof(struct esp_softc), espmatch_intio, espattach_intio 139 }; 140 141 struct scsipi_adapter esp_switch = { 142 ncr53c9x_scsi_cmd, 143 minphys, /* no max at this level; handled by DMA code */ 144 NULL, 145 NULL, 146 }; 147 148 struct scsipi_device esp_dev = { 149 NULL, /* Use default error handler */ 150 NULL, /* have a queue, served by this */ 151 NULL, /* have no async handler */ 152 NULL, /* Use default 'done' routine */ 153 }; 154 155 /* 156 * Functions and the switch for the MI code. 157 */ 158 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 159 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 160 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 161 void esp_dma_reset __P((struct ncr53c9x_softc *)); 162 int esp_dma_intr __P((struct ncr53c9x_softc *)); 163 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 164 size_t *, int, size_t *)); 165 void esp_dma_go __P((struct ncr53c9x_softc *)); 166 void esp_dma_stop __P((struct ncr53c9x_softc *)); 167 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 168 169 struct ncr53c9x_glue esp_glue = { 170 esp_read_reg, 171 esp_write_reg, 172 esp_dma_isintr, 173 esp_dma_reset, 174 esp_dma_intr, 175 esp_dma_setup, 176 esp_dma_go, 177 esp_dma_stop, 178 esp_dma_isactive, 179 NULL, /* gl_clear_latched_intr */ 180 }; 181 182 int 183 espmatch_intio(parent, cf, aux) 184 struct device *parent; 185 struct cfdata *cf; 186 void *aux; 187 { 188 /* should probably probe here */ 189 /* Should also probably set up data from config */ 190 191 #if 1 192 /* this code isn't working yet, don't match on it */ 193 return(0); 194 #else 195 return(1); 196 #endif 197 } 198 199 void 200 espattach_intio(parent, self, aux) 201 struct device *parent, *self; 202 void *aux; 203 { 204 struct esp_softc *esc = (void *)self; 205 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 206 207 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 208 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 209 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 210 panic("\n%s: can't map ncr53c90 registers", 211 sc->sc_dev.dv_xname); 212 } 213 214 sc->sc_id = 7; 215 sc->sc_freq = 20; /* Mhz */ 216 217 /* 218 * Set up glue for MI code early; we use some of it here. 219 */ 220 sc->sc_glue = &esp_glue; 221 222 /* 223 * XXX More of this should be in ncr53c9x_attach(), but 224 * XXX should we really poke around the chip that much in 225 * XXX the MI code? Think about this more... 226 */ 227 228 /* 229 * It is necessary to try to load the 2nd config register here, 230 * to find out what rev the esp chip is, else the ncr53c9x_reset 231 * will not set up the defaults correctly. 232 */ 233 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 234 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 235 sc->sc_cfg3 = NCRCFG3_CDB; 236 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 237 238 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 239 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 240 sc->sc_rev = NCR_VARIANT_ESP100; 241 } else { 242 sc->sc_cfg2 = NCRCFG2_SCSI2; 243 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 244 sc->sc_cfg3 = 0; 245 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 246 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 247 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 248 if (NCR_READ_REG(sc, NCR_CFG3) != 249 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 250 sc->sc_rev = NCR_VARIANT_ESP100A; 251 } else { 252 /* NCRCFG2_FE enables > 64K transfers */ 253 sc->sc_cfg2 |= NCRCFG2_FE; 254 sc->sc_cfg3 = 0; 255 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 256 sc->sc_rev = NCR_VARIANT_ESP200; 257 } 258 } 259 260 /* 261 * XXX minsync and maxxfer _should_ be set up in MI code, 262 * XXX but it appears to have some dependency on what sort 263 * XXX of DMA we're hooked up to, etc. 264 */ 265 266 /* 267 * This is the value used to start sync negotiations 268 * Note that the NCR register "SYNCTP" is programmed 269 * in "clocks per byte", and has a minimum value of 4. 270 * The SCSI period used in negotiation is one-fourth 271 * of the time (in nanoseconds) needed to transfer one byte. 272 * Since the chip's clock is given in MHz, we have the following 273 * formula: 4 * period = (1000 / freq) * 4 274 */ 275 sc->sc_minsync = 1000 / sc->sc_freq; 276 277 /* 278 * Alas, we must now modify the value a bit, because it's 279 * only valid when can switch on FASTCLK and FASTSCSI bits 280 * in config register 3... 281 */ 282 switch (sc->sc_rev) { 283 case NCR_VARIANT_ESP100: 284 sc->sc_maxxfer = 64 * 1024; 285 sc->sc_minsync = 0; /* No synch on old chip? */ 286 break; 287 288 case NCR_VARIANT_ESP100A: 289 sc->sc_maxxfer = 64 * 1024; 290 /* Min clocks/byte is 5 */ 291 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 292 break; 293 294 case NCR_VARIANT_ESP200: 295 sc->sc_maxxfer = 16 * 1024 * 1024; 296 /* XXX - do actually set FAST* bits */ 297 break; 298 } 299 300 /* @@@ Some ESP_DCTL bits probably need setting */ 301 NCR_WRITE_REG(sc, ESP_DCTL, 302 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 303 DELAY(10); 304 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 305 DELAY(10); 306 307 /* Set up SCSI DMA */ 308 { 309 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 310 311 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 312 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 313 panic("\n%s: can't map scsi DMA registers", 314 sc->sc_dev.dv_xname); 315 } 316 317 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 318 esc->sc_scsi_dma.nd_chaining_flag = 0; 319 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 320 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 321 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 322 esc->sc_scsi_dma.nd_cb_arg = sc; 323 nextdma_config(&esc->sc_scsi_dma); 324 nextdma_init(&esc->sc_scsi_dma); 325 326 { 327 int error; 328 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 329 sc->sc_maxxfer, 1, sc->sc_maxxfer, 330 0, BUS_DMA_ALLOCNOW, &esc->sc_dmamap)) != 0) { 331 panic("%s: can't create i/o DMA map, error = %d", 332 sc->sc_dev.dv_xname,error); 333 } 334 } 335 } 336 337 #if 0 338 /* Turn on target selection using the `dma' method */ 339 ncr53c9x_dmaselect = 1; 340 #else 341 ncr53c9x_dmaselect = 0; 342 #endif 343 344 esc->sc_slop_bgn_addr = 0; 345 esc->sc_slop_bgn_size = 0; 346 esc->sc_slop_end_addr = 0; 347 esc->sc_slop_end_size = 0; 348 esc->sc_datain = -1; 349 350 /* Establish interrupt channel */ 351 isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc, 352 NEXT_I_IPL(NEXT_I_SCSI), 0); 353 INTR_ENABLE(NEXT_I_SCSI); 354 355 /* register interrupt stats */ 356 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 357 358 /* Do the common parts of attachment. */ 359 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 360 } 361 362 /* 363 * Glue functions. 364 */ 365 366 u_char 367 esp_read_reg(sc, reg) 368 struct ncr53c9x_softc *sc; 369 int reg; 370 { 371 struct esp_softc *esc = (struct esp_softc *)sc; 372 373 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 374 } 375 376 void 377 esp_write_reg(sc, reg, val) 378 struct ncr53c9x_softc *sc; 379 int reg; 380 u_char val; 381 { 382 struct esp_softc *esc = (struct esp_softc *)sc; 383 384 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 385 } 386 387 int 388 esp_dma_isintr(sc) 389 struct ncr53c9x_softc *sc; 390 { 391 struct esp_softc *esc = (struct esp_softc *)sc; 392 393 int r = (INTR_OCCURRED(NEXT_I_SCSI)); 394 395 if (r) { 396 DPRINTF(("esp_dma_isintr = %d\n",r)); 397 398 if (esc->sc_datain) { 399 NCR_WRITE_REG(sc, ESP_DCTL, 400 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 401 } else { 402 NCR_WRITE_REG(sc, ESP_DCTL, 403 ESPDCTL_20MHZ | ESPDCTL_INTENB); 404 } 405 } 406 407 return (r); 408 } 409 410 void 411 esp_dma_reset(sc) 412 struct ncr53c9x_softc *sc; 413 { 414 struct esp_softc *esc = (struct esp_softc *)sc; 415 416 nextdma_reset(&esc->sc_scsi_dma); 417 418 if (esc->sc_dmamap->dm_mapsize != 0) { 419 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap); 420 } 421 422 esc->sc_slop_bgn_addr = 0; 423 esc->sc_slop_bgn_size = 0; 424 esc->sc_slop_end_addr = 0; 425 esc->sc_slop_end_size = 0; 426 esc->sc_datain = -1; 427 } 428 429 int 430 esp_dma_intr(sc) 431 struct ncr53c9x_softc *sc; 432 { 433 int trans; 434 int resid; 435 int datain; 436 struct esp_softc *esc = (struct esp_softc *)sc; 437 438 datain = esc->sc_datain; 439 440 DPRINTF(("esp_dma_intr resetting dma\n")); 441 442 /* If the dma hasn't finished when we are in a scsi 443 * interrupt. Then, "Houston, we have a problem." 444 * Stop DMA and figure out how many bytes were transferred 445 */ 446 esp_dma_reset(sc); 447 448 resid = 0; 449 450 /* 451 * If a transfer onto the SCSI bus gets interrupted by the device 452 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 453 * as residual since the ESP counter registers get decremented as 454 * bytes are clocked into the FIFO. 455 */ 456 457 if (! datain) { 458 resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 459 if (resid) { 460 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 461 NCRCMD(sc, NCRCMD_FLUSH); 462 DELAY(1); 463 } 464 } 465 466 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 467 /* 468 * `Terminal count' is off, so read the residue 469 * out of the ESP counter registers. 470 */ 471 resid += (NCR_READ_REG(sc, NCR_TCL) | 472 (NCR_READ_REG(sc, NCR_TCM) << 8) | 473 ((sc->sc_cfg2 & NCRCFG2_FE) 474 ? (NCR_READ_REG(sc, NCR_TCH) << 16) 475 : 0)); 476 477 if (resid == 0 && esc->sc_dmasize == 65536 && 478 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 479 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 480 resid = 65536; 481 } 482 483 trans = esc->sc_dmasize - resid; 484 if (trans < 0) { /* transferred < 0 ? */ 485 #if 0 486 /* 487 * This situation can happen in perfectly normal operation 488 * if the ESP is reselected while using DMA to select 489 * another target. As such, don't print the warning. 490 */ 491 printf("%s: xfer (%d) > req (%d)\n", 492 esc->sc_dev.dv_xname, trans, esc->sc_dmasize); 493 #endif 494 trans = esc->sc_dmasize; 495 } 496 497 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 498 NCR_READ_REG(sc, NCR_TCL), 499 NCR_READ_REG(sc, NCR_TCM), 500 (sc->sc_cfg2 & NCRCFG2_FE) 501 ? NCR_READ_REG(sc, NCR_TCH) : 0, 502 trans, resid)); 503 504 *esc->sc_dmalen -= trans; 505 *esc->sc_dmaaddr += trans; 506 507 return 0; 508 } 509 510 int 511 esp_dma_setup(sc, addr, len, datain, dmasize) 512 struct ncr53c9x_softc *sc; 513 caddr_t *addr; 514 size_t *len; 515 int datain; 516 size_t *dmasize; 517 { 518 struct esp_softc *esc = (struct esp_softc *)sc; 519 520 /* Save these in case we have to abort DMA */ 521 esc->sc_dmaaddr = addr; 522 esc->sc_dmalen = len; 523 esc->sc_dmasize = *dmasize; 524 525 DPRINTF(("esp_dma_setup(0x%08lx,0x%08lx)\n",*addr,*dmasize)); 526 527 #ifdef DIAGNOSTIC 528 if ((esc->sc_datain != -1) || 529 (esc->sc_dmamap->dm_mapsize != 0)) { 530 panic("%s: map already loaded in esp_dma_setup\n" 531 "\tdatain = %d\n\tmapsize=%d", 532 sc->sc_dev.dv_xname,esc->sc_datain,esc->sc_dmamap->dm_mapsize); 533 } 534 #endif 535 536 /* Deal with DMA alignment issues, by stuffing the FIFO. 537 * This assumes that if bus_dmamap_load is given an aligned 538 * buffer, then it will generate aligned hardware addresses 539 * to give to the device. Perhaps that is not a good assumption, 540 * but it is probably true. [dbj (at) netbsd.org:19980719.0135EDT] 541 */ 542 { 543 int slop_bgn_size; /* # bytes to be fifo'd at beginning */ 544 int slop_end_size; /* # bytes to be fifo'd at end */ 545 546 { 547 u_long bgn = (u_long)(*addr); 548 u_long end = (u_long)(*addr+*dmasize); 549 550 slop_bgn_size = DMA_BEGINALIGNMENT-(bgn % DMA_BEGINALIGNMENT); 551 if (slop_bgn_size == DMA_BEGINALIGNMENT) slop_bgn_size = 0; 552 slop_end_size = end % DMA_ENDALIGNMENT; 553 } 554 555 /* Check to make sure we haven't counted the slop twice 556 * as would happen for a very short dma buffer */ 557 if (slop_bgn_size+slop_end_size > *dmasize) { 558 #if defined(DIAGNOSTIC) 559 if ((slop_bgn_size != *dmasize) || 560 (slop_end_size != *dmasize)) { 561 panic("%s: confused alignment calculation\n" 562 "\tslop_bgn_size %d\n\tslop_end_size %d\n\tdmasize %d", 563 sc->sc_dev.dv_xname,slop_bgn_size,slop_end_size,*dmasize); 564 } 565 #endif 566 slop_end_size = 0; 567 } 568 569 if (slop_bgn_size+slop_end_size < *dmasize) { 570 int error; 571 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 572 esc->sc_dmamap, 573 *addr+slop_bgn_size, 574 *dmasize-(slop_bgn_size+slop_end_size), 575 NULL, BUS_DMA_NOWAIT); 576 if (error) { 577 panic("%s: can't load dma map. error = %d", 578 sc->sc_dev.dv_xname, error); 579 } 580 581 } else { 582 /* If there's no DMA, then coalesce the fifo buffers */ 583 slop_bgn_size += slop_end_size; 584 slop_end_size = 0; 585 } 586 587 esc->sc_slop_bgn_addr = *addr; 588 esc->sc_slop_bgn_size = slop_bgn_size; 589 esc->sc_slop_end_addr = (*addr+*dmasize)-slop_end_size; 590 esc->sc_slop_end_size = slop_end_size; 591 } 592 593 esc->sc_datain = datain; 594 595 return (0); 596 } 597 598 void 599 esp_dma_go(sc) 600 struct ncr53c9x_softc *sc; 601 { 602 struct esp_softc *esc = (struct esp_softc *)sc; 603 604 DPRINTF(("esp_dma_go(datain = %d)\n",esc->sc_datain)); 605 606 DPRINTF(("\tbgn slop = %d\n\tend slop = %d\n\tmapsize = %d\n", 607 esc->sc_slop_bgn_size,esc->sc_slop_end_size, 608 esc->sc_dmamap->dm_mapsize)); 609 610 DPRINTF(("esp fifo size = %d\n", 611 (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF))); 612 613 if (esc->sc_datain) { 614 NCR_WRITE_REG(sc, ESP_DCTL, 615 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 616 } else { 617 NCR_WRITE_REG(sc, ESP_DCTL, 618 ESPDCTL_20MHZ | ESPDCTL_INTENB); 619 } 620 621 if (esc->sc_datain) { 622 int i; 623 #ifdef DIAGNOSTIC 624 #if 0 /* This is a fine thing to happen */ 625 int n = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 626 if (n != esc->sc_slop_bgn_size) { 627 panic("%s: Unexpected data in fifo n = %d, expecting %d ", 628 sc->sc_dev.dv_xname, n, esc->sc_slop_bgn_size); 629 } 630 #endif 631 #endif 632 for(i=0;i<esc->sc_slop_bgn_size;i++) { 633 esc->sc_slop_bgn_addr[i]=NCR_READ_REG(sc, NCR_FIFO); 634 } 635 636 } else { 637 int i; 638 for(i=0;i<esc->sc_slop_bgn_size;i++) { 639 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_slop_bgn_addr[i]); 640 } 641 642 DPRINTF(("esp fifo size = %d\n", 643 (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF))); 644 } 645 646 if (esc->sc_dmamap->dm_mapsize != 0) { 647 if (esc->sc_datain) { 648 NCR_WRITE_REG(sc, ESP_DCTL, 649 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 650 } else { 651 NCR_WRITE_REG(sc, ESP_DCTL, 652 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 653 } 654 655 656 nextdma_start(&esc->sc_scsi_dma, 657 (esc->sc_datain ? DMACSR_READ : DMACSR_WRITE)); 658 } else { 659 #if defined(DIAGNOSTIC) 660 /* verify that end slop is 0, since the shutdown 661 * callback will not be called. 662 */ 663 if (esc->sc_slop_end_size != 0) { 664 panic("%s: Unexpected end slop with no DMA, slop = %d", 665 sc->sc_dev.dv_xname, esc->sc_slop_end_size); 666 } 667 #endif 668 #if 0 669 if (esc->sc_datain) { 670 NCR_WRITE_REG(sc, ESP_DCTL, 671 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD | ESPDCTL_FLUSH); 672 } else { 673 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 674 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_FLUSH); 675 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 676 } 677 #endif 678 679 esc->sc_datain = -1; 680 esc->sc_slop_bgn_addr = 0; 681 esc->sc_slop_bgn_size = 0; 682 esc->sc_slop_end_addr = 0; 683 esc->sc_slop_end_size = 0; 684 685 DPRINTF(("esp fifo size = %d\n", 686 (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF))); 687 } 688 } 689 690 void 691 esp_dma_stop(sc) 692 struct ncr53c9x_softc *sc; 693 { 694 panic("Not yet implemented"); 695 } 696 697 int 698 esp_dma_isactive(sc) 699 struct ncr53c9x_softc *sc; 700 { 701 struct esp_softc *esc = (struct esp_softc *)sc; 702 return( !nextdma_finished(&esc->sc_scsi_dma)); 703 } 704 705 /****************************************************************/ 706 707 /* Internal dma callback routines */ 708 bus_dmamap_t 709 esp_dmacb_continue(arg) 710 void *arg; 711 { 712 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 713 struct esp_softc *esc = (struct esp_softc *)sc; 714 715 DPRINTF(("esp dma continue\n")); 716 717 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap, 718 0, esc->sc_dmamap->dm_mapsize, 719 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 720 721 #ifdef DIAGNOSTIC 722 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 723 panic("%s: map not loaded in dma continue callback, datain = %d", 724 sc->sc_dev.dv_xname,esc->sc_datain); 725 } 726 #endif 727 728 return(esc->sc_dmamap); 729 } 730 731 void 732 esp_dmacb_completed(map, arg) 733 bus_dmamap_t map; 734 void *arg; 735 { 736 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 737 struct esp_softc *esc = (struct esp_softc *)sc; 738 739 DPRINTF(("esp dma completed\n")); 740 741 #ifdef DIAGNOSTIC 742 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 743 panic("%s: map not loaded in dma completed callback, datain = %d", 744 sc->sc_dev.dv_xname,esc->sc_datain); 745 } 746 if (map != esc->sc_dmamap) { 747 panic("%s: unexpected tx completed map", sc->sc_dev.dv_xname); 748 } 749 #endif 750 751 /* @@@ Flush the fifo? */ 752 753 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap, 754 0, esc->sc_dmamap->dm_mapsize, 755 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 756 } 757 758 void 759 esp_dmacb_shutdown(arg) 760 void *arg; 761 { 762 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 763 struct esp_softc *esc = (struct esp_softc *)sc; 764 765 DPRINTF(("esp dma shutdown\n")); 766 767 #ifdef DIAGNOSTIC 768 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 769 panic("%s: map not loaded in dma shutdown callback, datain = %d", 770 sc->sc_dev.dv_xname,esc->sc_datain); 771 } 772 #endif 773 774 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap); 775 776 /* Stuff the end slop into fifo */ 777 778 { 779 if (esc->sc_datain) { 780 NCR_WRITE_REG(sc, ESP_DCTL, 781 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 782 } else { 783 NCR_WRITE_REG(sc, ESP_DCTL, 784 ESPDCTL_20MHZ | ESPDCTL_INTENB); 785 } 786 787 if (esc->sc_datain) { 788 int i; 789 #ifdef DIAGNOSTIC 790 int n = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 791 if (n != esc->sc_slop_end_size) { 792 panic("%s: Unexpected data in fifo n = %d, expecting %d at end", 793 sc->sc_dev.dv_xname, n, esc->sc_slop_end_size); 794 } 795 #endif 796 for(i=0;i<esc->sc_slop_end_size;i++) { 797 esc->sc_slop_end_addr[i]=NCR_READ_REG(sc, NCR_FIFO); 798 } 799 800 } else { 801 int i; 802 for(i=0;i<esc->sc_slop_end_size;i++) { 803 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_slop_end_addr[i]); 804 } 805 } 806 } 807 808 809 esc->sc_datain = -1; 810 esc->sc_slop_bgn_addr = 0; 811 esc->sc_slop_bgn_size = 0; 812 esc->sc_slop_end_addr = 0; 813 esc->sc_slop_end_size = 0; 814 } 815
Indexes created Tue Sep 23 20:09:58 GMT 2025