esp.c revision 1.64.44.1
1 /* $NetBSD: esp.c,v 1.64.44.1 2023/02/01 18:55:11 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1994 Peter Galbavy 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Peter Galbavy 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 53 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 54 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 59 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 60 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* 65 * Based on aic6360 by Jarle Greipsland 66 * 67 * Acknowledgements: Many of the algorithms used in this driver are 68 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 69 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 70 */ 71 72 /* 73 * Grabbed from the sparc port at revision 1.73 for the NeXT. 74 * Darrin B. Jewell <dbj (at) NetBSD.org> Sat Jul 4 15:41:32 1998 75 */ 76 77 #include <sys/cdefs.h> 78 __KERNEL_RCSID(0, "$NetBSD: esp.c,v 1.64.44.1 2023/02/01 18:55:11 martin Exp $"); 79 80 #include <sys/types.h> 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/kernel.h> 84 #include <sys/errno.h> 85 #include <sys/ioctl.h> 86 #include <sys/device.h> 87 #include <sys/buf.h> 88 #include <sys/proc.h> 89 #include <sys/queue.h> 90 91 #include <uvm/uvm_extern.h> 92 93 #include <dev/scsipi/scsi_all.h> 94 #include <dev/scsipi/scsipi_all.h> 95 #include <dev/scsipi/scsiconf.h> 96 #include <dev/scsipi/scsi_message.h> 97 98 #include <machine/bus.h> 99 #include <machine/autoconf.h> 100 #include <machine/cpu.h> 101 102 #include <dev/ic/ncr53c9xreg.h> 103 #include <dev/ic/ncr53c9xvar.h> 104 105 #include <next68k/next68k/isr.h> 106 107 #include <next68k/dev/intiovar.h> 108 #include <next68k/dev/nextdmareg.h> 109 #include <next68k/dev/nextdmavar.h> 110 111 #include <next68k/dev/espreg.h> 112 #include <next68k/dev/espvar.h> 113 114 #ifdef DEBUG 115 #undef ESP_DEBUG 116 #endif 117 118 #ifdef ESP_DEBUG 119 int esp_debug = 0; 120 #define DPRINTF(x) if (esp_debug) printf x; 121 #define NDTRACEIF(x) if (10) do {x;} while (0) 122 #else 123 #define DPRINTF(x) 124 #define NDTRACEIF(x) 125 #endif 126 #define PRINTF(x) printf x; 127 128 129 int espmatch_intio(device_t, cfdata_t, void *); 130 void espattach_intio(device_t, device_t, void *); 131 132 /* DMA callbacks */ 133 bus_dmamap_t esp_dmacb_continue(void *); 134 void esp_dmacb_completed(bus_dmamap_t, void *); 135 void esp_dmacb_shutdown(void *); 136 137 static void findchannel_defer(device_t); 138 139 #ifdef ESP_DEBUG 140 char esp_dma_dump[5*1024] = ""; 141 struct ncr53c9x_softc *esp_debug_sc = 0; 142 void esp_dma_store(struct ncr53c9x_softc *); 143 void esp_dma_print(struct ncr53c9x_softc *); 144 int esp_dma_nest = 0; 145 int esptraceshow; 146 #endif 147 148 149 /* Linkup to the rest of the kernel */ 150 CFATTACH_DECL_NEW(esp, sizeof(struct esp_softc), 151 espmatch_intio, espattach_intio, NULL, NULL); 152 153 static int attached = 0; 154 155 /* 156 * Functions and the switch for the MI code. 157 */ 158 uint8_t esp_read_reg(struct ncr53c9x_softc *, int); 159 void esp_write_reg(struct ncr53c9x_softc *, int, uint8_t); 160 int esp_dma_isintr(struct ncr53c9x_softc *); 161 void esp_dma_reset(struct ncr53c9x_softc *); 162 int esp_dma_intr(struct ncr53c9x_softc *); 163 int esp_dma_setup(struct ncr53c9x_softc *, uint8_t **, size_t *, int, 164 size_t *); 165 void esp_dma_go(struct ncr53c9x_softc *); 166 void esp_dma_stop(struct ncr53c9x_softc *); 167 int esp_dma_isactive(struct ncr53c9x_softc *); 168 169 struct ncr53c9x_glue esp_glue = { 170 esp_read_reg, 171 esp_write_reg, 172 esp_dma_isintr, 173 esp_dma_reset, 174 esp_dma_intr, 175 esp_dma_setup, 176 esp_dma_go, 177 esp_dma_stop, 178 esp_dma_isactive, 179 NULL, /* gl_clear_latched_intr */ 180 }; 181 182 #ifdef ESP_DEBUG 183 #define XCHR(x) hexdigits[(x) & 0xf] 184 static void 185 esp_hex_dump(unsigned char *pkt, size_t len) 186 { 187 size_t i, j; 188 189 printf("00000000 "); 190 for(i = 0; i < len; i++) { 191 printf("%c%c ", XCHR(pkt[i]>>4), XCHR(pkt[i])); 192 if ((i + 1) % 16 == 8) { 193 printf(" "); 194 } 195 if ((i + 1) % 16 == 0) { 196 printf(" %c", '|'); 197 for(j = 0; j < 16; j++) { 198 printf("%c", pkt[i-15+j]>=32 && pkt[i-15+j]<127?pkt[i-15+j]:'.'); 199 } 200 printf("%c\n%c%c%c%c%c%c%c%c ", '|', 201 XCHR((i+1)>>28),XCHR((i+1)>>24),XCHR((i+1)>>20),XCHR((i+1)>>16), 202 XCHR((i+1)>>12), XCHR((i+1)>>8), XCHR((i+1)>>4), XCHR(i+1)); 203 } 204 } 205 printf("\n"); 206 } 207 #endif 208 209 int 210 espmatch_intio(device_t parent, cfdata_t cf, void *aux) 211 { 212 struct intio_attach_args *ia = aux; 213 214 if (attached) 215 return 0; 216 217 ia->ia_addr = (void *)NEXT_P_SCSI; 218 219 return 1; 220 } 221 222 static void 223 findchannel_defer(device_t self) 224 { 225 struct esp_softc *esc = device_private(self); 226 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 227 int error; 228 229 if (!esc->sc_dma) { 230 aprint_normal("%s", device_xname(sc->sc_dev)); 231 esc->sc_dma = nextdma_findchannel("scsi"); 232 if (!esc->sc_dma) 233 panic("%s: can't find DMA channel", 234 device_xname(sc->sc_dev)); 235 } 236 237 nextdma_setconf(esc->sc_dma, shutdown_cb, &esp_dmacb_shutdown); 238 nextdma_setconf(esc->sc_dma, continue_cb, &esp_dmacb_continue); 239 nextdma_setconf(esc->sc_dma, completed_cb, &esp_dmacb_completed); 240 nextdma_setconf(esc->sc_dma, cb_arg, sc); 241 242 error = bus_dmamap_create(esc->sc_dma->sc_dmat, 243 sc->sc_maxxfer, 244 sc->sc_maxxfer / PAGE_SIZE + 1, 245 sc->sc_maxxfer, 246 0, BUS_DMA_ALLOCNOW, &esc->sc_main_dmamap); 247 if (error) { 248 panic("%s: can't create main i/o DMA map, error = %d", 249 device_xname(sc->sc_dev), error); 250 } 251 252 error = bus_dmamap_create(esc->sc_dma->sc_dmat, 253 ESP_DMA_TAILBUFSIZE, 1, ESP_DMA_TAILBUFSIZE, 254 0, BUS_DMA_ALLOCNOW, &esc->sc_tail_dmamap); 255 if (error) { 256 panic("%s: can't create tail i/o DMA map, error = %d", 257 device_xname(sc->sc_dev), error); 258 } 259 260 #if 0 261 /* Turn on target selection using the `DMA' method */ 262 sc->sc_features |= NCR_F_DMASELECT; 263 #endif 264 265 /* Do the common parts of attachment. */ 266 sc->sc_adapter.adapt_minphys = minphys; 267 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 268 ncr53c9x_attach(sc); 269 270 /* Establish interrupt channel */ 271 isrlink_autovec(ncr53c9x_intr, sc, NEXT_I_IPL(NEXT_I_SCSI), 0, NULL); 272 INTR_ENABLE(NEXT_I_SCSI); 273 274 /* register interrupt stats */ 275 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 276 device_xname(sc->sc_dev), "intr"); 277 278 aprint_normal_dev(sc->sc_dev, "using DMA channel %s\n", 279 device_xname(esc->sc_dma->sc_dev)); 280 } 281 282 void 283 espattach_intio(device_t parent, device_t self, void *aux) 284 { 285 struct esp_softc *esc = device_private(self); 286 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 287 struct intio_attach_args *ia = aux; 288 289 sc->sc_dev = self; 290 291 #ifdef ESP_DEBUG 292 esp_debug_sc = sc; 293 #endif 294 295 esc->sc_bst = ia->ia_bst; 296 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 297 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 298 aprint_normal("\n"); 299 panic("%s: can't map ncr53c90 registers", 300 device_xname(self)); 301 } 302 303 sc->sc_id = 7; 304 sc->sc_freq = 20; /* MHz */ 305 306 /* 307 * Set up glue for MI code early; we use some of it here. 308 */ 309 sc->sc_glue = &esp_glue; 310 311 /* 312 * XXX More of this should be in ncr53c9x_attach(), but 313 * XXX should we really poke around the chip that much in 314 * XXX the MI code? Think about this more... 315 */ 316 317 /* 318 * It is necessary to try to load the 2nd config register here, 319 * to find out what rev the esp chip is, else the ncr53c9x_reset 320 * will not set up the defaults correctly. 321 */ 322 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 323 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 324 sc->sc_cfg3 = NCRCFG3_CDB; 325 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 326 327 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 328 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 329 sc->sc_rev = NCR_VARIANT_ESP100; 330 } else { 331 sc->sc_cfg2 = NCRCFG2_SCSI2; 332 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 333 sc->sc_cfg3 = 0; 334 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 335 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 336 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 337 if (NCR_READ_REG(sc, NCR_CFG3) != 338 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 339 sc->sc_rev = NCR_VARIANT_ESP100A; 340 } else { 341 /* NCRCFG2_FE enables > 64K transfers */ 342 sc->sc_cfg2 |= NCRCFG2_FE; 343 sc->sc_cfg3 = 0; 344 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 345 sc->sc_rev = NCR_VARIANT_ESP200; 346 } 347 } 348 349 /* 350 * XXX minsync and maxxfer _should_ be set up in MI code, 351 * XXX but it appears to have some dependency on what sort 352 * XXX of DMA we're hooked up to, etc. 353 */ 354 355 /* 356 * This is the value used to start sync negotiations 357 * Note that the NCR register "SYNCTP" is programmed 358 * in "clocks per byte", and has a minimum value of 4. 359 * The SCSI period used in negotiation is one-fourth 360 * of the time (in nanoseconds) needed to transfer one byte. 361 * Since the chip's clock is given in MHz, we have the following 362 * formula: 4 * period = (1000 / freq) * 4 363 */ 364 sc->sc_minsync = /* 1000 / sc->sc_freq */ 0; 365 366 /* 367 * Alas, we must now modify the value a bit, because it's 368 * only valid when can switch on FASTCLK and FASTSCSI bits 369 * in config register 3... 370 */ 371 switch (sc->sc_rev) { 372 case NCR_VARIANT_ESP100: 373 sc->sc_maxxfer = 64 * 1024; 374 sc->sc_minsync = 0; /* No synch on old chip? */ 375 break; 376 377 case NCR_VARIANT_ESP100A: 378 sc->sc_maxxfer = 64 * 1024; 379 /* Min clocks/byte is 5 */ 380 sc->sc_minsync = /* ncr53c9x_cpb2stp(sc, 5) */ 0; 381 break; 382 383 case NCR_VARIANT_ESP200: 384 sc->sc_maxxfer = 16 * 1024 * 1024; 385 /* XXX - do actually set FAST* bits */ 386 break; 387 } 388 389 /* @@@ Some ESP_DCTL bits probably need setting */ 390 NCR_WRITE_REG(sc, ESP_DCTL, 391 ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 392 DELAY(10); 393 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 394 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_16MHZ | ESPDCTL_INTENB); 395 DELAY(10); 396 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 397 398 esc->sc_dma = nextdma_findchannel ("scsi"); 399 if (esc->sc_dma) { 400 findchannel_defer(self); 401 } else { 402 aprint_normal("\n"); 403 config_defer(self, findchannel_defer); 404 } 405 406 attached = 1; 407 } 408 409 /* 410 * Glue functions. 411 */ 412 413 uint8_t 414 esp_read_reg(struct ncr53c9x_softc *sc, int reg) 415 { 416 struct esp_softc *esc = (struct esp_softc *)sc; 417 418 return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg); 419 } 420 421 void 422 esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 423 { 424 struct esp_softc *esc = (struct esp_softc *)sc; 425 426 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 427 } 428 429 volatile uint32_t save1; 430 431 #define xADDR 0x0211a000 432 int doze(volatile int); 433 int 434 doze(volatile int c) 435 { 436 /* static int tmp1; */ 437 uint32_t tmp1; 438 volatile uint8_t tmp2; 439 volatile uint8_t *reg = (volatile uint8_t *)IIOV(xADDR); 440 441 if (c > 244) 442 return 0; 443 if (c == 0) 444 return 0; 445 /* ((*(volatile u_long *)IIOV(NEXT_P_INTRMASK))&=(~NEXT_I_BIT(x))) */ 446 (*reg) = 0; 447 (*reg) = 0; 448 do { 449 save1 = (*reg); 450 tmp2 = *(reg + 3); 451 tmp1 = tmp2; 452 } while (tmp1 <= c); 453 return 0; 454 } 455 456 int 457 esp_dma_isintr(struct ncr53c9x_softc *sc) 458 { 459 struct esp_softc *esc = (struct esp_softc *)sc; 460 461 if (INTR_OCCURRED(NEXT_I_SCSI)) { 462 NDTRACEIF (ndtrace_addc('i')); 463 NCR_WRITE_REG(sc, ESP_DCTL, 464 ESPDCTL_16MHZ | ESPDCTL_INTENB | 465 (esc->sc_datain ? ESPDCTL_DMARD : 0)); 466 return 1; 467 } else { 468 return 0; 469 } 470 } 471 472 #define nd_bsr4(reg) \ 473 bus_space_read_4(nsc->sc_bst, nsc->sc_bsh, (reg)) 474 #define nd_bsw4(reg,val) \ 475 bus_space_write_4(nsc->sc_bst, nsc->sc_bsh, (reg), (val)) 476 477 int 478 esp_dma_intr(struct ncr53c9x_softc *sc) 479 { 480 struct esp_softc *esc = (struct esp_softc *)sc; 481 struct nextdma_softc *nsc = esc->sc_dma; 482 struct nextdma_status *stat = &nsc->sc_stat; 483 int r = (INTR_OCCURRED(NEXT_I_SCSI)); 484 int flushcount; 485 486 r = 1; 487 488 NDTRACEIF (ndtrace_addc('I')); 489 if (r) { 490 /* printf ("esp_dma_isintr start\n"); */ 491 { 492 int s = spldma(); 493 void *ndmap = stat->nd_map; 494 int ndidx = stat->nd_idx; 495 splx(s); 496 497 flushcount = 0; 498 499 #ifdef ESP_DEBUG 500 /* esp_dma_nest++; */ 501 502 if (esp_debug) { 503 char sbuf[256]; 504 505 snprintb(sbuf, sizeof(sbuf), NEXT_INTR_BITS, 506 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT))); 507 508 printf("esp_dma_isintr = %s\n", sbuf); 509 } 510 #endif 511 512 mutex_exit(&sc->sc_lock); /* for nextdma intr */ 513 while (!nextdma_finished(nsc)) { 514 /* esp_dma_isactive(sc)) { */ 515 NDTRACEIF (ndtrace_addc('w')); 516 NDTRACEIF ( 517 ndtrace_printf("f%dm%dl%dw", 518 NCR_READ_REG(sc, NCR_FFLAG) & 519 NCRFIFO_FF, 520 NCR_READ_REG((sc), NCR_TCM), 521 NCR_READ_REG((sc), NCR_TCL)); 522 ); 523 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) 524 flushcount = 5; 525 NCR_WRITE_REG(sc, ESP_DCTL, 526 ESPDCTL_16MHZ | ESPDCTL_INTENB | 527 ESPDCTL_DMAMOD | 528 (esc->sc_datain ? ESPDCTL_DMARD : 0)); 529 530 s = spldma(); 531 while (ndmap == stat->nd_map && 532 ndidx == stat->nd_idx && 533 (nd_bsr4 (DD_CSR) & 0x08000000) == 0&& 534 ++flushcount < 5) { 535 splx(s); 536 NDTRACEIF (ndtrace_addc('F')); 537 NCR_WRITE_REG(sc, ESP_DCTL, 538 ESPDCTL_FLUSH | ESPDCTL_16MHZ | 539 ESPDCTL_INTENB | ESPDCTL_DMAMOD | 540 (esc->sc_datain ? 541 ESPDCTL_DMARD : 0)); 542 doze(0x32); 543 NCR_WRITE_REG(sc, ESP_DCTL, 544 ESPDCTL_16MHZ | ESPDCTL_INTENB | 545 ESPDCTL_DMAMOD | 546 (esc->sc_datain ? 547 ESPDCTL_DMARD : 0)); 548 doze(0x32); 549 s = spldma(); 550 } 551 NDTRACEIF (ndtrace_addc('0' + flushcount)); 552 if (flushcount > 4) { 553 int next; 554 int onext = 0; 555 556 splx(s); 557 DPRINTF(("DMA reset\n")); 558 while (((next = nd_bsr4 (DD_NEXT)) != 559 (nd_bsr4(DD_LIMIT) & 0x7FFFFFFF)) && 560 onext != next) { 561 onext = next; 562 DELAY(50); 563 } 564 NDTRACEIF (ndtrace_addc('R')); 565 NCR_WRITE_REG(sc, ESP_DCTL, 566 ESPDCTL_16MHZ | ESPDCTL_INTENB); 567 NDTRACEIF ( 568 ndtrace_printf( 569 "ff:%d tcm:%d tcl:%d ", 570 NCR_READ_REG(sc, NCR_FFLAG) 571 & NCRFIFO_FF, 572 NCR_READ_REG((sc), NCR_TCM), 573 NCR_READ_REG((sc), 574 NCR_TCL)); 575 ); 576 s = spldma(); 577 nextdma_reset (nsc); 578 splx(s); 579 goto out; 580 } 581 splx(s); 582 583 #ifdef DIAGNOSTIC 584 if (flushcount > 4) { 585 NDTRACEIF (ndtrace_addc('+')); 586 printf("%s: unexpected flushcount" 587 " %d on %s\n", 588 device_xname(sc->sc_dev), 589 flushcount, 590 esc->sc_datain ? "read" : "write"); 591 } 592 #endif 593 594 if (!nextdma_finished(nsc)) { 595 /* esp_dma_isactive(sc)) { */ 596 NDTRACEIF (ndtrace_addc('1')); 597 } 598 flushcount = 0; 599 s = spldma(); 600 ndmap = stat->nd_map; 601 ndidx = stat->nd_idx; 602 splx(s); 603 604 } 605 out: 606 mutex_enter(&sc->sc_lock); /* for nextdma intr */ 607 608 #ifdef ESP_DEBUG 609 /* esp_dma_nest--; */ 610 #endif 611 612 } 613 614 doze(0x32); 615 NCR_WRITE_REG(sc, ESP_DCTL, 616 ESPDCTL_16MHZ | ESPDCTL_INTENB | 617 (esc->sc_datain ? ESPDCTL_DMARD : 0)); 618 NDTRACEIF (ndtrace_addc('b')); 619 620 while (esc->sc_datain != -1) 621 DELAY(50); 622 623 if (esc->sc_dmaaddr) { 624 bus_size_t xfer_len = 0; 625 int resid; 626 627 NCR_WRITE_REG(sc, ESP_DCTL, 628 ESPDCTL_16MHZ | ESPDCTL_INTENB); 629 if (stat->nd_exception == 0) { 630 resid = NCR_READ_REG((sc), NCR_TCL) + 631 (NCR_READ_REG((sc), NCR_TCM) << 8); 632 if (resid) { 633 resid += (NCR_READ_REG(sc, NCR_FFLAG) & 634 NCRFIFO_FF); 635 #ifdef ESP_DEBUG 636 if (NCR_READ_REG(sc, NCR_FFLAG) & 637 NCRFIFO_FF) 638 if ((NCR_READ_REG(sc, 639 NCR_FFLAG) & NCRFIFO_FF) != 640 16 || 641 NCR_READ_REG((sc), 642 NCR_TCL) != 240) 643 esptraceshow++; 644 #endif 645 } 646 xfer_len = esc->sc_dmasize - resid; 647 } else { 648 #define ncr53c9x_sched_msgout(m) \ 649 do { \ 650 NCR_MISC(("ncr53c9x_sched_msgout %x %d", m, __LINE__)); \ 651 NCRCMD(sc, NCRCMD_SETATN); \ 652 sc->sc_flags |= NCR_ATN; \ 653 sc->sc_msgpriq |= (m); \ 654 } while (0) 655 int i; 656 657 xfer_len = 0; 658 if (esc->sc_begin) 659 xfer_len += esc->sc_begin_size; 660 if (esc->sc_main_dmamap) 661 xfer_len += 662 esc->sc_main_dmamap->dm_xfer_len; 663 if (esc->sc_tail_dmamap) 664 xfer_len += 665 esc->sc_tail_dmamap->dm_xfer_len; 666 resid = 0; 667 printf ("X\n"); 668 for (i = 0; i < 16; i++) { 669 NCR_WRITE_REG(sc, ESP_DCTL, 670 ESPDCTL_FLUSH | ESPDCTL_16MHZ | 671 ESPDCTL_INTENB | 672 (esc->sc_datain ? 673 ESPDCTL_DMARD : 0)); 674 NCR_WRITE_REG(sc, ESP_DCTL, 675 ESPDCTL_16MHZ | ESPDCTL_INTENB | 676 (esc->sc_datain ? 677 ESPDCTL_DMARD : 0)); 678 } 679 #if 0 680 printf ("ff:%02x tcm:%d tcl:%d esp_dstat:%02x" 681 " stat:%02x step: %02x intr:%02x" 682 " new stat:%02X\n", 683 NCR_READ_REG(sc, NCR_FFLAG), 684 NCR_READ_REG((sc), NCR_TCM), 685 NCR_READ_REG((sc), NCR_TCL), 686 NCR_READ_REG(sc, ESP_DSTAT), 687 sc->sc_espstat, sc->sc_espstep, 688 sc->sc_espintr, 689 NCR_READ_REG(sc, NCR_STAT)); 690 printf("sc->sc_state: %x sc->sc_phase: %x" 691 " sc->sc_espstep:%x sc->sc_prevphase:%x" 692 " sc->sc_flags:%x\n", 693 sc->sc_state, sc->sc_phase, sc->sc_espstep, 694 sc->sc_prevphase, sc->sc_flags); 695 #endif 696 /* sc->sc_flags &= ~NCR_ICCS; */ 697 sc->sc_nexus->flags |= ECB_ABORT; 698 if (sc->sc_phase == MESSAGE_IN_PHASE) { 699 /* ncr53c9x_sched_msgout(SEND_ABORT); */ 700 ncr53c9x_abort(sc, sc->sc_nexus); 701 } else if (sc->sc_phase != STATUS_PHASE) { 702 printf("ATTENTION!!! " 703 "not message/status phase: %d\n", 704 sc->sc_phase); 705 } 706 } 707 708 NDTRACEIF( 709 ndtrace_printf("f%dm%dl%ds%dx%dr%dS", 710 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF, 711 NCR_READ_REG((sc), NCR_TCM), 712 NCR_READ_REG((sc), NCR_TCL), 713 esc->sc_dmasize, (int)xfer_len, resid); 714 ); 715 716 *esc->sc_dmaaddr += xfer_len; 717 *esc->sc_dmalen -= xfer_len; 718 esc->sc_dmaaddr = 0; 719 esc->sc_dmalen = 0; 720 esc->sc_dmasize = 0; 721 } 722 723 NDTRACEIF (ndtrace_addc('B')); 724 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT) | 725 (sc->sc_espstat & NCRSTAT_INT); 726 727 DPRINTF(("esp dctl is 0x%02x\n", NCR_READ_REG(sc, ESP_DCTL))); 728 /* printf ("esp_dma_isintr DONE\n"); */ 729 730 } 731 732 return r; 733 } 734 735 void 736 esp_dma_reset(struct ncr53c9x_softc *sc) 737 { 738 struct esp_softc *esc = (struct esp_softc *)sc; 739 740 DPRINTF(("esp DMA reset\n")); 741 742 #ifdef ESP_DEBUG 743 if (esp_debug) { 744 char sbuf[256]; 745 746 snprintb(sbuf, sizeof(sbuf), NEXT_INTR_BITS, 747 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT))); 748 printf(" *intrstat = %s\n", sbuf); 749 750 snprintb(sbuf, sizeof(sbuf), NEXT_INTR_BITS, 751 (*(volatile u_long *)IIOV(NEXT_P_INTRMASK))); 752 printf(" *intrmask = %s\n", sbuf); 753 } 754 #endif 755 756 #if 0 757 /* Clear the DMAMOD bit in the DCTL register: */ 758 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_16MHZ | ESPDCTL_INTENB); 759 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 760 #endif 761 762 nextdma_reset(esc->sc_dma); 763 nextdma_init(esc->sc_dma); 764 765 esc->sc_datain = -1; 766 esc->sc_dmaaddr = 0; 767 esc->sc_dmalen = 0; 768 esc->sc_dmasize = 0; 769 770 esc->sc_loaded = 0; 771 772 esc->sc_begin = 0; 773 esc->sc_begin_size = 0; 774 775 if (esc->sc_main_dmamap->dm_mapsize) { 776 bus_dmamap_unload(esc->sc_dma->sc_dmat, esc->sc_main_dmamap); 777 } 778 esc->sc_main = 0; 779 esc->sc_main_size = 0; 780 781 if (esc->sc_tail_dmamap->dm_mapsize) { 782 bus_dmamap_unload(esc->sc_dma->sc_dmat, esc->sc_tail_dmamap); 783 } 784 esc->sc_tail = 0; 785 esc->sc_tail_size = 0; 786 } 787 788 /* it appears that: 789 * addr and len arguments to this need to be kept up to date 790 * with the status of the transfter. 791 * the dmasize of this is the actual length of the transfer 792 * request, which is guaranteed to be less than maxxfer. 793 * (len may be > maxxfer) 794 */ 795 796 int 797 esp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 798 int datain, size_t *dmasize) 799 { 800 struct esp_softc *esc = (struct esp_softc *)sc; 801 802 NDTRACEIF (ndtrace_addc('h')); 803 #ifdef DIAGNOSTIC 804 #ifdef ESP_DEBUG 805 /* if this is a read DMA, pre-fill the buffer with 0xdeadbeef 806 * to identify bogus reads 807 */ 808 if (datain) { 809 int *v = (int *)(*addr); 810 int i; 811 for (i = 0; i < ((*len) / 4); i++) 812 v[i] = 0xdeadbeef; 813 v = (int *)(&(esc->sc_tailbuf[0])); 814 for (i = 0; i < ((sizeof(esc->sc_tailbuf) / 4)); i++) 815 v[i] = 0xdeafbeef; 816 } else { 817 int *v; 818 int i; 819 v = (int *)(&(esc->sc_tailbuf[0])); 820 for (i = 0; i < ((sizeof(esc->sc_tailbuf) / 4)); i++) 821 v[i] = 0xfeeb1eed; 822 } 823 #endif 824 #endif 825 826 DPRINTF(("esp_dma_setup(%p,0x%08x,0x%08x)\n", *addr, *len, *dmasize)); 827 828 #if 0 829 #ifdef DIAGNOSTIC /* @@@ this is ok sometimes. verify that we handle it ok 830 * and then remove this check 831 */ 832 if (*len != *dmasize) { 833 panic("esp dmalen 0x%lx != size 0x%lx", *len, *dmasize); 834 } 835 #endif 836 #endif 837 838 #ifdef DIAGNOSTIC 839 if ((esc->sc_datain != -1) || 840 (esc->sc_main_dmamap->dm_mapsize != 0) || 841 (esc->sc_tail_dmamap->dm_mapsize != 0) || 842 (esc->sc_dmasize != 0)) { 843 panic("%s: map already loaded in esp_dma_setup" 844 "\tdatain = %d\n\tmain_mapsize=%ld\n" 845 "\tail_mapsize=%ld\n\tdmasize = %d", 846 device_xname(sc->sc_dev), esc->sc_datain, 847 esc->sc_main_dmamap->dm_mapsize, 848 esc->sc_tail_dmamap->dm_mapsize, 849 esc->sc_dmasize); 850 } 851 #endif 852 853 /* we are sometimes asked to DMA zero bytes, that's easy */ 854 if (*dmasize <= 0) { 855 return 0; 856 } 857 858 if (*dmasize > ESP_MAX_DMASIZE) 859 *dmasize = ESP_MAX_DMASIZE; 860 861 /* Save these in case we have to abort DMA */ 862 esc->sc_datain = datain; 863 esc->sc_dmaaddr = addr; 864 esc->sc_dmalen = len; 865 esc->sc_dmasize = *dmasize; 866 867 esc->sc_loaded = 0; 868 869 #define DMA_SCSI_ALIGNMENT 16 870 #define DMA_SCSI_ALIGN(type, addr) \ 871 ((type)(((unsigned int)(addr) + DMA_SCSI_ALIGNMENT - 1) \ 872 &~(DMA_SCSI_ALIGNMENT-1))) 873 #define DMA_SCSI_ALIGNED(addr) \ 874 (((unsigned int)(addr) & (DMA_SCSI_ALIGNMENT - 1))==0) 875 876 { 877 size_t slop_bgn_size; /* # bytes to be fifo'd at beginning */ 878 size_t slop_end_size; /* # bytes to be transferred in tail buffer */ 879 880 { 881 u_long bgn = (u_long)(*esc->sc_dmaaddr); 882 u_long end = bgn + esc->sc_dmasize; 883 884 slop_bgn_size = 885 DMA_SCSI_ALIGNMENT - (bgn % DMA_SCSI_ALIGNMENT); 886 if (slop_bgn_size == DMA_SCSI_ALIGNMENT) 887 slop_bgn_size = 0; 888 slop_end_size = end % DMA_ENDALIGNMENT; 889 } 890 891 /* Force a minimum slop end size. This ensures that write 892 * requests will overrun, as required to get completion 893 * interrupts. 894 * In addition, since the tail buffer is guaranteed to be mapped 895 * in a single DMA segment, the overrun won't accidentally 896 * end up in its own segment. 897 */ 898 if (!esc->sc_datain) { 899 #if 0 900 slop_end_size += ESP_DMA_MAXTAIL; 901 #else 902 slop_end_size += 0x10; 903 #endif 904 } 905 906 /* Check to make sure we haven't counted extra slop 907 * as would happen for a very short DMA buffer, also 908 * for short buffers, just stuff the entire thing in the tail 909 */ 910 if ((slop_bgn_size+slop_end_size >= esc->sc_dmasize) 911 #if 0 912 || (esc->sc_dmasize <= ESP_DMA_MAXTAIL) 913 #endif 914 ) { 915 slop_bgn_size = 0; 916 slop_end_size = esc->sc_dmasize; 917 } 918 919 /* initialize the fifo buffer */ 920 if (slop_bgn_size) { 921 esc->sc_begin = *esc->sc_dmaaddr; 922 esc->sc_begin_size = slop_bgn_size; 923 } else { 924 esc->sc_begin = 0; 925 esc->sc_begin_size = 0; 926 } 927 928 #if 01 929 /* Load the normal DMA map */ 930 { 931 esc->sc_main = *esc->sc_dmaaddr; 932 esc->sc_main += slop_bgn_size; 933 esc->sc_main_size = 934 (esc->sc_dmasize) - (slop_end_size+slop_bgn_size); 935 936 if (esc->sc_main_size) { 937 int error; 938 939 if (!esc->sc_datain || 940 DMA_ENDALIGNED(esc->sc_main_size + 941 slop_end_size)) { 942 KASSERT(DMA_SCSI_ALIGNMENT == 943 DMA_ENDALIGNMENT); 944 KASSERT(DMA_BEGINALIGNMENT == 945 DMA_ENDALIGNMENT); 946 esc->sc_main_size += slop_end_size; 947 slop_end_size = 0; 948 if (!esc->sc_datain) { 949 esc->sc_main_size = 950 DMA_ENDALIGN(uint8_t *, 951 esc->sc_main + 952 esc->sc_main_size) - 953 esc->sc_main; 954 } 955 } 956 957 error = bus_dmamap_load(esc->sc_dma->sc_dmat, 958 esc->sc_main_dmamap, 959 esc->sc_main, esc->sc_main_size, 960 NULL, BUS_DMA_NOWAIT); 961 if (error) { 962 #ifdef ESP_DEBUG 963 printf("%s: esc->sc_main_dmamap->" 964 "_dm_size = %ld\n", 965 device_xname(sc->sc_dev), 966 esc->sc_main_dmamap->_dm_size); 967 printf("%s: esc->sc_main_dmamap->" 968 "_dm_segcnt = %d\n", 969 device_xname(sc->sc_dev), 970 esc->sc_main_dmamap->_dm_segcnt); 971 #ifdef notdef 972 printf("%s: esc->sc_main_dmamap->" 973 "_dm_maxsegsz = %ld\n", 974 device_xname(sc->sc_dev), 975 esc->sc_main_dmamap->_dm_maxsegsz); 976 #endif 977 printf("%s: esc->sc_main_dmamap->" 978 "_dm_boundary = %ld\n", 979 device_xname(sc->sc_dev), 980 esc->sc_main_dmamap->_dm_boundary); 981 esp_dma_print(sc); 982 #endif 983 panic("%s: can't load main DMA map." 984 " error = %d, addr=%p, size=0x%08x", 985 device_xname(sc->sc_dev), 986 error, esc->sc_main, 987 esc->sc_main_size); 988 } 989 if (!esc->sc_datain) { 990 /* 991 * patch the DMA map for write overrun 992 */ 993 esc->sc_main_dmamap->dm_mapsize += 994 ESP_DMA_OVERRUN; 995 esc->sc_main_dmamap->dm_segs[ 996 esc->sc_main_dmamap->dm_nsegs - 997 1].ds_len += 998 ESP_DMA_OVERRUN; 999 } 1000 #if 0 1001 bus_dmamap_sync(esc->sc_dma->sc_dmat, 1002 esc->sc_main_dmamap, 1003 0, esc->sc_main_dmamap->dm_mapsize, 1004 (esc->sc_datain ? BUS_DMASYNC_PREREAD : 1005 BUS_DMASYNC_PREWRITE)); 1006 esc->sc_main_dmamap->dm_xfer_len = 0; 1007 #endif 1008 } else { 1009 esc->sc_main = 0; 1010 } 1011 } 1012 1013 /* Load the tail DMA map */ 1014 if (slop_end_size) { 1015 esc->sc_tail = DMA_ENDALIGN(uint8_t *, 1016 esc->sc_tailbuf + slop_end_size) - slop_end_size; 1017 /* 1018 * If the beginning of the tail is not correctly 1019 * aligned, we have no choice but to align the start, 1020 * which might then unalign the end. 1021 */ 1022 esc->sc_tail = DMA_SCSI_ALIGN(uint8_t *, esc->sc_tail); 1023 /* 1024 * So therefore, we change the tail size to be 1025 * end aligned again. 1026 */ 1027 esc->sc_tail_size = DMA_ENDALIGN(uint8_t *, 1028 esc->sc_tail + slop_end_size) - esc->sc_tail; 1029 1030 /* @@@ next DMA overrun lossage */ 1031 if (!esc->sc_datain) { 1032 esc->sc_tail_size += ESP_DMA_OVERRUN; 1033 } 1034 1035 { 1036 int error; 1037 error = bus_dmamap_load(esc->sc_dma->sc_dmat, 1038 esc->sc_tail_dmamap, 1039 esc->sc_tail, esc->sc_tail_size, 1040 NULL, BUS_DMA_NOWAIT); 1041 if (error) { 1042 panic("%s: can't load tail DMA map." 1043 " error = %d, addr=%p, size=0x%08x", 1044 device_xname(sc->sc_dev), error, 1045 esc->sc_tail,esc->sc_tail_size); 1046 } 1047 #if 0 1048 bus_dmamap_sync(esc->sc_dma->sc_dmat, 1049 esc->sc_tail_dmamap, 0, 1050 esc->sc_tail_dmamap->dm_mapsize, 1051 (esc->sc_datain ? BUS_DMASYNC_PREREAD : 1052 BUS_DMASYNC_PREWRITE)); 1053 esc->sc_tail_dmamap->dm_xfer_len = 0; 1054 #endif 1055 } 1056 } 1057 #else 1058 1059 esc->sc_begin = *esc->sc_dmaaddr; 1060 slop_bgn_size = DMA_SCSI_ALIGNMENT - 1061 ((u_long)esc->sc_begin % DMA_SCSI_ALIGNMENT); 1062 if (slop_bgn_size == DMA_SCSI_ALIGNMENT) 1063 slop_bgn_size = 0; 1064 slop_end_size = esc->sc_dmasize - slop_bgn_size; 1065 1066 if (slop_bgn_size < esc->sc_dmasize) { 1067 int error; 1068 1069 esc->sc_tail = 0; 1070 esc->sc_tail_size = 0; 1071 1072 esc->sc_begin_size = slop_bgn_size; 1073 esc->sc_main = *esc->sc_dmaaddr; 1074 esc->sc_main += slop_bgn_size; 1075 esc->sc_main_size = DMA_ENDALIGN(uint8_t *, 1076 esc->sc_main + esc->sc_dmasize - slop_bgn_size) - 1077 esc->sc_main; 1078 1079 if (!esc->sc_datain) { 1080 esc->sc_main_size += ESP_DMA_OVERRUN; 1081 } 1082 error = bus_dmamap_load(esc->sc_dma->sc_dmat, 1083 esc->sc_main_dmamap, 1084 esc->sc_main, esc->sc_main_size, 1085 NULL, BUS_DMA_NOWAIT); 1086 if (error) { 1087 panic("%s: can't load main DMA map." 1088 " error = %d, addr=%p, size=0x%08x", 1089 device_xname(sc->sc_dev), error, 1090 esc->sc_main,esc->sc_main_size); 1091 } 1092 } else { 1093 esc->sc_begin = 0; 1094 esc->sc_begin_size = 0; 1095 esc->sc_main = 0; 1096 esc->sc_main_size = 0; 1097 1098 #if 0 1099 esc->sc_tail = DMA_ENDALIGN(uint8_t *, 1100 esc->sc_tailbuf + slop_bgn_size) - slop_bgn_size; 1101 /* 1102 * If the beginning of the tail is not correctly 1103 * aligned, we have no choice but to align the start, 1104 * which might then unalign the end. 1105 */ 1106 #endif 1107 esc->sc_tail = DMA_SCSI_ALIGN(void *, esc->sc_tailbuf); 1108 /* 1109 * So therefore, we change the tail size to be 1110 * end aligned again. 1111 */ 1112 esc->sc_tail_size = DMA_ENDALIGN(uint8_t *, 1113 esc->sc_tail + esc->sc_dmasize) - esc->sc_tail; 1114 1115 /* @@@ next DMA overrun lossage */ 1116 if (!esc->sc_datain) { 1117 esc->sc_tail_size += ESP_DMA_OVERRUN; 1118 } 1119 1120 { 1121 int error; 1122 error = bus_dmamap_load(esc->sc_dma->sc_dmat, 1123 esc->sc_tail_dmamap, 1124 esc->sc_tail, esc->sc_tail_size, 1125 NULL, BUS_DMA_NOWAIT); 1126 if (error) { 1127 panic("%s: can't load tail DMA map." 1128 " error = %d, addr=%p, size=0x%08x", 1129 device_xname(sc->sc_dev), error, 1130 esc->sc_tail, esc->sc_tail_size); 1131 } 1132 } 1133 } 1134 #endif 1135 1136 DPRINTF(("%s: setup: %8p %d %8p %d %8p %d %8p %d\n", 1137 device_xname(sc->sc_dev), 1138 *esc->sc_dmaaddr, esc->sc_dmasize, 1139 esc->sc_begin, esc->sc_begin_size, 1140 esc->sc_main, esc->sc_main_size, 1141 esc->sc_tail, esc->sc_tail_size)); 1142 } 1143 1144 return 0; 1145 } 1146 1147 #ifdef ESP_DEBUG 1148 /* For debugging */ 1149 void 1150 esp_dma_store(struct ncr53c9x_softc *sc) 1151 { 1152 struct esp_softc *esc = (struct esp_softc *)sc; 1153 char *p = esp_dma_dump; 1154 size_t l = 0; 1155 size_t len = sizeof(esp_dma_dump); 1156 1157 l += snprintf(p + l, len - l, "%s: sc_datain=%d\n", 1158 device_xname(sc->sc_dev), esc->sc_datain); 1159 if (l > len) 1160 return; 1161 l += snprintf(p + l, len - l, "%s: sc_loaded=0x%08x\n", 1162 device_xname(sc->sc_dev), esc->sc_loaded); 1163 if (l > len) 1164 return; 1165 1166 if (esc->sc_dmaaddr) { 1167 l += snprintf(p + l, len - l, "%s: sc_dmaaddr=%p\n", 1168 device_xname(sc->sc_dev), *esc->sc_dmaaddr); 1169 } else { 1170 l += snprintf(p + l, len - l, "%s: sc_dmaaddr=NULL\n", 1171 device_xname(sc->sc_dev)); 1172 } 1173 if (l > len) 1174 return; 1175 if (esc->sc_dmalen) { 1176 l += snprintf(p + l, len - l, "%s: sc_dmalen=0x%08x\n", 1177 device_xname(sc->sc_dev), *esc->sc_dmalen); 1178 } else { 1179 l += snprintf(p + l, len - l, "%s: sc_dmalen=NULL\n", 1180 device_xname(sc->sc_dev)); 1181 } 1182 if (l > len) 1183 return; 1184 l += snprintf(p + l, len - l, "%s: sc_dmasize=0x%08x\n", 1185 device_xname(sc->sc_dev), esc->sc_dmasize); 1186 if (l > len) 1187 return; 1188 1189 l += snprintf(p + l, len - l, "%s: sc_begin = %p, sc_begin_size = 0x%08x\n", 1190 device_xname(sc->sc_dev), esc->sc_begin, esc->sc_begin_size); 1191 if (l > len) 1192 return; 1193 l += snprintf(p + l, len - l, "%s: sc_main = %p, sc_main_size = 0x%08x\n", 1194 device_xname(sc->sc_dev), esc->sc_main, esc->sc_main_size); 1195 if (l > len) 1196 return; 1197 /* if (esc->sc_main) */ { 1198 int i; 1199 bus_dmamap_t map = esc->sc_main_dmamap; 1200 l += snprintf(p + l, len - l, "%s: sc_main_dmamap." 1201 " mapsize = 0x%08lx, nsegs = %d\n", 1202 device_xname(sc->sc_dev), map->dm_mapsize, map->dm_nsegs); 1203 if (l > len) 1204 return; 1205 for(i = 0; i < map->dm_nsegs; i++) { 1206 l += snprintf(p + l, len - l, "%s:" 1207 " map->dm_segs[%d].ds_addr = 0x%08lx," 1208 " len = 0x%08lx\n", 1209 device_xname(sc->sc_dev), 1210 i, map->dm_segs[i].ds_addr, 1211 map->dm_segs[i].ds_len); 1212 if (l > len) 1213 return; 1214 } 1215 } 1216 l += snprintf(p + l, len - l, "%s: sc_tail = %p, sc_tail_size = 0x%08x\n", 1217 device_xname(sc->sc_dev), esc->sc_tail, esc->sc_tail_size); 1218 if (l > len) 1219 return; 1220 /* if (esc->sc_tail) */ { 1221 int i; 1222 bus_dmamap_t map = esc->sc_tail_dmamap; 1223 l += snprintf(p + l, len - l, "%s: sc_tail_dmamap." 1224 " mapsize = 0x%08lx, nsegs = %d\n", 1225 device_xname(sc->sc_dev), map->dm_mapsize, map->dm_nsegs); 1226 if (l > len) 1227 return; 1228 for (i = 0; i < map->dm_nsegs; i++) { 1229 l += snprintf(p + l, len - l, "%s:" 1230 " map->dm_segs[%d].ds_addr = 0x%08lx," 1231 " len = 0x%08lx\n", 1232 device_xname(sc->sc_dev), 1233 i, map->dm_segs[i].ds_addr, 1234 map->dm_segs[i].ds_len); 1235 if (l > len) 1236 return; 1237 } 1238 } 1239 } 1240 1241 void 1242 esp_dma_print(struct ncr53c9x_softc *sc) 1243 { 1244 1245 esp_dma_store(sc); 1246 printf("%s", esp_dma_dump); 1247 } 1248 #endif 1249 1250 void 1251 esp_dma_go(struct ncr53c9x_softc *sc) 1252 { 1253 struct esp_softc *esc = (struct esp_softc *)sc; 1254 struct nextdma_softc *nsc = esc->sc_dma; 1255 struct nextdma_status *stat = &nsc->sc_stat; 1256 /* int s = spldma(); */ 1257 1258 #ifdef ESP_DEBUG 1259 if (!ndtrace_empty()) { 1260 if (esptraceshow) { 1261 printf("esp ndtrace: %s\n", ndtrace_get()); 1262 esptraceshow = 0; 1263 } else { 1264 DPRINTF(("X")); 1265 } 1266 ndtrace_reset(); 1267 } 1268 #endif 1269 1270 DPRINTF(("%s: esp_dma_go(datain = %d)\n", 1271 device_xname(sc->sc_dev), esc->sc_datain)); 1272 1273 #ifdef ESP_DEBUG 1274 if (esp_debug) 1275 esp_dma_print(sc); 1276 else 1277 esp_dma_store(sc); 1278 #endif 1279 1280 #ifdef ESP_DEBUG 1281 { 1282 int n = NCR_READ_REG(sc, NCR_FFLAG); 1283 DPRINTF(("%s: fifo size = %d, seq = 0x%x\n", 1284 device_xname(sc->sc_dev), 1285 n & NCRFIFO_FF, (n & NCRFIFO_SS) >> 5)); 1286 } 1287 #endif 1288 1289 /* zero length DMA transfers are boring */ 1290 if (esc->sc_dmasize == 0) { 1291 /* splx(s); */ 1292 return; 1293 } 1294 1295 #if defined(DIAGNOSTIC) 1296 if ((esc->sc_begin_size == 0) && 1297 (esc->sc_main_dmamap->dm_mapsize == 0) && 1298 (esc->sc_tail_dmamap->dm_mapsize == 0)) { 1299 #ifdef ESP_DEBUG 1300 esp_dma_print(sc); 1301 #endif 1302 panic("%s: No DMA requested!", device_xname(sc->sc_dev)); 1303 } 1304 #endif 1305 1306 /* Stuff the fifo with the begin buffer */ 1307 if (esc->sc_datain) { 1308 int i; 1309 DPRINTF(("%s: FIFO read of %d bytes:", 1310 device_xname(sc->sc_dev), esc->sc_begin_size)); 1311 for (i = 0; i < esc->sc_begin_size; i++) { 1312 esc->sc_begin[i] = NCR_READ_REG(sc, NCR_FIFO); 1313 DPRINTF((" %02x", esc->sc_begin[i] & 0xff)); 1314 } 1315 DPRINTF(("\n")); 1316 } else { 1317 int i; 1318 DPRINTF(("%s: FIFO write of %d bytes:", 1319 device_xname(sc->sc_dev), esc->sc_begin_size)); 1320 for (i = 0; i < esc->sc_begin_size; i++) { 1321 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_begin[i]); 1322 DPRINTF((" %02x",esc->sc_begin[i] & 0xff)); 1323 } 1324 DPRINTF(("\n")); 1325 } 1326 1327 if (esc->sc_main_dmamap->dm_mapsize) { 1328 bus_dmamap_sync(esc->sc_dma->sc_dmat, esc->sc_main_dmamap, 1329 0, esc->sc_main_dmamap->dm_mapsize, 1330 (esc->sc_datain ? 1331 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1332 esc->sc_main_dmamap->dm_xfer_len = 0; 1333 } 1334 1335 if (esc->sc_tail_dmamap->dm_mapsize) { 1336 /* if we are a DMA write cycle, copy the end slop */ 1337 if (!esc->sc_datain) { 1338 memcpy(esc->sc_tail, *esc->sc_dmaaddr + 1339 esc->sc_begin_size+esc->sc_main_size, 1340 esc->sc_dmasize - 1341 (esc->sc_begin_size + esc->sc_main_size)); 1342 } 1343 bus_dmamap_sync(esc->sc_dma->sc_dmat, esc->sc_tail_dmamap, 1344 0, esc->sc_tail_dmamap->dm_mapsize, 1345 (esc->sc_datain ? 1346 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1347 esc->sc_tail_dmamap->dm_xfer_len = 0; 1348 } 1349 1350 stat->nd_exception = 0; 1351 nextdma_start(nsc, (esc->sc_datain ? DMACSR_SETREAD : DMACSR_SETWRITE)); 1352 1353 if (esc->sc_datain) { 1354 NCR_WRITE_REG(sc, ESP_DCTL, 1355 ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | 1356 ESPDCTL_DMARD); 1357 } else { 1358 NCR_WRITE_REG(sc, ESP_DCTL, 1359 ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 1360 } 1361 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL))); 1362 1363 NDTRACEIF( 1364 if (esc->sc_begin_size) { 1365 ndtrace_addc('1'); 1366 ndtrace_addc('A' + esc->sc_begin_size); 1367 } 1368 ); 1369 NDTRACEIF( 1370 if (esc->sc_main_size) { 1371 ndtrace_addc('2'); 1372 ndtrace_addc('0' + esc->sc_main_dmamap->dm_nsegs); 1373 } 1374 ); 1375 NDTRACEIF( 1376 if (esc->sc_tail_size) { 1377 ndtrace_addc('3'); 1378 ndtrace_addc('A' + esc->sc_tail_size); 1379 } 1380 ); 1381 1382 /* splx(s); */ 1383 } 1384 1385 void 1386 esp_dma_stop(struct ncr53c9x_softc *sc) 1387 { 1388 struct esp_softc *esc = (struct esp_softc *)sc; 1389 1390 nextdma_print(esc->sc_dma); 1391 #ifdef ESP_DEBUG 1392 esp_dma_print(sc); 1393 #endif 1394 #if 1 1395 panic("%s: stop not yet implemented", device_xname(sc->sc_dev)); 1396 #endif 1397 } 1398 1399 int 1400 esp_dma_isactive(struct ncr53c9x_softc *sc) 1401 { 1402 struct esp_softc *esc = (struct esp_softc *)sc; 1403 int r; 1404 1405 r = (esc->sc_dmaaddr != NULL); /* !nextdma_finished(esc->sc_dma); */ 1406 DPRINTF(("esp_dma_isactive = %d\n",r)); 1407 return r; 1408 } 1409 1410 /****************************************************************/ 1411 1412 int esp_dma_int(void *); 1413 int esp_dma_int(void *arg) 1414 { 1415 void nextdma_rotate(struct nextdma_softc *); 1416 void nextdma_setup_curr_regs(struct nextdma_softc *); 1417 void nextdma_setup_cont_regs(struct nextdma_softc *); 1418 1419 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1420 struct esp_softc *esc = (struct esp_softc *)sc; 1421 struct nextdma_softc *nsc = esc->sc_dma; 1422 struct nextdma_status *stat = &nsc->sc_stat; 1423 unsigned int state; 1424 1425 NDTRACEIF (ndtrace_addc('E')); 1426 1427 state = nd_bsr4 (DD_CSR); 1428 1429 #if 1 1430 NDTRACEIF ( 1431 if (state & DMACSR_COMPLETE) 1432 ndtrace_addc('c'); 1433 if (state & DMACSR_ENABLE) 1434 ndtrace_addc('e'); 1435 if (state & DMACSR_BUSEXC) 1436 ndtrace_addc('b'); 1437 if (state & DMACSR_READ) 1438 ndtrace_addc('r'); 1439 if (state & DMACSR_SUPDATE) 1440 ndtrace_addc('s'); 1441 ); 1442 1443 NDTRACEIF (ndtrace_addc('E')); 1444 1445 #ifdef ESP_DEBUG 1446 if (0) 1447 if ((state & DMACSR_BUSEXC) && (state & DMACSR_ENABLE)) 1448 esptraceshow++; 1449 if (0) 1450 if ((state & DMACSR_SUPDATE)) 1451 esptraceshow++; 1452 #endif 1453 #endif 1454 1455 if ((stat->nd_exception == 0) && 1456 (state & DMACSR_COMPLETE) && 1457 (state & DMACSR_ENABLE)) { 1458 stat->nd_map->dm_xfer_len += 1459 stat->nd_map->dm_segs[stat->nd_idx].ds_len; 1460 } 1461 1462 if ((stat->nd_idx + 1) == stat->nd_map->dm_nsegs) { 1463 if (nsc->sc_conf.nd_completed_cb) 1464 (*nsc->sc_conf.nd_completed_cb)(stat->nd_map, 1465 nsc->sc_conf.nd_cb_arg); 1466 } 1467 nextdma_rotate(nsc); 1468 1469 if ((state & DMACSR_COMPLETE) && (state & DMACSR_ENABLE)) { 1470 #if 0 1471 int l = nd_bsr4 (DD_LIMIT) & 0x7FFFFFFF; 1472 int s = nd_bsr4 (DD_STOP); 1473 #endif 1474 /* nextdma_setup_cont_regs(nsc); */ 1475 if (stat->nd_map_cont) { 1476 nd_bsw4(DD_START, stat->nd_map_cont->dm_segs[ 1477 stat->nd_idx_cont].ds_addr); 1478 nd_bsw4(DD_STOP, (stat->nd_map_cont->dm_segs[ 1479 stat->nd_idx_cont].ds_addr + 1480 stat->nd_map_cont->dm_segs[ 1481 stat->nd_idx_cont].ds_len)); 1482 } 1483 1484 nd_bsw4 (DD_CSR, DMACSR_CLRCOMPLETE | 1485 (state & DMACSR_READ ? DMACSR_SETREAD : DMACSR_SETWRITE) | 1486 (stat->nd_map_cont ? DMACSR_SETSUPDATE : 0)); 1487 1488 #if 0 1489 #ifdef ESP_DEBUG 1490 if (state & DMACSR_BUSEXC) { 1491 ndtrace_printf("CE/BUSEXC: %08lX %08X %08X\n", 1492 (stat->nd_map->dm_segs[stat->nd_idx].ds_addr + 1493 stat->nd_map->dm_segs[stat->nd_idx].ds_len), 1494 l, s); 1495 } 1496 #endif 1497 #endif 1498 } else { 1499 #if 0 1500 if (state & DMACSR_BUSEXC) { 1501 while (nd_bsr4(DD_NEXT) != 1502 (nd_bsr4(DD_LIMIT) & 0x7FFFFFFF)) 1503 printf("Y"); /* DELAY(50); */ 1504 state = nd_bsr4(DD_CSR); 1505 } 1506 #endif 1507 1508 if (!(state & DMACSR_SUPDATE)) { 1509 nextdma_rotate(nsc); 1510 } else { 1511 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE | 1512 DMACSR_INITBUF | DMACSR_RESET | 1513 (state & DMACSR_READ ? 1514 DMACSR_SETREAD : DMACSR_SETWRITE)); 1515 1516 nd_bsw4(DD_NEXT, 1517 stat->nd_map->dm_segs[stat->nd_idx].ds_addr); 1518 nd_bsw4(DD_LIMIT, 1519 (stat->nd_map->dm_segs[stat->nd_idx].ds_addr + 1520 stat->nd_map->dm_segs[stat->nd_idx].ds_len) | 1521 0/* x80000000 */); 1522 if (stat->nd_map_cont) { 1523 nd_bsw4(DD_START, 1524 stat->nd_map_cont->dm_segs[ 1525 stat->nd_idx_cont].ds_addr); 1526 nd_bsw4(DD_STOP, 1527 (stat->nd_map_cont->dm_segs[ 1528 stat->nd_idx_cont].ds_addr + 1529 stat->nd_map_cont->dm_segs[ 1530 stat->nd_idx_cont].ds_len) | 1531 0/* x80000000 */); 1532 } 1533 nd_bsw4(DD_CSR, DMACSR_SETENABLE | DMACSR_CLRCOMPLETE | 1534 (state & DMACSR_READ ? 1535 DMACSR_SETREAD : DMACSR_SETWRITE) | 1536 (stat->nd_map_cont ? DMACSR_SETSUPDATE : 0)); 1537 #if 1 1538 #ifdef ESP_DEBUG 1539 ndtrace_printf("supdate "); 1540 ndtrace_printf("%08X %08X %08X %08X ", 1541 nd_bsr4(DD_NEXT), 1542 nd_bsr4(DD_LIMIT) & 0x7FFFFFFF, 1543 nd_bsr4 (DD_START), 1544 nd_bsr4 (DD_STOP) & 0x7FFFFFFF); 1545 #endif 1546 #endif 1547 stat->nd_exception++; 1548 return 1; 1549 /* NCR_WRITE_REG(sc, ESP_DCTL, ctl); */ 1550 goto restart; 1551 } 1552 1553 if (stat->nd_map) { 1554 #if 1 1555 #ifdef ESP_DEBUG 1556 ndtrace_printf("%08X %08X %08X %08X ", 1557 nd_bsr4 (DD_NEXT), 1558 nd_bsr4 (DD_LIMIT) & 0x7FFFFFFF, 1559 nd_bsr4 (DD_START), 1560 nd_bsr4 (DD_STOP) & 0x7FFFFFFF); 1561 #endif 1562 #endif 1563 1564 #if 0 1565 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE | DMACSR_RESET); 1566 1567 nd_bsw4(DD_CSR, 0); 1568 #endif 1569 #if 1 1570 /* 6/2 */ 1571 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE | 1572 DMACSR_INITBUF | DMACSR_RESET | 1573 (state & DMACSR_READ ? 1574 DMACSR_SETREAD : DMACSR_SETWRITE)); 1575 1576 /* nextdma_setup_curr_regs(nsc); */ 1577 nd_bsw4(DD_NEXT, 1578 stat->nd_map->dm_segs[stat->nd_idx].ds_addr); 1579 nd_bsw4(DD_LIMIT, 1580 (stat->nd_map->dm_segs[stat->nd_idx].ds_addr + 1581 stat->nd_map->dm_segs[stat->nd_idx].ds_len) | 1582 0/* x80000000 */); 1583 /* nextdma_setup_cont_regs(nsc); */ 1584 if (stat->nd_map_cont) { 1585 nd_bsw4(DD_START, 1586 stat->nd_map_cont->dm_segs[ 1587 stat->nd_idx_cont].ds_addr); 1588 nd_bsw4(DD_STOP, 1589 (stat->nd_map_cont->dm_segs[ 1590 stat->nd_idx_cont].ds_addr + 1591 stat->nd_map_cont->dm_segs[ 1592 stat->nd_idx_cont].ds_len) | 1593 0/* x80000000 */); 1594 } 1595 1596 nd_bsw4(DD_CSR, DMACSR_SETENABLE | 1597 (stat->nd_map_cont ? DMACSR_SETSUPDATE : 0) | 1598 (state & DMACSR_READ ? 1599 DMACSR_SETREAD : DMACSR_SETWRITE)); 1600 #ifdef ESP_DEBUG 1601 /* esptraceshow++; */ 1602 #endif 1603 stat->nd_exception++; 1604 return 1; 1605 #endif 1606 /* NCR_WRITE_REG(sc, ESP_DCTL, ctl); */ 1607 goto restart; 1608 restart: 1609 #if 1 1610 #ifdef ESP_DEBUG 1611 ndtrace_printf("restart %08lX %08lX\n", 1612 stat->nd_map->dm_segs[stat->nd_idx].ds_addr, 1613 stat->nd_map->dm_segs[stat->nd_idx].ds_addr + 1614 stat->nd_map->dm_segs[stat->nd_idx].ds_len); 1615 if (stat->nd_map_cont) { 1616 ndtrace_printf(" %08lX %08lX\n", 1617 stat->nd_map_cont->dm_segs[ 1618 stat->nd_idx_cont].ds_addr, 1619 stat->nd_map_cont->dm_segs[ 1620 stat->nd_idx_cont].ds_addr + 1621 stat->nd_map_cont->dm_segs[ 1622 stat->nd_idx_cont].ds_len); 1623 } 1624 #endif 1625 #endif 1626 nextdma_print(nsc); 1627 NCR_WRITE_REG(sc, ESP_DCTL, 1628 ESPDCTL_16MHZ | ESPDCTL_INTENB); 1629 printf("ff:%02x tcm:%d tcl:%d esp_dstat:%02x" 1630 " state:%02x step: %02x intr:%02x state:%08X\n", 1631 NCR_READ_REG(sc, NCR_FFLAG), 1632 NCR_READ_REG((sc), NCR_TCM), 1633 NCR_READ_REG((sc), NCR_TCL), 1634 NCR_READ_REG(sc, ESP_DSTAT), 1635 NCR_READ_REG(sc, NCR_STAT), 1636 NCR_READ_REG(sc, NCR_STEP), 1637 NCR_READ_REG(sc, NCR_INTR), state); 1638 #ifdef ESP_DEBUG 1639 printf("ndtrace: %s\n", ndtrace_get()); 1640 #endif 1641 panic("%s: busexc/supdate occurred." 1642 " Please email this output to chris (at) pin.lu.", 1643 device_xname(sc->sc_dev)); 1644 #ifdef ESP_DEBUG 1645 esptraceshow++; 1646 #endif 1647 } else { 1648 nd_bsw4(DD_CSR, DMACSR_CLRCOMPLETE | DMACSR_RESET); 1649 if (nsc->sc_conf.nd_shutdown_cb) 1650 (*nsc->sc_conf.nd_shutdown_cb)(nsc->sc_conf.nd_cb_arg); 1651 } 1652 } 1653 return 1; 1654 } 1655 1656 /* Internal DMA callback routines */ 1657 bus_dmamap_t 1658 esp_dmacb_continue(void *arg) 1659 { 1660 struct ncr53c9x_softc *sc = arg; 1661 struct esp_softc *esc = (struct esp_softc *)sc; 1662 1663 NDTRACEIF (ndtrace_addc('x')); 1664 DPRINTF(("%s: DMA continue\n", device_xname(sc->sc_dev))); 1665 1666 #ifdef DIAGNOSTIC 1667 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 1668 panic("%s: map not loaded in DMA continue callback," 1669 " datain = %d", 1670 device_xname(sc->sc_dev), esc->sc_datain); 1671 } 1672 #endif 1673 1674 if (((esc->sc_loaded & ESP_LOADED_MAIN) == 0) && 1675 (esc->sc_main_dmamap->dm_mapsize)) { 1676 DPRINTF(("%s: Loading main map\n", device_xname(sc->sc_dev))); 1677 #if 0 1678 bus_dmamap_sync(esc->sc_dma->sc_dmat, esc->sc_main_dmamap, 1679 0, esc->sc_main_dmamap->dm_mapsize, 1680 (esc->sc_datain ? 1681 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1682 esc->sc_main_dmamap->dm_xfer_len = 0; 1683 #endif 1684 esc->sc_loaded |= ESP_LOADED_MAIN; 1685 return esc->sc_main_dmamap; 1686 } 1687 1688 if (((esc->sc_loaded & ESP_LOADED_TAIL) == 0) && 1689 (esc->sc_tail_dmamap->dm_mapsize)) { 1690 DPRINTF(("%s: Loading tail map\n", device_xname(sc->sc_dev))); 1691 #if 0 1692 bus_dmamap_sync(esc->sc_dma->sc_dmat, esc->sc_tail_dmamap, 1693 0, esc->sc_tail_dmamap->dm_mapsize, 1694 (esc->sc_datain ? 1695 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1696 esc->sc_tail_dmamap->dm_xfer_len = 0; 1697 #endif 1698 esc->sc_loaded |= ESP_LOADED_TAIL; 1699 return esc->sc_tail_dmamap; 1700 } 1701 1702 DPRINTF(("%s: not loading map\n", device_xname(sc->sc_dev))); 1703 return 0; 1704 } 1705 1706 1707 void 1708 esp_dmacb_completed(bus_dmamap_t map, void *arg) 1709 { 1710 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1711 struct esp_softc *esc = (struct esp_softc *)sc; 1712 1713 NDTRACEIF (ndtrace_addc('X')); 1714 DPRINTF(("%s: DMA completed\n", device_xname(sc->sc_dev))); 1715 1716 #ifdef DIAGNOSTIC 1717 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 1718 panic("%s: invalid DMA direction in completed callback," 1719 " datain = %d", 1720 device_xname(sc->sc_dev), esc->sc_datain); 1721 } 1722 #endif 1723 1724 #if defined(DIAGNOSTIC) && 0 1725 { 1726 int i; 1727 for(i = 0; i < map->dm_nsegs; i++) { 1728 if (map->dm_xfer_len != map->dm_mapsize) { 1729 printf("%s: map->dm_mapsize = %d\n", 1730 device_xname(sc->sc_dev), map->dm_mapsize); 1731 printf("%s: map->dm_nsegs = %d\n", 1732 device_xname(sc->sc_dev), map->dm_nsegs); 1733 printf("%s: map->dm_xfer_len = %d\n", 1734 device_xname(sc->sc_dev), map->dm_xfer_len); 1735 for(i = 0; i < map->dm_nsegs; i++) { 1736 printf("%s: map->dm_segs[%d].ds_addr =" 1737 " 0x%08lx\n", 1738 device_xname(sc->sc_dev), i, 1739 map->dm_segs[i].ds_addr); 1740 printf("%s: map->dm_segs[%d].ds_len =" 1741 " %d\n", 1742 device_xname(sc->sc_dev), i, 1743 map->dm_segs[i].ds_len); 1744 } 1745 panic("%s: incomplete DMA transfer", 1746 device_xname(sc->sc_dev)); 1747 } 1748 } 1749 } 1750 #endif 1751 1752 if (map == esc->sc_main_dmamap) { 1753 #ifdef DIAGNOSTIC 1754 if ((esc->sc_loaded & ESP_UNLOADED_MAIN) || 1755 (esc->sc_loaded & ESP_LOADED_MAIN) == 0) { 1756 panic("%s: unexpected completed call for main map", 1757 device_xname(sc->sc_dev)); 1758 } 1759 #endif 1760 esc->sc_loaded |= ESP_UNLOADED_MAIN; 1761 } else if (map == esc->sc_tail_dmamap) { 1762 #ifdef DIAGNOSTIC 1763 if ((esc->sc_loaded & ESP_UNLOADED_TAIL) || 1764 (esc->sc_loaded & ESP_LOADED_TAIL) == 0) { 1765 panic("%s: unexpected completed call for tail map", 1766 device_xname(sc->sc_dev)); 1767 } 1768 #endif 1769 esc->sc_loaded |= ESP_UNLOADED_TAIL; 1770 } 1771 #ifdef DIAGNOSTIC 1772 else { 1773 panic("%s: unexpected completed map", device_xname(sc->sc_dev)); 1774 } 1775 #endif 1776 1777 #ifdef ESP_DEBUG 1778 if (esp_debug) { 1779 if (map == esc->sc_main_dmamap) { 1780 printf("%s: completed main map\n", 1781 device_xname(sc->sc_dev)); 1782 } else if (map == esc->sc_tail_dmamap) { 1783 printf("%s: completed tail map\n", 1784 device_xname(sc->sc_dev)); 1785 } 1786 } 1787 #endif 1788 1789 #if 0 1790 if ((map == esc->sc_tail_dmamap) || 1791 ((esc->sc_tail_size == 0) && (map == esc->sc_main_dmamap))) { 1792 1793 /* 1794 * Clear the DMAMOD bit in the DCTL register to give control 1795 * back to the scsi chip. 1796 */ 1797 if (esc->sc_datain) { 1798 NCR_WRITE_REG(sc, ESP_DCTL, 1799 ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 1800 } else { 1801 NCR_WRITE_REG(sc, ESP_DCTL, 1802 ESPDCTL_16MHZ | ESPDCTL_INTENB); 1803 } 1804 DPRINTF(("esp dctl is 0x%02x\n", NCR_READ_REG(sc, ESP_DCTL))); 1805 } 1806 #endif 1807 1808 1809 #if 0 1810 bus_dmamap_sync(esc->sc_dma->sc_dmat, map, 1811 0, map->dm_mapsize, 1812 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1813 #endif 1814 1815 } 1816 1817 void 1818 esp_dmacb_shutdown(void *arg) 1819 { 1820 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 1821 struct esp_softc *esc = (struct esp_softc *)sc; 1822 1823 NDTRACEIF (ndtrace_addc('S')); 1824 DPRINTF(("%s: DMA shutdown\n", device_xname(sc->sc_dev))); 1825 1826 if (esc->sc_loaded == 0) 1827 return; 1828 1829 #if 0 1830 { 1831 /* Clear the DMAMOD bit in the DCTL register to give control 1832 * back to the scsi chip. 1833 */ 1834 if (esc->sc_datain) { 1835 NCR_WRITE_REG(sc, ESP_DCTL, 1836 ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 1837 } else { 1838 NCR_WRITE_REG(sc, ESP_DCTL, 1839 ESPDCTL_16MHZ | ESPDCTL_INTENB); 1840 } 1841 DPRINTF(("esp dctl is 0x%02x\n", NCR_READ_REG(sc, ESP_DCTL))); 1842 } 1843 #endif 1844 1845 DPRINTF(("%s: esp_dma_nest == %d\n", 1846 device_xname(sc->sc_dev), esp_dma_nest)); 1847 1848 /* Stuff the end slop into fifo */ 1849 1850 #ifdef ESP_DEBUG 1851 if (esp_debug) { 1852 int n = NCR_READ_REG(sc, NCR_FFLAG); 1853 1854 DPRINTF(("%s: fifo size = %d, seq = 0x%x\n", 1855 device_xname(sc->sc_dev), n & NCRFIFO_FF, 1856 (n & NCRFIFO_SS) >> 5)); 1857 } 1858 #endif 1859 1860 if (esc->sc_main_dmamap->dm_mapsize) { 1861 if (!esc->sc_datain) { 1862 /* unpatch the DMA map for write overrun */ 1863 esc->sc_main_dmamap->dm_mapsize -= ESP_DMA_OVERRUN; 1864 esc->sc_main_dmamap->dm_segs[ 1865 esc->sc_main_dmamap->dm_nsegs - 1].ds_len -= 1866 ESP_DMA_OVERRUN; 1867 } 1868 bus_dmamap_sync(esc->sc_dma->sc_dmat, esc->sc_main_dmamap, 1869 0, esc->sc_main_dmamap->dm_mapsize, 1870 (esc->sc_datain ? 1871 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1872 bus_dmamap_unload(esc->sc_dma->sc_dmat, esc->sc_main_dmamap); 1873 NDTRACEIF ( 1874 ndtrace_printf("m%ld", 1875 esc->sc_main_dmamap->dm_xfer_len); 1876 ); 1877 } 1878 1879 if (esc->sc_tail_dmamap->dm_mapsize) { 1880 bus_dmamap_sync(esc->sc_dma->sc_dmat, esc->sc_tail_dmamap, 1881 0, esc->sc_tail_dmamap->dm_mapsize, 1882 (esc->sc_datain ? 1883 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 1884 bus_dmamap_unload(esc->sc_dma->sc_dmat, esc->sc_tail_dmamap); 1885 /* copy the tail DMA buffer data for read transfers */ 1886 if (esc->sc_datain) { 1887 memcpy(*esc->sc_dmaaddr + esc->sc_begin_size + 1888 esc->sc_main_size, esc->sc_tail, 1889 esc->sc_dmasize - 1890 (esc->sc_begin_size + esc->sc_main_size)); 1891 } 1892 NDTRACEIF ( 1893 ndtrace_printf("t%ld", 1894 esc->sc_tail_dmamap->dm_xfer_len); 1895 ); 1896 } 1897 1898 #ifdef ESP_DEBUG 1899 if (esp_debug) { 1900 printf("%s: dma_shutdown: addr=%p,len=0x%08x,size=0x%08x\n", 1901 device_xname(sc->sc_dev), 1902 *esc->sc_dmaaddr, *esc->sc_dmalen, esc->sc_dmasize); 1903 if (esp_debug > 10) { 1904 esp_hex_dump(*(esc->sc_dmaaddr), esc->sc_dmasize); 1905 printf("%s: tail=%p,tailbuf=%p,tail_size=0x%08x\n", 1906 device_xname(sc->sc_dev), 1907 esc->sc_tail, &(esc->sc_tailbuf[0]), 1908 esc->sc_tail_size); 1909 esp_hex_dump(&(esc->sc_tailbuf[0]), 1910 sizeof(esc->sc_tailbuf)); 1911 } 1912 } 1913 #endif 1914 1915 esc->sc_main = 0; 1916 esc->sc_main_size = 0; 1917 esc->sc_tail = 0; 1918 esc->sc_tail_size = 0; 1919 1920 esc->sc_datain = -1; 1921 /* esc->sc_dmaaddr = 0; */ 1922 /* esc->sc_dmalen = 0; */ 1923 /* esc->sc_dmasize = 0; */ 1924 1925 esc->sc_loaded = 0; 1926 1927 esc->sc_begin = 0; 1928 esc->sc_begin_size = 0; 1929 1930 #ifdef ESP_DEBUG 1931 if (esp_debug) { 1932 char sbuf[256]; 1933 1934 snprintb(sbuf, sizeof(sbuf), NEXT_INTR_BITS, 1935 (*(volatile u_long *)IIOV(NEXT_P_INTRSTAT))); 1936 printf(" *intrstat = %s\n", sbuf); 1937 1938 snprintb(sbuf, sizeof(sbuf), NEXT_INTR_BITS, 1939 (*(volatile u_long *)IIOV(NEXT_P_INTRMASK))); 1940 printf(" *intrmask = %s\n", sbuf); 1941 } 1942 #endif 1943 } 1944
Indexes created Sat Oct 11 16:09:52 GMT 2025