esp.c revision 1.7
1 /* $NetBSD: esp.c,v 1.7 1998/09/05 15:31:42 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Grabbed from the sparc port at revision 1.73 for the NeXT. 81 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 82 */ 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/device.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 #include <sys/user.h> 94 #include <sys/queue.h> 95 96 #include <dev/scsipi/scsi_all.h> 97 #include <dev/scsipi/scsipi_all.h> 98 #include <dev/scsipi/scsiconf.h> 99 #include <dev/scsipi/scsi_message.h> 100 101 #include <machine/bus.h> 102 #include <machine/autoconf.h> 103 #include <machine/cpu.h> 104 105 #include <dev/ic/ncr53c9xreg.h> 106 #include <dev/ic/ncr53c9xvar.h> 107 108 #include <next68k/next68k/isr.h> 109 110 #include <next68k/dev/nextdmareg.h> 111 #include <next68k/dev/nextdmavar.h> 112 113 #include "espreg.h" 114 #include "espvar.h" 115 116 #if 1 117 #define ESP_DEBUG 118 #endif 119 120 #ifdef ESP_DEBUG 121 #define DPRINTF(x) printf x; 122 #else 123 #define DPRINTF(x) 124 #endif 125 126 127 void espattach_intio __P((struct device *, struct device *, void *)); 128 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 129 130 /* DMA callbacks */ 131 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 132 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 133 void esp_dmacb_shutdown __P((void *arg)); 134 135 /* Linkup to the rest of the kernel */ 136 struct cfattach esp_ca = { 137 sizeof(struct esp_softc), espmatch_intio, espattach_intio 138 }; 139 140 struct scsipi_adapter esp_switch = { 141 ncr53c9x_scsi_cmd, 142 minphys, /* no max at this level; handled by DMA code */ 143 NULL, 144 NULL, 145 }; 146 147 struct scsipi_device esp_dev = { 148 NULL, /* Use default error handler */ 149 NULL, /* have a queue, served by this */ 150 NULL, /* have no async handler */ 151 NULL, /* Use default 'done' routine */ 152 }; 153 154 /* 155 * Functions and the switch for the MI code. 156 */ 157 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 158 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 159 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 160 void esp_dma_reset __P((struct ncr53c9x_softc *)); 161 int esp_dma_intr __P((struct ncr53c9x_softc *)); 162 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 163 size_t *, int, size_t *)); 164 void esp_dma_go __P((struct ncr53c9x_softc *)); 165 void esp_dma_stop __P((struct ncr53c9x_softc *)); 166 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 167 168 struct ncr53c9x_glue esp_glue = { 169 esp_read_reg, 170 esp_write_reg, 171 esp_dma_isintr, 172 esp_dma_reset, 173 esp_dma_intr, 174 esp_dma_setup, 175 esp_dma_go, 176 esp_dma_stop, 177 esp_dma_isactive, 178 NULL, /* gl_clear_latched_intr */ 179 }; 180 181 int 182 espmatch_intio(parent, cf, aux) 183 struct device *parent; 184 struct cfdata *cf; 185 void *aux; 186 { 187 /* should probably probe here */ 188 /* Should also probably set up data from config */ 189 190 #if 1 191 /* this code isn't working yet, don't match on it */ 192 return(0); 193 #else 194 return(1); 195 #endif 196 } 197 198 void 199 espattach_intio(parent, self, aux) 200 struct device *parent, *self; 201 void *aux; 202 { 203 struct esp_softc *esc = (void *)self; 204 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 205 206 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 207 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 208 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 209 panic("\n%s: can't map ncr53c90 registers", 210 sc->sc_dev.dv_xname); 211 } 212 213 sc->sc_id = 7; 214 sc->sc_freq = 20; /* Mhz */ 215 216 /* 217 * Set up glue for MI code early; we use some of it here. 218 */ 219 sc->sc_glue = &esp_glue; 220 221 /* 222 * XXX More of this should be in ncr53c9x_attach(), but 223 * XXX should we really poke around the chip that much in 224 * XXX the MI code? Think about this more... 225 */ 226 227 /* 228 * It is necessary to try to load the 2nd config register here, 229 * to find out what rev the esp chip is, else the ncr53c9x_reset 230 * will not set up the defaults correctly. 231 */ 232 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 233 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 234 sc->sc_cfg3 = NCRCFG3_CDB; 235 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 236 237 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 238 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 239 sc->sc_rev = NCR_VARIANT_ESP100; 240 } else { 241 sc->sc_cfg2 = NCRCFG2_SCSI2; 242 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 243 sc->sc_cfg3 = 0; 244 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 245 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 246 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 247 if (NCR_READ_REG(sc, NCR_CFG3) != 248 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 249 sc->sc_rev = NCR_VARIANT_ESP100A; 250 } else { 251 /* NCRCFG2_FE enables > 64K transfers */ 252 sc->sc_cfg2 |= NCRCFG2_FE; 253 sc->sc_cfg3 = 0; 254 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 255 sc->sc_rev = NCR_VARIANT_ESP200; 256 } 257 } 258 259 /* 260 * XXX minsync and maxxfer _should_ be set up in MI code, 261 * XXX but it appears to have some dependency on what sort 262 * XXX of DMA we're hooked up to, etc. 263 */ 264 265 /* 266 * This is the value used to start sync negotiations 267 * Note that the NCR register "SYNCTP" is programmed 268 * in "clocks per byte", and has a minimum value of 4. 269 * The SCSI period used in negotiation is one-fourth 270 * of the time (in nanoseconds) needed to transfer one byte. 271 * Since the chip's clock is given in MHz, we have the following 272 * formula: 4 * period = (1000 / freq) * 4 273 */ 274 sc->sc_minsync = 1000 / sc->sc_freq; 275 276 /* 277 * Alas, we must now modify the value a bit, because it's 278 * only valid when can switch on FASTCLK and FASTSCSI bits 279 * in config register 3... 280 */ 281 switch (sc->sc_rev) { 282 case NCR_VARIANT_ESP100: 283 sc->sc_maxxfer = 64 * 1024; 284 sc->sc_minsync = 0; /* No synch on old chip? */ 285 break; 286 287 case NCR_VARIANT_ESP100A: 288 sc->sc_maxxfer = 64 * 1024; 289 /* Min clocks/byte is 5 */ 290 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 291 break; 292 293 case NCR_VARIANT_ESP200: 294 sc->sc_maxxfer = 16 * 1024 * 1024; 295 /* XXX - do actually set FAST* bits */ 296 break; 297 } 298 299 /* @@@ Some ESP_DCTL bits probably need setting */ 300 NCR_WRITE_REG(sc, ESP_DCTL, 301 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 302 DELAY(10); 303 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 304 DELAY(10); 305 306 /* Set up SCSI DMA */ 307 { 308 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 309 310 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 311 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 312 panic("\n%s: can't map scsi DMA registers", 313 sc->sc_dev.dv_xname); 314 } 315 316 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 317 esc->sc_scsi_dma.nd_chaining_flag = 0; 318 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 319 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 320 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 321 esc->sc_scsi_dma.nd_cb_arg = sc; 322 nextdma_config(&esc->sc_scsi_dma); 323 nextdma_init(&esc->sc_scsi_dma); 324 325 { 326 int error; 327 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 328 sc->sc_maxxfer, 1, sc->sc_maxxfer, 329 0, BUS_DMA_ALLOCNOW, &esc->sc_dmamap)) != 0) { 330 panic("%s: can't create i/o DMA map, error = %d", 331 sc->sc_dev.dv_xname,error); 332 } 333 } 334 } 335 336 #if 0 337 /* Turn on target selection using the `dma' method */ 338 ncr53c9x_dmaselect = 1; 339 #else 340 ncr53c9x_dmaselect = 0; 341 #endif 342 343 esc->sc_slop_bgn_addr = 0; 344 esc->sc_slop_bgn_size = 0; 345 esc->sc_slop_end_addr = 0; 346 esc->sc_slop_end_size = 0; 347 esc->sc_datain = -1; 348 349 /* Establish interrupt channel */ 350 isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc, 351 NEXT_I_IPL(NEXT_I_SCSI), 0); 352 INTR_ENABLE(NEXT_I_SCSI); 353 354 /* register interrupt stats */ 355 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 356 357 /* Do the common parts of attachment. */ 358 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 359 } 360 361 /* 362 * Glue functions. 363 */ 364 365 u_char 366 esp_read_reg(sc, reg) 367 struct ncr53c9x_softc *sc; 368 int reg; 369 { 370 struct esp_softc *esc = (struct esp_softc *)sc; 371 372 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 373 } 374 375 void 376 esp_write_reg(sc, reg, val) 377 struct ncr53c9x_softc *sc; 378 int reg; 379 u_char val; 380 { 381 struct esp_softc *esc = (struct esp_softc *)sc; 382 383 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 384 } 385 386 int 387 esp_dma_isintr(sc) 388 struct ncr53c9x_softc *sc; 389 { 390 struct esp_softc *esc = (struct esp_softc *)sc; 391 392 int r = (INTR_OCCURRED(NEXT_I_SCSI)); 393 394 if (r) { 395 DPRINTF(("esp_dma_isintr = %d\n",r)); 396 397 if (esc->sc_datain) { 398 NCR_WRITE_REG(sc, ESP_DCTL, 399 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 400 } else { 401 NCR_WRITE_REG(sc, ESP_DCTL, 402 ESPDCTL_20MHZ | ESPDCTL_INTENB); 403 } 404 } 405 406 return (r); 407 } 408 409 void 410 esp_dma_reset(sc) 411 struct ncr53c9x_softc *sc; 412 { 413 struct esp_softc *esc = (struct esp_softc *)sc; 414 415 nextdma_reset(&esc->sc_scsi_dma); 416 417 if (esc->sc_dmamap->dm_mapsize != 0) { 418 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap); 419 } 420 421 esc->sc_slop_bgn_addr = 0; 422 esc->sc_slop_bgn_size = 0; 423 esc->sc_slop_end_addr = 0; 424 esc->sc_slop_end_size = 0; 425 esc->sc_datain = -1; 426 } 427 428 int 429 esp_dma_intr(sc) 430 struct ncr53c9x_softc *sc; 431 { 432 int trans; 433 int resid; 434 int datain; 435 struct esp_softc *esc = (struct esp_softc *)sc; 436 437 datain = esc->sc_datain; 438 439 DPRINTF(("esp_dma_intr resetting dma\n")); 440 441 /* If the dma hasn't finished when we are in a scsi 442 * interrupt. Then, "Houston, we have a problem." 443 * Stop DMA and figure out how many bytes were transferred 444 */ 445 esp_dma_reset(sc); 446 447 resid = 0; 448 449 /* 450 * If a transfer onto the SCSI bus gets interrupted by the device 451 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 452 * as residual since the ESP counter registers get decremented as 453 * bytes are clocked into the FIFO. 454 */ 455 456 if (! datain) { 457 resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 458 if (resid) { 459 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 460 NCRCMD(sc, NCRCMD_FLUSH); 461 DELAY(1); 462 } 463 } 464 465 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 466 /* 467 * `Terminal count' is off, so read the residue 468 * out of the ESP counter registers. 469 */ 470 resid += (NCR_READ_REG(sc, NCR_TCL) | 471 (NCR_READ_REG(sc, NCR_TCM) << 8) | 472 ((sc->sc_cfg2 & NCRCFG2_FE) 473 ? (NCR_READ_REG(sc, NCR_TCH) << 16) 474 : 0)); 475 476 if (resid == 0 && esc->sc_dmasize == 65536 && 477 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 478 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 479 resid = 65536; 480 } 481 482 trans = esc->sc_dmasize - resid; 483 if (trans < 0) { /* transferred < 0 ? */ 484 #if 0 485 /* 486 * This situation can happen in perfectly normal operation 487 * if the ESP is reselected while using DMA to select 488 * another target. As such, don't print the warning. 489 */ 490 printf("%s: xfer (%d) > req (%d)\n", 491 esc->sc_dev.dv_xname, trans, esc->sc_dmasize); 492 #endif 493 trans = esc->sc_dmasize; 494 } 495 496 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 497 NCR_READ_REG(sc, NCR_TCL), 498 NCR_READ_REG(sc, NCR_TCM), 499 (sc->sc_cfg2 & NCRCFG2_FE) 500 ? NCR_READ_REG(sc, NCR_TCH) : 0, 501 trans, resid)); 502 503 *esc->sc_dmalen -= trans; 504 *esc->sc_dmaaddr += trans; 505 506 return 0; 507 } 508 509 int 510 esp_dma_setup(sc, addr, len, datain, dmasize) 511 struct ncr53c9x_softc *sc; 512 caddr_t *addr; 513 size_t *len; 514 int datain; 515 size_t *dmasize; 516 { 517 struct esp_softc *esc = (struct esp_softc *)sc; 518 519 /* Save these in case we have to abort DMA */ 520 esc->sc_dmaaddr = addr; 521 esc->sc_dmalen = len; 522 esc->sc_dmasize = *dmasize; 523 524 DPRINTF(("esp_dma_setup(0x%08lx,0x%08lx)\n",*addr,*dmasize)); 525 526 #ifdef DIAGNOSTIC 527 if ((esc->sc_datain != -1) || 528 (esc->sc_dmamap->dm_mapsize != 0)) { 529 panic("%s: map already loaded in esp_dma_setup\n" 530 "\tdatain = %d\n\tmapsize=%d", 531 sc->sc_dev.dv_xname,esc->sc_datain,esc->sc_dmamap->dm_mapsize); 532 } 533 #endif 534 535 /* Deal with DMA alignment issues, by stuffing the FIFO. 536 * This assumes that if bus_dmamap_load is given an aligned 537 * buffer, then it will generate aligned hardware addresses 538 * to give to the device. Perhaps that is not a good assumption, 539 * but it is probably true. [dbj (at) netbsd.org:19980719.0135EDT] 540 */ 541 { 542 int slop_bgn_size; /* # bytes to be fifo'd at beginning */ 543 int slop_end_size; /* # bytes to be fifo'd at end */ 544 545 { 546 u_long bgn = (u_long)(*addr); 547 u_long end = (u_long)(*addr+*dmasize); 548 549 slop_bgn_size = DMA_BEGINALIGNMENT-(bgn % DMA_BEGINALIGNMENT); 550 if (slop_bgn_size == DMA_BEGINALIGNMENT) slop_bgn_size = 0; 551 slop_end_size = end % DMA_ENDALIGNMENT; 552 } 553 554 /* Check to make sure we haven't counted the slop twice 555 * as would happen for a very short dma buffer */ 556 if (slop_bgn_size+slop_end_size > *dmasize) { 557 #if defined(DIAGNOSTIC) 558 if ((slop_bgn_size != *dmasize) || 559 (slop_end_size != *dmasize)) { 560 panic("%s: confused alignment calculation\n" 561 "\tslop_bgn_size %d\n\tslop_end_size %d\n\tdmasize %d", 562 sc->sc_dev.dv_xname,slop_bgn_size,slop_end_size,*dmasize); 563 } 564 #endif 565 slop_end_size = 0; 566 } 567 568 if (slop_bgn_size+slop_end_size < *dmasize) { 569 int error; 570 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 571 esc->sc_dmamap, 572 *addr+slop_bgn_size, 573 *dmasize-(slop_bgn_size+slop_end_size), 574 NULL, BUS_DMA_NOWAIT); 575 if (error) { 576 panic("%s: can't load dma map. error = %d", 577 sc->sc_dev.dv_xname, error); 578 } 579 580 } else { 581 /* If there's no DMA, then coalesce the fifo buffers */ 582 slop_bgn_size += slop_end_size; 583 slop_end_size = 0; 584 } 585 586 esc->sc_slop_bgn_addr = *addr; 587 esc->sc_slop_bgn_size = slop_bgn_size; 588 esc->sc_slop_end_addr = (*addr+*dmasize)-slop_end_size; 589 esc->sc_slop_end_size = slop_end_size; 590 } 591 592 esc->sc_datain = datain; 593 594 return (0); 595 } 596 597 void 598 esp_dma_go(sc) 599 struct ncr53c9x_softc *sc; 600 { 601 struct esp_softc *esc = (struct esp_softc *)sc; 602 603 DPRINTF(("esp_dma_go(datain = %d)\n",esc->sc_datain)); 604 605 DPRINTF(("\tbgn slop = %d\n\tend slop = %d\n\tmapsize = %d\n", 606 esc->sc_slop_bgn_size,esc->sc_slop_end_size, 607 esc->sc_dmamap->dm_mapsize)); 608 609 DPRINTF(("esp fifo size = %d\n", 610 (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF))); 611 612 if (esc->sc_datain) { 613 NCR_WRITE_REG(sc, ESP_DCTL, 614 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 615 } else { 616 NCR_WRITE_REG(sc, ESP_DCTL, 617 ESPDCTL_20MHZ | ESPDCTL_INTENB); 618 } 619 620 if (esc->sc_datain) { 621 int i; 622 #ifdef DIAGNOSTIC 623 #if 0 /* This is a fine thing to happen */ 624 int n = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 625 if (n != esc->sc_slop_bgn_size) { 626 panic("%s: Unexpected data in fifo n = %d, expecting %d ", 627 sc->sc_dev.dv_xname, n, esc->sc_slop_bgn_size); 628 } 629 #endif 630 #endif 631 for(i=0;i<esc->sc_slop_bgn_size;i++) { 632 esc->sc_slop_bgn_addr[i]=NCR_READ_REG(sc, NCR_FIFO); 633 } 634 635 } else { 636 int i; 637 for(i=0;i<esc->sc_slop_bgn_size;i++) { 638 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_slop_bgn_addr[i]); 639 } 640 641 DPRINTF(("esp fifo size = %d\n", 642 (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF))); 643 } 644 645 if (esc->sc_dmamap->dm_mapsize != 0) { 646 if (esc->sc_datain) { 647 NCR_WRITE_REG(sc, ESP_DCTL, 648 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 649 } else { 650 NCR_WRITE_REG(sc, ESP_DCTL, 651 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 652 } 653 654 655 nextdma_start(&esc->sc_scsi_dma, 656 (esc->sc_datain ? DMACSR_READ : DMACSR_WRITE)); 657 } else { 658 #if defined(DIAGNOSTIC) 659 /* verify that end slop is 0, since the shutdown 660 * callback will not be called. 661 */ 662 if (esc->sc_slop_end_size != 0) { 663 panic("%s: Unexpected end slop with no DMA, slop = %d", 664 sc->sc_dev.dv_xname, esc->sc_slop_end_size); 665 } 666 #endif 667 #if 0 668 if (esc->sc_datain) { 669 NCR_WRITE_REG(sc, ESP_DCTL, 670 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD | ESPDCTL_FLUSH); 671 } else { 672 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 673 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_FLUSH); 674 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 675 } 676 #endif 677 678 esc->sc_datain = -1; 679 esc->sc_slop_bgn_addr = 0; 680 esc->sc_slop_bgn_size = 0; 681 esc->sc_slop_end_addr = 0; 682 esc->sc_slop_end_size = 0; 683 684 DPRINTF(("esp fifo size = %d\n", 685 (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF))); 686 } 687 } 688 689 void 690 esp_dma_stop(sc) 691 struct ncr53c9x_softc *sc; 692 { 693 panic("Not yet implemented"); 694 } 695 696 int 697 esp_dma_isactive(sc) 698 struct ncr53c9x_softc *sc; 699 { 700 struct esp_softc *esc = (struct esp_softc *)sc; 701 return( !nextdma_finished(&esc->sc_scsi_dma)); 702 } 703 704 /****************************************************************/ 705 706 /* Internal dma callback routines */ 707 bus_dmamap_t 708 esp_dmacb_continue(arg) 709 void *arg; 710 { 711 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 712 struct esp_softc *esc = (struct esp_softc *)sc; 713 714 DPRINTF(("esp dma continue\n")); 715 716 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap, 717 0, esc->sc_dmamap->dm_mapsize, 718 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 719 720 #ifdef DIAGNOSTIC 721 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 722 panic("%s: map not loaded in dma continue callback, datain = %d", 723 sc->sc_dev.dv_xname,esc->sc_datain); 724 } 725 #endif 726 727 return(esc->sc_dmamap); 728 } 729 730 void 731 esp_dmacb_completed(map, arg) 732 bus_dmamap_t map; 733 void *arg; 734 { 735 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 736 struct esp_softc *esc = (struct esp_softc *)sc; 737 738 DPRINTF(("esp dma completed\n")); 739 740 #ifdef DIAGNOSTIC 741 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 742 panic("%s: map not loaded in dma completed callback, datain = %d", 743 sc->sc_dev.dv_xname,esc->sc_datain); 744 } 745 if (map != esc->sc_dmamap) { 746 panic("%s: unexpected tx completed map", sc->sc_dev.dv_xname); 747 } 748 #endif 749 750 /* @@@ Flush the fifo? */ 751 752 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap, 753 0, esc->sc_dmamap->dm_mapsize, 754 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 755 } 756 757 void 758 esp_dmacb_shutdown(arg) 759 void *arg; 760 { 761 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 762 struct esp_softc *esc = (struct esp_softc *)sc; 763 764 DPRINTF(("esp dma shutdown\n")); 765 766 #ifdef DIAGNOSTIC 767 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 768 panic("%s: map not loaded in dma shutdown callback, datain = %d", 769 sc->sc_dev.dv_xname,esc->sc_datain); 770 } 771 #endif 772 773 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap); 774 775 /* Stuff the end slop into fifo */ 776 777 { 778 if (esc->sc_datain) { 779 NCR_WRITE_REG(sc, ESP_DCTL, 780 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 781 } else { 782 NCR_WRITE_REG(sc, ESP_DCTL, 783 ESPDCTL_20MHZ | ESPDCTL_INTENB); 784 } 785 786 if (esc->sc_datain) { 787 int i; 788 #ifdef DIAGNOSTIC 789 int n = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 790 if (n != esc->sc_slop_end_size) { 791 panic("%s: Unexpected data in fifo n = %d, expecting %d at end", 792 sc->sc_dev.dv_xname, n, esc->sc_slop_end_size); 793 } 794 #endif 795 for(i=0;i<esc->sc_slop_end_size;i++) { 796 esc->sc_slop_end_addr[i]=NCR_READ_REG(sc, NCR_FIFO); 797 } 798 799 } else { 800 int i; 801 for(i=0;i<esc->sc_slop_end_size;i++) { 802 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_slop_end_addr[i]); 803 } 804 } 805 } 806 807 808 esc->sc_datain = -1; 809 esc->sc_slop_bgn_addr = 0; 810 esc->sc_slop_bgn_size = 0; 811 esc->sc_slop_end_addr = 0; 812 esc->sc_slop_end_size = 0; 813 } 814
Indexes created Sat Oct 11 16:09:52 GMT 2025