esp.c revision 1.8
1 /* $NetBSD: esp.c,v 1.8 1998/10/10 00:28:31 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994 Peter Galbavy 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Peter Galbavy 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 60 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 61 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 62 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 63 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 67 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 /* 72 * Based on aic6360 by Jarle Greipsland 73 * 74 * Acknowledgements: Many of the algorithms used in this driver are 75 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 76 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 77 */ 78 79 /* 80 * Grabbed from the sparc port at revision 1.73 for the NeXT. 81 * Darrin B. Jewell <dbj (at) netbsd.org> Sat Jul 4 15:41:32 1998 82 */ 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/errno.h> 89 #include <sys/ioctl.h> 90 #include <sys/device.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 #include <sys/user.h> 94 #include <sys/queue.h> 95 96 #include <dev/scsipi/scsi_all.h> 97 #include <dev/scsipi/scsipi_all.h> 98 #include <dev/scsipi/scsiconf.h> 99 #include <dev/scsipi/scsi_message.h> 100 101 #include <machine/bus.h> 102 #include <machine/autoconf.h> 103 #include <machine/cpu.h> 104 105 #include <dev/ic/ncr53c9xreg.h> 106 #include <dev/ic/ncr53c9xvar.h> 107 108 #include <next68k/next68k/isr.h> 109 110 #include <next68k/dev/nextdmareg.h> 111 #include <next68k/dev/nextdmavar.h> 112 113 #include "espreg.h" 114 #include "espvar.h" 115 116 #if 1 117 #define ESP_DEBUG 118 #endif 119 120 #ifdef ESP_DEBUG 121 #define DPRINTF(x) printf x; 122 #else 123 #define DPRINTF(x) 124 #endif 125 126 127 void espattach_intio __P((struct device *, struct device *, void *)); 128 int espmatch_intio __P((struct device *, struct cfdata *, void *)); 129 130 /* DMA callbacks */ 131 bus_dmamap_t esp_dmacb_continue __P((void *arg)); 132 void esp_dmacb_completed __P((bus_dmamap_t map, void *arg)); 133 void esp_dmacb_shutdown __P((void *arg)); 134 135 /* Linkup to the rest of the kernel */ 136 struct cfattach esp_ca = { 137 sizeof(struct esp_softc), espmatch_intio, espattach_intio 138 }; 139 140 struct scsipi_adapter esp_switch = { 141 ncr53c9x_scsi_cmd, 142 minphys, /* no max at this level; handled by DMA code */ 143 NULL, /* scsipi_ioctl */ 144 }; 145 146 struct scsipi_device esp_dev = { 147 NULL, /* Use default error handler */ 148 NULL, /* have a queue, served by this */ 149 NULL, /* have no async handler */ 150 NULL, /* Use default 'done' routine */ 151 }; 152 153 /* 154 * Functions and the switch for the MI code. 155 */ 156 u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 157 void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 158 int esp_dma_isintr __P((struct ncr53c9x_softc *)); 159 void esp_dma_reset __P((struct ncr53c9x_softc *)); 160 int esp_dma_intr __P((struct ncr53c9x_softc *)); 161 int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 162 size_t *, int, size_t *)); 163 void esp_dma_go __P((struct ncr53c9x_softc *)); 164 void esp_dma_stop __P((struct ncr53c9x_softc *)); 165 int esp_dma_isactive __P((struct ncr53c9x_softc *)); 166 167 struct ncr53c9x_glue esp_glue = { 168 esp_read_reg, 169 esp_write_reg, 170 esp_dma_isintr, 171 esp_dma_reset, 172 esp_dma_intr, 173 esp_dma_setup, 174 esp_dma_go, 175 esp_dma_stop, 176 esp_dma_isactive, 177 NULL, /* gl_clear_latched_intr */ 178 }; 179 180 int 181 espmatch_intio(parent, cf, aux) 182 struct device *parent; 183 struct cfdata *cf; 184 void *aux; 185 { 186 /* should probably probe here */ 187 /* Should also probably set up data from config */ 188 189 #if 1 190 /* this code isn't working yet, don't match on it */ 191 return(0); 192 #else 193 return(1); 194 #endif 195 } 196 197 void 198 espattach_intio(parent, self, aux) 199 struct device *parent, *self; 200 void *aux; 201 { 202 struct esp_softc *esc = (void *)self; 203 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 204 205 esc->sc_bst = NEXT68K_INTIO_BUS_SPACE; 206 if (bus_space_map(esc->sc_bst, NEXT_P_SCSI, 207 ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) { 208 panic("\n%s: can't map ncr53c90 registers", 209 sc->sc_dev.dv_xname); 210 } 211 212 sc->sc_id = 7; 213 sc->sc_freq = 20; /* Mhz */ 214 215 /* 216 * Set up glue for MI code early; we use some of it here. 217 */ 218 sc->sc_glue = &esp_glue; 219 220 /* 221 * XXX More of this should be in ncr53c9x_attach(), but 222 * XXX should we really poke around the chip that much in 223 * XXX the MI code? Think about this more... 224 */ 225 226 /* 227 * It is necessary to try to load the 2nd config register here, 228 * to find out what rev the esp chip is, else the ncr53c9x_reset 229 * will not set up the defaults correctly. 230 */ 231 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 232 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 233 sc->sc_cfg3 = NCRCFG3_CDB; 234 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 235 236 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 237 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 238 sc->sc_rev = NCR_VARIANT_ESP100; 239 } else { 240 sc->sc_cfg2 = NCRCFG2_SCSI2; 241 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 242 sc->sc_cfg3 = 0; 243 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 244 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 245 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 246 if (NCR_READ_REG(sc, NCR_CFG3) != 247 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 248 sc->sc_rev = NCR_VARIANT_ESP100A; 249 } else { 250 /* NCRCFG2_FE enables > 64K transfers */ 251 sc->sc_cfg2 |= NCRCFG2_FE; 252 sc->sc_cfg3 = 0; 253 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 254 sc->sc_rev = NCR_VARIANT_ESP200; 255 } 256 } 257 258 /* 259 * XXX minsync and maxxfer _should_ be set up in MI code, 260 * XXX but it appears to have some dependency on what sort 261 * XXX of DMA we're hooked up to, etc. 262 */ 263 264 /* 265 * This is the value used to start sync negotiations 266 * Note that the NCR register "SYNCTP" is programmed 267 * in "clocks per byte", and has a minimum value of 4. 268 * The SCSI period used in negotiation is one-fourth 269 * of the time (in nanoseconds) needed to transfer one byte. 270 * Since the chip's clock is given in MHz, we have the following 271 * formula: 4 * period = (1000 / freq) * 4 272 */ 273 sc->sc_minsync = 1000 / sc->sc_freq; 274 275 /* 276 * Alas, we must now modify the value a bit, because it's 277 * only valid when can switch on FASTCLK and FASTSCSI bits 278 * in config register 3... 279 */ 280 switch (sc->sc_rev) { 281 case NCR_VARIANT_ESP100: 282 sc->sc_maxxfer = 64 * 1024; 283 sc->sc_minsync = 0; /* No synch on old chip? */ 284 break; 285 286 case NCR_VARIANT_ESP100A: 287 sc->sc_maxxfer = 64 * 1024; 288 /* Min clocks/byte is 5 */ 289 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 290 break; 291 292 case NCR_VARIANT_ESP200: 293 sc->sc_maxxfer = 16 * 1024 * 1024; 294 /* XXX - do actually set FAST* bits */ 295 break; 296 } 297 298 /* @@@ Some ESP_DCTL bits probably need setting */ 299 NCR_WRITE_REG(sc, ESP_DCTL, 300 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET); 301 DELAY(10); 302 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 303 DELAY(10); 304 305 /* Set up SCSI DMA */ 306 { 307 esc->sc_scsi_dma.nd_bst = NEXT68K_INTIO_BUS_SPACE; 308 309 if (bus_space_map(esc->sc_scsi_dma.nd_bst, NEXT_P_SCSI_CSR, 310 sizeof(struct dma_dev),0, &esc->sc_scsi_dma.nd_bsh)) { 311 panic("\n%s: can't map scsi DMA registers", 312 sc->sc_dev.dv_xname); 313 } 314 315 esc->sc_scsi_dma.nd_intr = NEXT_I_SCSI_DMA; 316 esc->sc_scsi_dma.nd_chaining_flag = 0; 317 esc->sc_scsi_dma.nd_shutdown_cb = &esp_dmacb_shutdown; 318 esc->sc_scsi_dma.nd_continue_cb = &esp_dmacb_continue; 319 esc->sc_scsi_dma.nd_completed_cb = &esp_dmacb_completed; 320 esc->sc_scsi_dma.nd_cb_arg = sc; 321 nextdma_config(&esc->sc_scsi_dma); 322 nextdma_init(&esc->sc_scsi_dma); 323 324 { 325 int error; 326 if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat, 327 sc->sc_maxxfer, 1, sc->sc_maxxfer, 328 0, BUS_DMA_ALLOCNOW, &esc->sc_dmamap)) != 0) { 329 panic("%s: can't create i/o DMA map, error = %d", 330 sc->sc_dev.dv_xname,error); 331 } 332 } 333 } 334 335 #if 0 336 /* Turn on target selection using the `dma' method */ 337 ncr53c9x_dmaselect = 1; 338 #else 339 ncr53c9x_dmaselect = 0; 340 #endif 341 342 esc->sc_slop_bgn_addr = 0; 343 esc->sc_slop_bgn_size = 0; 344 esc->sc_slop_end_addr = 0; 345 esc->sc_slop_end_size = 0; 346 esc->sc_datain = -1; 347 348 /* Establish interrupt channel */ 349 isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc, 350 NEXT_I_IPL(NEXT_I_SCSI), 0); 351 INTR_ENABLE(NEXT_I_SCSI); 352 353 /* register interrupt stats */ 354 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 355 356 /* Do the common parts of attachment. */ 357 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 358 } 359 360 /* 361 * Glue functions. 362 */ 363 364 u_char 365 esp_read_reg(sc, reg) 366 struct ncr53c9x_softc *sc; 367 int reg; 368 { 369 struct esp_softc *esc = (struct esp_softc *)sc; 370 371 return(bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg)); 372 } 373 374 void 375 esp_write_reg(sc, reg, val) 376 struct ncr53c9x_softc *sc; 377 int reg; 378 u_char val; 379 { 380 struct esp_softc *esc = (struct esp_softc *)sc; 381 382 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val); 383 } 384 385 int 386 esp_dma_isintr(sc) 387 struct ncr53c9x_softc *sc; 388 { 389 struct esp_softc *esc = (struct esp_softc *)sc; 390 391 int r = (INTR_OCCURRED(NEXT_I_SCSI)); 392 393 if (r) { 394 DPRINTF(("esp_dma_isintr = %d\n",r)); 395 396 if (esc->sc_datain) { 397 NCR_WRITE_REG(sc, ESP_DCTL, 398 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 399 } else { 400 NCR_WRITE_REG(sc, ESP_DCTL, 401 ESPDCTL_20MHZ | ESPDCTL_INTENB); 402 } 403 } 404 405 return (r); 406 } 407 408 void 409 esp_dma_reset(sc) 410 struct ncr53c9x_softc *sc; 411 { 412 struct esp_softc *esc = (struct esp_softc *)sc; 413 414 nextdma_reset(&esc->sc_scsi_dma); 415 416 if (esc->sc_dmamap->dm_mapsize != 0) { 417 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap); 418 } 419 420 esc->sc_slop_bgn_addr = 0; 421 esc->sc_slop_bgn_size = 0; 422 esc->sc_slop_end_addr = 0; 423 esc->sc_slop_end_size = 0; 424 esc->sc_datain = -1; 425 } 426 427 int 428 esp_dma_intr(sc) 429 struct ncr53c9x_softc *sc; 430 { 431 int trans; 432 int resid; 433 int datain; 434 struct esp_softc *esc = (struct esp_softc *)sc; 435 436 datain = esc->sc_datain; 437 438 DPRINTF(("esp_dma_intr resetting dma\n")); 439 440 /* If the dma hasn't finished when we are in a scsi 441 * interrupt. Then, "Houston, we have a problem." 442 * Stop DMA and figure out how many bytes were transferred 443 */ 444 esp_dma_reset(sc); 445 446 resid = 0; 447 448 /* 449 * If a transfer onto the SCSI bus gets interrupted by the device 450 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 451 * as residual since the ESP counter registers get decremented as 452 * bytes are clocked into the FIFO. 453 */ 454 455 if (! datain) { 456 resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 457 if (resid) { 458 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid)); 459 NCRCMD(sc, NCRCMD_FLUSH); 460 DELAY(1); 461 } 462 } 463 464 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 465 /* 466 * `Terminal count' is off, so read the residue 467 * out of the ESP counter registers. 468 */ 469 resid += (NCR_READ_REG(sc, NCR_TCL) | 470 (NCR_READ_REG(sc, NCR_TCM) << 8) | 471 ((sc->sc_cfg2 & NCRCFG2_FE) 472 ? (NCR_READ_REG(sc, NCR_TCH) << 16) 473 : 0)); 474 475 if (resid == 0 && esc->sc_dmasize == 65536 && 476 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 477 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 478 resid = 65536; 479 } 480 481 trans = esc->sc_dmasize - resid; 482 if (trans < 0) { /* transferred < 0 ? */ 483 #if 0 484 /* 485 * This situation can happen in perfectly normal operation 486 * if the ESP is reselected while using DMA to select 487 * another target. As such, don't print the warning. 488 */ 489 printf("%s: xfer (%d) > req (%d)\n", 490 esc->sc_dev.dv_xname, trans, esc->sc_dmasize); 491 #endif 492 trans = esc->sc_dmasize; 493 } 494 495 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 496 NCR_READ_REG(sc, NCR_TCL), 497 NCR_READ_REG(sc, NCR_TCM), 498 (sc->sc_cfg2 & NCRCFG2_FE) 499 ? NCR_READ_REG(sc, NCR_TCH) : 0, 500 trans, resid)); 501 502 *esc->sc_dmalen -= trans; 503 *esc->sc_dmaaddr += trans; 504 505 return 0; 506 } 507 508 int 509 esp_dma_setup(sc, addr, len, datain, dmasize) 510 struct ncr53c9x_softc *sc; 511 caddr_t *addr; 512 size_t *len; 513 int datain; 514 size_t *dmasize; 515 { 516 struct esp_softc *esc = (struct esp_softc *)sc; 517 518 /* Save these in case we have to abort DMA */ 519 esc->sc_dmaaddr = addr; 520 esc->sc_dmalen = len; 521 esc->sc_dmasize = *dmasize; 522 523 DPRINTF(("esp_dma_setup(0x%08lx,0x%08lx)\n",*addr,*dmasize)); 524 525 #ifdef DIAGNOSTIC 526 if ((esc->sc_datain != -1) || 527 (esc->sc_dmamap->dm_mapsize != 0)) { 528 panic("%s: map already loaded in esp_dma_setup\n" 529 "\tdatain = %d\n\tmapsize=%d", 530 sc->sc_dev.dv_xname,esc->sc_datain,esc->sc_dmamap->dm_mapsize); 531 } 532 #endif 533 534 /* Deal with DMA alignment issues, by stuffing the FIFO. 535 * This assumes that if bus_dmamap_load is given an aligned 536 * buffer, then it will generate aligned hardware addresses 537 * to give to the device. Perhaps that is not a good assumption, 538 * but it is probably true. [dbj (at) netbsd.org:19980719.0135EDT] 539 */ 540 { 541 int slop_bgn_size; /* # bytes to be fifo'd at beginning */ 542 int slop_end_size; /* # bytes to be fifo'd at end */ 543 544 { 545 u_long bgn = (u_long)(*addr); 546 u_long end = (u_long)(*addr+*dmasize); 547 548 slop_bgn_size = DMA_BEGINALIGNMENT-(bgn % DMA_BEGINALIGNMENT); 549 if (slop_bgn_size == DMA_BEGINALIGNMENT) slop_bgn_size = 0; 550 slop_end_size = end % DMA_ENDALIGNMENT; 551 } 552 553 /* Check to make sure we haven't counted the slop twice 554 * as would happen for a very short dma buffer */ 555 if (slop_bgn_size+slop_end_size > *dmasize) { 556 #if defined(DIAGNOSTIC) 557 if ((slop_bgn_size != *dmasize) || 558 (slop_end_size != *dmasize)) { 559 panic("%s: confused alignment calculation\n" 560 "\tslop_bgn_size %d\n\tslop_end_size %d\n\tdmasize %d", 561 sc->sc_dev.dv_xname,slop_bgn_size,slop_end_size,*dmasize); 562 } 563 #endif 564 slop_end_size = 0; 565 } 566 567 if (slop_bgn_size+slop_end_size < *dmasize) { 568 int error; 569 error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat, 570 esc->sc_dmamap, 571 *addr+slop_bgn_size, 572 *dmasize-(slop_bgn_size+slop_end_size), 573 NULL, BUS_DMA_NOWAIT); 574 if (error) { 575 panic("%s: can't load dma map. error = %d", 576 sc->sc_dev.dv_xname, error); 577 } 578 579 } else { 580 /* If there's no DMA, then coalesce the fifo buffers */ 581 slop_bgn_size += slop_end_size; 582 slop_end_size = 0; 583 } 584 585 esc->sc_slop_bgn_addr = *addr; 586 esc->sc_slop_bgn_size = slop_bgn_size; 587 esc->sc_slop_end_addr = (*addr+*dmasize)-slop_end_size; 588 esc->sc_slop_end_size = slop_end_size; 589 } 590 591 esc->sc_datain = datain; 592 593 return (0); 594 } 595 596 void 597 esp_dma_go(sc) 598 struct ncr53c9x_softc *sc; 599 { 600 struct esp_softc *esc = (struct esp_softc *)sc; 601 602 DPRINTF(("esp_dma_go(datain = %d)\n",esc->sc_datain)); 603 604 DPRINTF(("\tbgn slop = %d\n\tend slop = %d\n\tmapsize = %d\n", 605 esc->sc_slop_bgn_size,esc->sc_slop_end_size, 606 esc->sc_dmamap->dm_mapsize)); 607 608 DPRINTF(("esp fifo size = %d\n", 609 (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF))); 610 611 if (esc->sc_datain) { 612 NCR_WRITE_REG(sc, ESP_DCTL, 613 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 614 } else { 615 NCR_WRITE_REG(sc, ESP_DCTL, 616 ESPDCTL_20MHZ | ESPDCTL_INTENB); 617 } 618 619 if (esc->sc_datain) { 620 int i; 621 #ifdef DIAGNOSTIC 622 #if 0 /* This is a fine thing to happen */ 623 int n = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 624 if (n != esc->sc_slop_bgn_size) { 625 panic("%s: Unexpected data in fifo n = %d, expecting %d ", 626 sc->sc_dev.dv_xname, n, esc->sc_slop_bgn_size); 627 } 628 #endif 629 #endif 630 for(i=0;i<esc->sc_slop_bgn_size;i++) { 631 esc->sc_slop_bgn_addr[i]=NCR_READ_REG(sc, NCR_FIFO); 632 } 633 634 } else { 635 int i; 636 for(i=0;i<esc->sc_slop_bgn_size;i++) { 637 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_slop_bgn_addr[i]); 638 } 639 640 DPRINTF(("esp fifo size = %d\n", 641 (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF))); 642 } 643 644 if (esc->sc_dmamap->dm_mapsize != 0) { 645 if (esc->sc_datain) { 646 NCR_WRITE_REG(sc, ESP_DCTL, 647 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD); 648 } else { 649 NCR_WRITE_REG(sc, ESP_DCTL, 650 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD); 651 } 652 653 654 nextdma_start(&esc->sc_scsi_dma, 655 (esc->sc_datain ? DMACSR_READ : DMACSR_WRITE)); 656 } else { 657 #if defined(DIAGNOSTIC) 658 /* verify that end slop is 0, since the shutdown 659 * callback will not be called. 660 */ 661 if (esc->sc_slop_end_size != 0) { 662 panic("%s: Unexpected end slop with no DMA, slop = %d", 663 sc->sc_dev.dv_xname, esc->sc_slop_end_size); 664 } 665 #endif 666 #if 0 667 if (esc->sc_datain) { 668 NCR_WRITE_REG(sc, ESP_DCTL, 669 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD | ESPDCTL_FLUSH); 670 } else { 671 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 672 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_FLUSH); 673 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB); 674 } 675 #endif 676 677 esc->sc_datain = -1; 678 esc->sc_slop_bgn_addr = 0; 679 esc->sc_slop_bgn_size = 0; 680 esc->sc_slop_end_addr = 0; 681 esc->sc_slop_end_size = 0; 682 683 DPRINTF(("esp fifo size = %d\n", 684 (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF))); 685 } 686 } 687 688 void 689 esp_dma_stop(sc) 690 struct ncr53c9x_softc *sc; 691 { 692 panic("Not yet implemented"); 693 } 694 695 int 696 esp_dma_isactive(sc) 697 struct ncr53c9x_softc *sc; 698 { 699 struct esp_softc *esc = (struct esp_softc *)sc; 700 return( !nextdma_finished(&esc->sc_scsi_dma)); 701 } 702 703 /****************************************************************/ 704 705 /* Internal dma callback routines */ 706 bus_dmamap_t 707 esp_dmacb_continue(arg) 708 void *arg; 709 { 710 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 711 struct esp_softc *esc = (struct esp_softc *)sc; 712 713 DPRINTF(("esp dma continue\n")); 714 715 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap, 716 0, esc->sc_dmamap->dm_mapsize, 717 (esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 718 719 #ifdef DIAGNOSTIC 720 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 721 panic("%s: map not loaded in dma continue callback, datain = %d", 722 sc->sc_dev.dv_xname,esc->sc_datain); 723 } 724 #endif 725 726 return(esc->sc_dmamap); 727 } 728 729 void 730 esp_dmacb_completed(map, arg) 731 bus_dmamap_t map; 732 void *arg; 733 { 734 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 735 struct esp_softc *esc = (struct esp_softc *)sc; 736 737 DPRINTF(("esp dma completed\n")); 738 739 #ifdef DIAGNOSTIC 740 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 741 panic("%s: map not loaded in dma completed callback, datain = %d", 742 sc->sc_dev.dv_xname,esc->sc_datain); 743 } 744 if (map != esc->sc_dmamap) { 745 panic("%s: unexpected tx completed map", sc->sc_dev.dv_xname); 746 } 747 #endif 748 749 /* @@@ Flush the fifo? */ 750 751 bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap, 752 0, esc->sc_dmamap->dm_mapsize, 753 (esc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE)); 754 } 755 756 void 757 esp_dmacb_shutdown(arg) 758 void *arg; 759 { 760 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 761 struct esp_softc *esc = (struct esp_softc *)sc; 762 763 DPRINTF(("esp dma shutdown\n")); 764 765 #ifdef DIAGNOSTIC 766 if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) { 767 panic("%s: map not loaded in dma shutdown callback, datain = %d", 768 sc->sc_dev.dv_xname,esc->sc_datain); 769 } 770 #endif 771 772 bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap); 773 774 /* Stuff the end slop into fifo */ 775 776 { 777 if (esc->sc_datain) { 778 NCR_WRITE_REG(sc, ESP_DCTL, 779 ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD); 780 } else { 781 NCR_WRITE_REG(sc, ESP_DCTL, 782 ESPDCTL_20MHZ | ESPDCTL_INTENB); 783 } 784 785 if (esc->sc_datain) { 786 int i; 787 #ifdef DIAGNOSTIC 788 int n = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF); 789 if (n != esc->sc_slop_end_size) { 790 panic("%s: Unexpected data in fifo n = %d, expecting %d at end", 791 sc->sc_dev.dv_xname, n, esc->sc_slop_end_size); 792 } 793 #endif 794 for(i=0;i<esc->sc_slop_end_size;i++) { 795 esc->sc_slop_end_addr[i]=NCR_READ_REG(sc, NCR_FIFO); 796 } 797 798 } else { 799 int i; 800 for(i=0;i<esc->sc_slop_end_size;i++) { 801 NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_slop_end_addr[i]); 802 } 803 } 804 } 805 806 807 esc->sc_datain = -1; 808 esc->sc_slop_bgn_addr = 0; 809 esc->sc_slop_bgn_size = 0; 810 esc->sc_slop_end_addr = 0; 811 esc->sc_slop_end_size = 0; 812 } 813
Indexes created Sat Oct 11 16:09:52 GMT 2025