mb8795.c revision 1.21 1 1.21 dbj /* $NetBSD: mb8795.c,v 1.21 2001/04/02 05:29:43 dbj Exp $ */
2 1.1 dbj /*
3 1.1 dbj * Copyright (c) 1998 Darrin B. Jewell
4 1.1 dbj * All rights reserved.
5 1.1 dbj *
6 1.1 dbj * Redistribution and use in source and binary forms, with or without
7 1.1 dbj * modification, are permitted provided that the following conditions
8 1.1 dbj * are met:
9 1.1 dbj * 1. Redistributions of source code must retain the above copyright
10 1.1 dbj * notice, this list of conditions and the following disclaimer.
11 1.1 dbj * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 dbj * notice, this list of conditions and the following disclaimer in the
13 1.1 dbj * documentation and/or other materials provided with the distribution.
14 1.1 dbj * 3. All advertising materials mentioning features or use of this software
15 1.1 dbj * must display the following acknowledgement:
16 1.1 dbj * This product includes software developed by Darrin B. Jewell
17 1.1 dbj * 4. The name of the author may not be used to endorse or promote products
18 1.1 dbj * derived from this software without specific prior written permission
19 1.1 dbj *
20 1.1 dbj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 1.1 dbj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 1.1 dbj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 1.1 dbj * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 1.1 dbj * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 1.1 dbj * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 1.1 dbj * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 1.1 dbj * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 1.1 dbj * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 1.1 dbj * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 1.1 dbj */
31 1.1 dbj
32 1.2 jonathan #include "opt_inet.h"
33 1.3 jonathan #include "opt_ccitt.h"
34 1.4 jonathan #include "opt_llc.h"
35 1.5 jonathan #include "opt_ns.h"
36 1.1 dbj #include "bpfilter.h"
37 1.1 dbj #include "rnd.h"
38 1.1 dbj
39 1.1 dbj #include <sys/param.h>
40 1.1 dbj #include <sys/systm.h>
41 1.1 dbj #include <sys/mbuf.h>
42 1.1 dbj #include <sys/syslog.h>
43 1.1 dbj #include <sys/socket.h>
44 1.1 dbj #include <sys/device.h>
45 1.1 dbj #include <sys/malloc.h>
46 1.1 dbj #include <sys/ioctl.h>
47 1.1 dbj #include <sys/errno.h>
48 1.1 dbj #if NRND > 0
49 1.1 dbj #include <sys/rnd.h>
50 1.1 dbj #endif
51 1.1 dbj
52 1.1 dbj #include <net/if.h>
53 1.1 dbj #include <net/if_dl.h>
54 1.1 dbj #include <net/if_ether.h>
55 1.1 dbj
56 1.1 dbj #if 0
57 1.1 dbj #include <net/if_media.h>
58 1.1 dbj #endif
59 1.1 dbj
60 1.1 dbj #ifdef INET
61 1.1 dbj #include <netinet/in.h>
62 1.1 dbj #include <netinet/if_inarp.h>
63 1.1 dbj #include <netinet/in_systm.h>
64 1.1 dbj #include <netinet/in_var.h>
65 1.1 dbj #include <netinet/ip.h>
66 1.1 dbj #endif
67 1.1 dbj
68 1.1 dbj #ifdef NS
69 1.1 dbj #include <netns/ns.h>
70 1.1 dbj #include <netns/ns_if.h>
71 1.1 dbj #endif
72 1.1 dbj
73 1.1 dbj #if defined(CCITT) && defined(LLC)
74 1.1 dbj #include <sys/socketvar.h>
75 1.1 dbj #include <netccitt/x25.h>
76 1.1 dbj #include <netccitt/pk.h>
77 1.1 dbj #include <netccitt/pk_var.h>
78 1.1 dbj #include <netccitt/pk_extern.h>
79 1.1 dbj #endif
80 1.1 dbj
81 1.1 dbj #if NBPFILTER > 0
82 1.1 dbj #include <net/bpf.h>
83 1.1 dbj #include <net/bpfdesc.h>
84 1.1 dbj #endif
85 1.1 dbj
86 1.1 dbj #include <machine/cpu.h>
87 1.1 dbj #include <machine/bus.h>
88 1.1 dbj #include <machine/intr.h>
89 1.1 dbj
90 1.1 dbj /* @@@ this is here for the REALIGN_DMABUF hack below */
91 1.1 dbj #include "nextdmareg.h"
92 1.1 dbj #include "nextdmavar.h"
93 1.1 dbj
94 1.1 dbj #include "mb8795reg.h"
95 1.1 dbj #include "mb8795var.h"
96 1.1 dbj
97 1.17 dbj #if 1
98 1.1 dbj #define XE_DEBUG
99 1.1 dbj #endif
100 1.1 dbj
101 1.1 dbj #ifdef XE_DEBUG
102 1.17 dbj int xe_debug = 0;
103 1.17 dbj #define DPRINTF(x) if (xe_debug) printf x;
104 1.1 dbj #else
105 1.1 dbj #define DPRINTF(x)
106 1.1 dbj #endif
107 1.1 dbj
108 1.1 dbj
109 1.1 dbj /*
110 1.1 dbj * Support for
111 1.1 dbj * Fujitsu Ethernet Data Link Controller (MB8795)
112 1.1 dbj * and the Fujitsu Manchester Encoder/Decoder (MB502).
113 1.1 dbj */
114 1.1 dbj
115 1.1 dbj void mb8795_shutdown __P((void *));
116 1.1 dbj
117 1.1 dbj struct mbuf * mb8795_rxdmamap_load __P((struct mb8795_softc *,
118 1.1 dbj bus_dmamap_t map));
119 1.1 dbj
120 1.1 dbj bus_dmamap_t mb8795_rxdma_continue __P((void *));
121 1.1 dbj void mb8795_rxdma_completed __P((bus_dmamap_t,void *));
122 1.1 dbj bus_dmamap_t mb8795_txdma_continue __P((void *));
123 1.1 dbj void mb8795_txdma_completed __P((bus_dmamap_t,void *));
124 1.1 dbj void mb8795_rxdma_shutdown __P((void *));
125 1.1 dbj void mb8795_txdma_shutdown __P((void *));
126 1.1 dbj bus_dmamap_t mb8795_txdma_restart __P((bus_dmamap_t,void *));
127 1.1 dbj
128 1.1 dbj void
129 1.1 dbj mb8795_config(sc)
130 1.1 dbj struct mb8795_softc *sc;
131 1.1 dbj {
132 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
133 1.1 dbj
134 1.1 dbj DPRINTF(("%s: mb8795_config()\n",sc->sc_dev.dv_xname));
135 1.1 dbj
136 1.1 dbj /* Initialize ifnet structure. */
137 1.1 dbj bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
138 1.1 dbj ifp->if_softc = sc;
139 1.1 dbj ifp->if_start = mb8795_start;
140 1.1 dbj ifp->if_ioctl = mb8795_ioctl;
141 1.1 dbj ifp->if_watchdog = mb8795_watchdog;
142 1.1 dbj ifp->if_flags =
143 1.1 dbj IFF_BROADCAST | IFF_NOTRAILERS;
144 1.1 dbj
145 1.1 dbj /* Attach the interface. */
146 1.1 dbj if_attach(ifp);
147 1.1 dbj ether_ifattach(ifp, sc->sc_enaddr);
148 1.1 dbj
149 1.1 dbj /* decrease the mtu on this interface to deal with
150 1.1 dbj * alignment problems
151 1.1 dbj */
152 1.1 dbj ifp->if_mtu -= 16;
153 1.1 dbj
154 1.1 dbj sc->sc_sh = shutdownhook_establish(mb8795_shutdown, sc);
155 1.1 dbj if (sc->sc_sh == NULL)
156 1.1 dbj panic("mb8795_config: can't establish shutdownhook");
157 1.1 dbj
158 1.1 dbj #if NRND > 0
159 1.1 dbj rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname,
160 1.10 explorer RND_TYPE_NET, 0);
161 1.1 dbj #endif
162 1.1 dbj
163 1.1 dbj /* Initialize the dma maps */
164 1.1 dbj {
165 1.1 dbj int error;
166 1.1 dbj if ((error = bus_dmamap_create(sc->sc_tx_dmat, MCLBYTES,
167 1.1 dbj (MCLBYTES/MSIZE), MCLBYTES, 0, BUS_DMA_ALLOCNOW,
168 1.1 dbj &sc->sc_tx_dmamap)) != 0) {
169 1.1 dbj panic("%s: can't create tx DMA map, error = %d\n",
170 1.1 dbj sc->sc_dev.dv_xname, error);
171 1.1 dbj }
172 1.1 dbj {
173 1.1 dbj int i;
174 1.1 dbj for(i=0;i<MB8795_NRXBUFS;i++) {
175 1.1 dbj if ((error = bus_dmamap_create(sc->sc_rx_dmat, MCLBYTES,
176 1.1 dbj (MCLBYTES/MSIZE), MCLBYTES, 0, BUS_DMA_ALLOCNOW,
177 1.1 dbj &sc->sc_rx_dmamap[i])) != 0) {
178 1.1 dbj panic("%s: can't create rx DMA map, error = %d\n",
179 1.1 dbj sc->sc_dev.dv_xname, error);
180 1.1 dbj }
181 1.1 dbj sc->sc_rx_mb_head[i] = NULL;
182 1.1 dbj }
183 1.1 dbj sc->sc_rx_loaded_idx = 0;
184 1.1 dbj sc->sc_rx_completed_idx = 0;
185 1.1 dbj sc->sc_rx_handled_idx = 0;
186 1.1 dbj }
187 1.1 dbj }
188 1.1 dbj
189 1.1 dbj /* @@@ more next hacks
190 1.1 dbj * the 2000 covers at least a 1500 mtu + headers
191 1.9 dbj * + DMA_BEGINALIGNMENT+ DMA_ENDALIGNMENT
192 1.1 dbj */
193 1.1 dbj sc->sc_txbuf = malloc(2000, M_DEVBUF, M_NOWAIT);
194 1.1 dbj if (!sc->sc_txbuf) panic("%s: can't malloc tx DMA buffer",
195 1.1 dbj sc->sc_dev.dv_xname);
196 1.1 dbj
197 1.1 dbj sc->sc_tx_mb_head = NULL;
198 1.1 dbj sc->sc_tx_loaded = 0;
199 1.1 dbj
200 1.1 dbj sc->sc_tx_nd->nd_shutdown_cb = mb8795_txdma_shutdown;
201 1.1 dbj sc->sc_tx_nd->nd_continue_cb = mb8795_txdma_continue;
202 1.1 dbj sc->sc_tx_nd->nd_completed_cb = mb8795_txdma_completed;
203 1.1 dbj sc->sc_tx_nd->nd_cb_arg = sc;
204 1.1 dbj
205 1.1 dbj sc->sc_rx_nd->nd_shutdown_cb = mb8795_rxdma_shutdown;
206 1.1 dbj sc->sc_rx_nd->nd_continue_cb = mb8795_rxdma_continue;
207 1.1 dbj sc->sc_rx_nd->nd_completed_cb = mb8795_rxdma_completed;
208 1.1 dbj sc->sc_rx_nd->nd_cb_arg = sc;
209 1.1 dbj
210 1.1 dbj DPRINTF(("%s: leaving mb8795_config()\n",sc->sc_dev.dv_xname));
211 1.1 dbj }
212 1.1 dbj
213 1.1 dbj
214 1.1 dbj /****************************************************************/
215 1.21 dbj #ifdef XE_DEBUG
216 1.1 dbj #define XCHR(x) "0123456789abcdef"[(x) & 0xf]
217 1.1 dbj static void
218 1.21 dbj xe_hex_dump(unsigned char *pkt, size_t len)
219 1.1 dbj {
220 1.1 dbj size_t i, j;
221 1.1 dbj
222 1.21 dbj printf("00000000 ");
223 1.1 dbj for(i=0; i<len; i++) {
224 1.1 dbj printf("%c%c ", XCHR(pkt[i]>>4), XCHR(pkt[i]));
225 1.21 dbj if ((i+1) % 16 == 8) {
226 1.21 dbj printf(" ");
227 1.21 dbj }
228 1.1 dbj if ((i+1) % 16 == 0) {
229 1.21 dbj printf(" %c", '|');
230 1.21 dbj for(j=0; j<16; j++) {
231 1.1 dbj printf("%c", pkt[i-15+j]>=32 && pkt[i-15+j]<127?pkt[i-15+j]:'.');
232 1.21 dbj }
233 1.21 dbj printf("%c\n%c%c%c%c%c%c%c%c ", '|',
234 1.21 dbj XCHR((i+1)>>28),XCHR((i+1)>>24),XCHR((i+1)>>20),XCHR((i+1)>>16),
235 1.21 dbj XCHR((i+1)>>12), XCHR((i+1)>>8), XCHR((i+1)>>4), XCHR(i+1));
236 1.1 dbj }
237 1.1 dbj }
238 1.1 dbj printf("\n");
239 1.1 dbj }
240 1.21 dbj #undef XCHR
241 1.7 dbj #endif
242 1.1 dbj
243 1.1 dbj /*
244 1.1 dbj * Controller receive interrupt.
245 1.1 dbj */
246 1.1 dbj void
247 1.1 dbj mb8795_rint(sc)
248 1.1 dbj struct mb8795_softc *sc;
249 1.1 dbj {
250 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
251 1.1 dbj int error = 0;
252 1.1 dbj u_char rxstat;
253 1.1 dbj u_char rxmask;
254 1.1 dbj
255 1.1 dbj rxstat = bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_RXSTAT);
256 1.1 dbj rxmask = bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_RXMASK);
257 1.1 dbj
258 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RXSTAT, XE_RXSTAT_CLEAR);
259 1.1 dbj
260 1.1 dbj if (rxstat & XE_RXSTAT_RESET) {
261 1.1 dbj DPRINTF(("%s: rx reset packet\n",
262 1.1 dbj sc->sc_dev.dv_xname));
263 1.1 dbj error++;
264 1.1 dbj }
265 1.1 dbj if (rxstat & XE_RXSTAT_SHORT) {
266 1.1 dbj DPRINTF(("%s: rx short packet\n",
267 1.1 dbj sc->sc_dev.dv_xname));
268 1.1 dbj error++;
269 1.1 dbj }
270 1.1 dbj if (rxstat & XE_RXSTAT_ALIGNERR) {
271 1.1 dbj DPRINTF(("%s: rx alignment error\n",
272 1.1 dbj sc->sc_dev.dv_xname));
273 1.21 dbj #if 0
274 1.1 dbj error++;
275 1.21 dbj #endif
276 1.1 dbj }
277 1.1 dbj if (rxstat & XE_RXSTAT_CRCERR) {
278 1.1 dbj DPRINTF(("%s: rx CRC error\n",
279 1.1 dbj sc->sc_dev.dv_xname));
280 1.21 dbj #if 0
281 1.1 dbj error++;
282 1.21 dbj #endif
283 1.1 dbj }
284 1.1 dbj if (rxstat & XE_RXSTAT_OVERFLOW) {
285 1.1 dbj DPRINTF(("%s: rx overflow error\n",
286 1.1 dbj sc->sc_dev.dv_xname));
287 1.21 dbj #if 0
288 1.1 dbj error++;
289 1.21 dbj #endif
290 1.1 dbj }
291 1.1 dbj
292 1.1 dbj if (error) {
293 1.1 dbj ifp->if_ierrors++;
294 1.1 dbj /* @@@ handle more gracefully, free memory, etc. */
295 1.1 dbj }
296 1.1 dbj
297 1.1 dbj if (rxstat & XE_RXSTAT_OK) {
298 1.1 dbj int s;
299 1.1 dbj s = spldma();
300 1.1 dbj
301 1.1 dbj while(sc->sc_rx_handled_idx != sc->sc_rx_completed_idx) {
302 1.1 dbj struct mbuf *m;
303 1.1 dbj bus_dmamap_t map;
304 1.1 dbj
305 1.1 dbj sc->sc_rx_handled_idx++;
306 1.1 dbj sc->sc_rx_handled_idx %= MB8795_NRXBUFS;
307 1.1 dbj
308 1.1 dbj /* Should probably not do this much while interrupts
309 1.1 dbj * are disabled, but for now we will.
310 1.1 dbj */
311 1.1 dbj
312 1.1 dbj map = sc->sc_rx_dmamap[sc->sc_rx_handled_idx];
313 1.1 dbj m = sc->sc_rx_mb_head[sc->sc_rx_handled_idx];
314 1.1 dbj
315 1.1 dbj bus_dmamap_sync(sc->sc_rx_dmat, map,
316 1.1 dbj 0, map->dm_mapsize, BUS_DMASYNC_POSTREAD);
317 1.1 dbj
318 1.21 dbj bus_dmamap_unload(sc->sc_rx_dmat, map);
319 1.21 dbj
320 1.21 dbj /* Install a fresh mbuf for next packet */
321 1.21 dbj
322 1.21 dbj sc->sc_rx_mb_head[sc->sc_rx_handled_idx] =
323 1.21 dbj mb8795_rxdmamap_load(sc,map);
324 1.21 dbj
325 1.21 dbj /* Punt runt packets, these may be caused by dma restarts */
326 1.21 dbj /* @@@ assumes packet is all in first segment */
327 1.21 dbj if (map->dm_segs[0].ds_xfer_len < ETHER_MIN_LEN) {
328 1.21 dbj m_freem(m);
329 1.21 dbj continue;
330 1.21 dbj }
331 1.21 dbj
332 1.1 dbj /* Find receive length and chop off CRC */
333 1.1 dbj /* @@@ assumes packet is all in first segment
334 1.1 dbj */
335 1.15 dbj m->m_pkthdr.len = map->dm_segs[0].ds_xfer_len-4;
336 1.15 dbj m->m_len = map->dm_segs[0].ds_xfer_len-4;
337 1.21 dbj
338 1.1 dbj m->m_pkthdr.rcvif = ifp;
339 1.1 dbj
340 1.1 dbj /* enable interrupts while we process the packet */
341 1.1 dbj splx(s);
342 1.1 dbj
343 1.1 dbj #if defined(XE_DEBUG)
344 1.1 dbj /* Peek at the packet */
345 1.1 dbj DPRINTF(("%s: received packet, at VA 0x%08x-0x%08x,len %d\n",
346 1.1 dbj sc->sc_dev.dv_xname,mtod(m,u_char *),mtod(m,u_char *)+m->m_len,m->m_len));
347 1.21 dbj if (xe_debug > 3) {
348 1.21 dbj xe_hex_dump(mtod(m,u_char *), m->m_pkthdr.len);
349 1.21 dbj } else if (xe_debug > 2) {
350 1.21 dbj xe_hex_dump(mtod(m,u_char *), m->m_pkthdr.len < 255 ? m->m_pkthdr.len : 128 );
351 1.21 dbj }
352 1.1 dbj #endif
353 1.1 dbj
354 1.1 dbj {
355 1.1 dbj ifp->if_ipackets++;
356 1.1 dbj
357 1.11 thorpej /* Pass the packet up. */
358 1.11 thorpej (*ifp->if_input)(ifp, m);
359 1.1 dbj }
360 1.1 dbj
361 1.1 dbj s = spldma();
362 1.1 dbj
363 1.1 dbj }
364 1.1 dbj
365 1.1 dbj splx(s);
366 1.1 dbj
367 1.1 dbj }
368 1.1 dbj
369 1.18 tv #ifdef XE_DEBUG
370 1.18 tv if (xe_debug) {
371 1.18 tv char sbuf[256];
372 1.18 tv
373 1.18 tv bitmask_snprintf(rxstat, XE_RXSTAT_BITS, sbuf, sizeof(sbuf));
374 1.18 tv printf("%s: rx interrupt, rxstat = %s\n",
375 1.18 tv sc->sc_dev.dv_xname, sbuf);
376 1.18 tv
377 1.18 tv bitmask_snprintf(bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_RXSTAT),
378 1.18 tv XE_RXSTAT_BITS, sbuf, sizeof(sbuf));
379 1.18 tv printf("rxstat = 0x%s\n", sbuf);
380 1.18 tv
381 1.18 tv bitmask_snprintf(bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_RXMASK),
382 1.18 tv XE_RXMASK_BITS, sbuf, sizeof(sbuf));
383 1.18 tv printf("rxmask = 0x%s\n", sbuf);
384 1.18 tv
385 1.18 tv bitmask_snprintf(bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_RXMODE),
386 1.18 tv XE_RXMODE_BITS, sbuf, sizeof(sbuf));
387 1.18 tv printf("rxmode = 0x%s\n", sbuf);
388 1.18 tv }
389 1.18 tv #endif
390 1.17 dbj
391 1.1 dbj return;
392 1.1 dbj }
393 1.1 dbj
394 1.1 dbj /*
395 1.1 dbj * Controller transmit interrupt.
396 1.1 dbj */
397 1.1 dbj void
398 1.1 dbj mb8795_tint(sc)
399 1.1 dbj struct mb8795_softc *sc;
400 1.1 dbj
401 1.1 dbj {
402 1.1 dbj u_char txstat;
403 1.1 dbj u_char txmask;
404 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
405 1.1 dbj
406 1.1 dbj txstat = bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_TXSTAT);
407 1.1 dbj txmask = bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK);
408 1.1 dbj
409 1.1 dbj if (txstat & XE_TXSTAT_SHORTED) {
410 1.1 dbj printf("%s: tx cable shorted\n", sc->sc_dev.dv_xname);
411 1.1 dbj ifp->if_oerrors++;
412 1.1 dbj }
413 1.1 dbj if (txstat & XE_TXSTAT_UNDERFLOW) {
414 1.1 dbj printf("%s: tx underflow\n", sc->sc_dev.dv_xname);
415 1.1 dbj ifp->if_oerrors++;
416 1.1 dbj }
417 1.1 dbj if (txstat & XE_TXSTAT_COLLERR) {
418 1.1 dbj DPRINTF(("%s: tx collision\n", sc->sc_dev.dv_xname));
419 1.1 dbj ifp->if_collisions++;
420 1.1 dbj }
421 1.1 dbj if (txstat & XE_TXSTAT_COLLERR16) {
422 1.1 dbj printf("%s: tx 16th collision\n", sc->sc_dev.dv_xname);
423 1.1 dbj ifp->if_oerrors++;
424 1.1 dbj ifp->if_collisions += 16;
425 1.1 dbj }
426 1.1 dbj
427 1.1 dbj #if 0
428 1.1 dbj if (txstat & XE_TXSTAT_READY) {
429 1.18 tv char sbuf[256];
430 1.1 dbj
431 1.18 tv bitmask_snprintf(txstat, XE_TXSTAT_BITS, sbuf, sizeof(sbuf));
432 1.18 tv panic("%s: unexpected tx interrupt %s",
433 1.18 tv sc->sc_dev.dv_xname, sbuf);
434 1.1 dbj
435 1.1 dbj /* turn interrupt off */
436 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK,
437 1.1 dbj txmask & ~XE_TXMASK_READYIE);
438 1.1 dbj }
439 1.1 dbj #endif
440 1.1 dbj
441 1.1 dbj return;
442 1.1 dbj }
443 1.1 dbj
444 1.1 dbj /****************************************************************/
445 1.1 dbj
446 1.1 dbj void
447 1.1 dbj mb8795_reset(sc)
448 1.1 dbj struct mb8795_softc *sc;
449 1.1 dbj {
450 1.1 dbj int s;
451 1.1 dbj
452 1.20 thorpej s = splnet();
453 1.1 dbj mb8795_init(sc);
454 1.1 dbj splx(s);
455 1.1 dbj }
456 1.1 dbj
457 1.1 dbj void
458 1.1 dbj mb8795_watchdog(ifp)
459 1.1 dbj struct ifnet *ifp;
460 1.1 dbj {
461 1.1 dbj struct mb8795_softc *sc = ifp->if_softc;
462 1.1 dbj
463 1.1 dbj log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
464 1.1 dbj ++ifp->if_oerrors;
465 1.1 dbj
466 1.1 dbj DPRINTF(("%s: %d input errors, %d input packets\n",
467 1.1 dbj sc->sc_dev.dv_xname, ifp->if_ierrors, ifp->if_ipackets));
468 1.1 dbj
469 1.1 dbj mb8795_reset(sc);
470 1.1 dbj }
471 1.1 dbj
472 1.1 dbj /*
473 1.1 dbj * Initialization of interface; set up initialization block
474 1.1 dbj * and transmit/receive descriptor rings.
475 1.1 dbj * @@@ error handling is bogus in here. memory leaks
476 1.1 dbj */
477 1.1 dbj void
478 1.1 dbj mb8795_init(sc)
479 1.1 dbj struct mb8795_softc *sc;
480 1.1 dbj {
481 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
482 1.1 dbj
483 1.1 dbj m_freem(sc->sc_tx_mb_head);
484 1.1 dbj sc->sc_tx_mb_head = NULL;
485 1.1 dbj sc->sc_tx_loaded = 0;
486 1.1 dbj
487 1.1 dbj {
488 1.1 dbj int i;
489 1.1 dbj for(i=0;i<MB8795_NRXBUFS;i++) {
490 1.1 dbj if (sc->sc_rx_mb_head[i]) {
491 1.1 dbj bus_dmamap_unload(sc->sc_rx_dmat, sc->sc_rx_dmamap[i]);
492 1.1 dbj m_freem(sc->sc_rx_mb_head[i]);
493 1.1 dbj }
494 1.1 dbj sc->sc_rx_mb_head[i] =
495 1.1 dbj mb8795_rxdmamap_load(sc, sc->sc_rx_dmamap[i]);
496 1.1 dbj }
497 1.1 dbj sc->sc_rx_loaded_idx = 0;
498 1.1 dbj sc->sc_rx_completed_idx = 0;
499 1.1 dbj sc->sc_rx_handled_idx = 0;
500 1.1 dbj }
501 1.1 dbj
502 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RESET, XE_RESET_MODE);
503 1.1 dbj
504 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXMODE, XE_TXMODE_LB_DISABLE);
505 1.1 dbj #if 0 /* This interrupt was sometimes failing to ack correctly
506 1.1 dbj * causing a loop @@@
507 1.1 dbj */
508 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK,
509 1.1 dbj XE_TXMASK_UNDERFLOWIE | XE_TXMASK_COLLIE | XE_TXMASK_COLL16IE
510 1.1 dbj | XE_TXMASK_PARERRIE);
511 1.1 dbj #else
512 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK, 0);
513 1.1 dbj #endif
514 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXSTAT, XE_TXSTAT_CLEAR);
515 1.1 dbj
516 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RXMODE, XE_RXMODE_NORMAL);
517 1.1 dbj
518 1.21 dbj #if 0
519 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RXMASK,
520 1.1 dbj XE_RXMASK_OKIE | XE_RXMASK_RESETIE | XE_RXMASK_SHORTIE |
521 1.1 dbj XE_RXMASK_ALIGNERRIE | XE_RXMASK_CRCERRIE | XE_RXMASK_OVERFLOWIE);
522 1.21 dbj #else
523 1.21 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RXMASK,
524 1.21 dbj XE_RXMASK_OKIE | XE_RXMASK_RESETIE | XE_RXMASK_SHORTIE);
525 1.21 dbj #endif
526 1.1 dbj
527 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RXSTAT, XE_RXSTAT_CLEAR);
528 1.1 dbj
529 1.1 dbj {
530 1.1 dbj int i;
531 1.1 dbj for(i=0;i<sizeof(sc->sc_enaddr);i++) {
532 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh,XE_ENADDR+i,sc->sc_enaddr[i]);
533 1.1 dbj }
534 1.1 dbj }
535 1.1 dbj
536 1.1 dbj DPRINTF(("%s: initializing ethernet %02x:%02x:%02x:%02x:%02x:%02x, size=%d\n",
537 1.1 dbj sc->sc_dev.dv_xname,
538 1.1 dbj sc->sc_enaddr[0],sc->sc_enaddr[1],sc->sc_enaddr[2],
539 1.1 dbj sc->sc_enaddr[3],sc->sc_enaddr[4],sc->sc_enaddr[5],
540 1.1 dbj sizeof(sc->sc_enaddr)));
541 1.1 dbj
542 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RESET, 0);
543 1.1 dbj
544 1.1 dbj ifp->if_flags |= IFF_RUNNING;
545 1.1 dbj ifp->if_flags &= ~IFF_OACTIVE;
546 1.1 dbj ifp->if_timer = 0;
547 1.1 dbj
548 1.1 dbj nextdma_init(sc->sc_tx_nd);
549 1.1 dbj nextdma_init(sc->sc_rx_nd);
550 1.1 dbj
551 1.16 dbj nextdma_start(sc->sc_rx_nd, DMACSR_SETREAD);
552 1.1 dbj
553 1.1 dbj if (ifp->if_snd.ifq_head != NULL) {
554 1.1 dbj mb8795_start(ifp);
555 1.1 dbj }
556 1.1 dbj }
557 1.1 dbj
558 1.1 dbj void
559 1.1 dbj mb8795_stop(sc)
560 1.1 dbj struct mb8795_softc *sc;
561 1.1 dbj {
562 1.1 dbj printf("%s: stop not implemented\n", sc->sc_dev.dv_xname);
563 1.1 dbj }
564 1.1 dbj
565 1.1 dbj
566 1.1 dbj void
567 1.1 dbj mb8795_shutdown(arg)
568 1.1 dbj void *arg;
569 1.1 dbj {
570 1.1 dbj struct mb8795_softc *sc = (struct mb8795_softc *)arg;
571 1.1 dbj mb8795_stop(sc);
572 1.1 dbj }
573 1.1 dbj
574 1.1 dbj /****************************************************************/
575 1.1 dbj int
576 1.1 dbj mb8795_ioctl(ifp, cmd, data)
577 1.1 dbj register struct ifnet *ifp;
578 1.1 dbj u_long cmd;
579 1.1 dbj caddr_t data;
580 1.1 dbj {
581 1.1 dbj register struct mb8795_softc *sc = ifp->if_softc;
582 1.1 dbj struct ifaddr *ifa = (struct ifaddr *)data;
583 1.1 dbj struct ifreq *ifr = (struct ifreq *)data;
584 1.1 dbj int s, error = 0;
585 1.1 dbj
586 1.20 thorpej s = splnet();
587 1.1 dbj
588 1.1 dbj switch (cmd) {
589 1.1 dbj
590 1.1 dbj case SIOCSIFADDR:
591 1.1 dbj ifp->if_flags |= IFF_UP;
592 1.1 dbj
593 1.1 dbj switch (ifa->ifa_addr->sa_family) {
594 1.1 dbj #ifdef INET
595 1.1 dbj case AF_INET:
596 1.1 dbj mb8795_init(sc);
597 1.1 dbj arp_ifinit(ifp, ifa);
598 1.1 dbj break;
599 1.1 dbj #endif
600 1.1 dbj #ifdef NS
601 1.1 dbj case AF_NS:
602 1.1 dbj {
603 1.1 dbj register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
604 1.1 dbj
605 1.1 dbj if (ns_nullhost(*ina))
606 1.1 dbj ina->x_host =
607 1.1 dbj *(union ns_host *)LLADDR(ifp->if_sadl);
608 1.1 dbj else {
609 1.1 dbj bcopy(ina->x_host.c_host,
610 1.1 dbj LLADDR(ifp->if_sadl),
611 1.1 dbj sizeof(sc->sc_enaddr));
612 1.1 dbj }
613 1.1 dbj /* Set new address. */
614 1.1 dbj mb8795_init(sc);
615 1.1 dbj break;
616 1.1 dbj }
617 1.1 dbj #endif
618 1.1 dbj default:
619 1.1 dbj mb8795_init(sc);
620 1.1 dbj break;
621 1.1 dbj }
622 1.1 dbj break;
623 1.1 dbj
624 1.1 dbj #if defined(CCITT) && defined(LLC)
625 1.1 dbj case SIOCSIFCONF_X25:
626 1.1 dbj ifp->if_flags |= IFF_UP;
627 1.1 dbj ifa->ifa_rtrequest = cons_rtrequest; /* XXX */
628 1.1 dbj error = x25_llcglue(PRC_IFUP, ifa->ifa_addr);
629 1.1 dbj if (error == 0)
630 1.1 dbj mb8795_init(sc);
631 1.1 dbj break;
632 1.1 dbj #endif /* CCITT && LLC */
633 1.1 dbj
634 1.1 dbj case SIOCSIFFLAGS:
635 1.1 dbj if ((ifp->if_flags & IFF_UP) == 0 &&
636 1.1 dbj (ifp->if_flags & IFF_RUNNING) != 0) {
637 1.1 dbj /*
638 1.1 dbj * If interface is marked down and it is running, then
639 1.1 dbj * stop it.
640 1.1 dbj */
641 1.1 dbj mb8795_stop(sc);
642 1.1 dbj ifp->if_flags &= ~IFF_RUNNING;
643 1.1 dbj } else if ((ifp->if_flags & IFF_UP) != 0 &&
644 1.1 dbj (ifp->if_flags & IFF_RUNNING) == 0) {
645 1.1 dbj /*
646 1.1 dbj * If interface is marked up and it is stopped, then
647 1.1 dbj * start it.
648 1.1 dbj */
649 1.1 dbj mb8795_init(sc);
650 1.1 dbj } else {
651 1.1 dbj /*
652 1.1 dbj * Reset the interface to pick up changes in any other
653 1.1 dbj * flags that affect hardware registers.
654 1.1 dbj */
655 1.1 dbj /*mb8795_stop(sc);*/
656 1.1 dbj mb8795_init(sc);
657 1.1 dbj }
658 1.1 dbj #ifdef XE_DEBUG
659 1.1 dbj if (ifp->if_flags & IFF_DEBUG)
660 1.1 dbj sc->sc_debug = 1;
661 1.1 dbj else
662 1.1 dbj sc->sc_debug = 0;
663 1.1 dbj #endif
664 1.1 dbj break;
665 1.1 dbj
666 1.1 dbj case SIOCADDMULTI:
667 1.1 dbj case SIOCDELMULTI:
668 1.1 dbj error = (cmd == SIOCADDMULTI) ?
669 1.1 dbj ether_addmulti(ifr, &sc->sc_ethercom) :
670 1.1 dbj ether_delmulti(ifr, &sc->sc_ethercom);
671 1.1 dbj
672 1.1 dbj if (error == ENETRESET) {
673 1.1 dbj /*
674 1.1 dbj * Multicast list has changed; set the hardware filter
675 1.1 dbj * accordingly.
676 1.1 dbj */
677 1.1 dbj mb8795_reset(sc);
678 1.1 dbj error = 0;
679 1.1 dbj }
680 1.1 dbj break;
681 1.1 dbj
682 1.1 dbj #if 0
683 1.1 dbj case SIOCGIFMEDIA:
684 1.1 dbj case SIOCSIFMEDIA:
685 1.1 dbj error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
686 1.1 dbj break;
687 1.1 dbj #endif
688 1.1 dbj
689 1.1 dbj default:
690 1.1 dbj error = EINVAL;
691 1.1 dbj break;
692 1.1 dbj }
693 1.1 dbj
694 1.1 dbj splx(s);
695 1.1 dbj
696 1.1 dbj #if 0
697 1.1 dbj DPRINTF(("DEBUG: mb8795_ioctl(0x%lx) returning %d\n",
698 1.1 dbj cmd,error));
699 1.1 dbj #endif
700 1.1 dbj
701 1.1 dbj return (error);
702 1.1 dbj }
703 1.1 dbj
704 1.1 dbj /*
705 1.1 dbj * Setup output on interface.
706 1.1 dbj * Get another datagram to send off of the interface queue, and map it to the
707 1.1 dbj * interface before starting the output.
708 1.20 thorpej * Called only at splnet or interrupt level.
709 1.1 dbj */
710 1.1 dbj void
711 1.1 dbj mb8795_start(ifp)
712 1.1 dbj struct ifnet *ifp;
713 1.1 dbj {
714 1.1 dbj int error;
715 1.1 dbj struct mb8795_softc *sc = ifp->if_softc;
716 1.1 dbj
717 1.1 dbj if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
718 1.1 dbj return;
719 1.1 dbj
720 1.1 dbj DPRINTF(("%s: mb8795_start()\n",sc->sc_dev.dv_xname));
721 1.1 dbj
722 1.1 dbj #if (defined(DIAGNOSTIC))
723 1.1 dbj {
724 1.1 dbj u_char txstat;
725 1.1 dbj txstat = bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_TXSTAT);
726 1.1 dbj if (!(txstat & XE_TXSTAT_READY)) {
727 1.6 dbj /* @@@ I used to panic here, but then it paniced once.
728 1.6 dbj * Let's see if I can just reset instead. [ dbj 980706.1900 ]
729 1.6 dbj */
730 1.6 dbj printf("%s: transmitter not ready\n", sc->sc_dev.dv_xname);
731 1.6 dbj mb8795_reset(sc);
732 1.6 dbj return;
733 1.1 dbj }
734 1.1 dbj }
735 1.1 dbj #endif
736 1.1 dbj
737 1.1 dbj #if 0
738 1.1 dbj return; /* @@@ Turn off xmit for debugging */
739 1.1 dbj #endif
740 1.1 dbj
741 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXSTAT, XE_TXSTAT_CLEAR);
742 1.1 dbj
743 1.1 dbj IF_DEQUEUE(&ifp->if_snd, sc->sc_tx_mb_head);
744 1.1 dbj if (sc->sc_tx_mb_head == 0) {
745 1.1 dbj printf("%s: No packet to start\n",
746 1.1 dbj sc->sc_dev.dv_xname);
747 1.1 dbj return;
748 1.1 dbj }
749 1.1 dbj
750 1.1 dbj ifp->if_timer = 5;
751 1.1 dbj
752 1.1 dbj /* The following is a next specific hack that should
753 1.1 dbj * probably be moved out of MI code.
754 1.1 dbj * This macro assumes it can move forward as needed
755 1.1 dbj * in the buffer. Perhaps it should zero the extra buffer.
756 1.1 dbj */
757 1.1 dbj #define REALIGN_DMABUF(s,l) \
758 1.1 dbj { (s) = ((u_char *)(((unsigned)(s)+DMA_BEGINALIGNMENT-1) \
759 1.1 dbj &~(DMA_BEGINALIGNMENT-1))); \
760 1.9 dbj (l) = ((u_char *)(((unsigned)((s)+(l))+DMA_ENDALIGNMENT-1) \
761 1.9 dbj &~(DMA_ENDALIGNMENT-1)))-(s);}
762 1.1 dbj
763 1.1 dbj #if 0
764 1.1 dbj error = bus_dmamap_load_mbuf(sc->sc_tx_dmat,
765 1.1 dbj sc->sc_tx_dmamap,
766 1.1 dbj sc->sc_tx_mb_head,
767 1.1 dbj BUS_DMA_NOWAIT);
768 1.1 dbj #else
769 1.1 dbj {
770 1.1 dbj u_char *buf = sc->sc_txbuf;
771 1.1 dbj int buflen = 0;
772 1.1 dbj struct mbuf *m = sc->sc_tx_mb_head;
773 1.1 dbj buflen = m->m_pkthdr.len;
774 1.1 dbj
775 1.1 dbj /* Fix runt packets, @@@ memory overrun */
776 1.1 dbj if (buflen < ETHERMIN+sizeof(struct ether_header)) {
777 1.1 dbj buflen = ETHERMIN+sizeof(struct ether_header);
778 1.1 dbj }
779 1.1 dbj
780 1.1 dbj buflen += 15;
781 1.1 dbj REALIGN_DMABUF(buf,buflen);
782 1.1 dbj if (buflen > 1520) {
783 1.1 dbj panic("%s: packet too long\n",sc->sc_dev.dv_xname);
784 1.1 dbj }
785 1.1 dbj
786 1.1 dbj {
787 1.1 dbj u_char *p = buf;
788 1.1 dbj for (m=sc->sc_tx_mb_head; m; m = m->m_next) {
789 1.1 dbj if (m->m_len == 0) continue;
790 1.1 dbj bcopy(mtod(m, u_char *), p, m->m_len);
791 1.1 dbj p += m->m_len;
792 1.1 dbj }
793 1.1 dbj }
794 1.1 dbj
795 1.1 dbj error = bus_dmamap_load(sc->sc_tx_dmat, sc->sc_tx_dmamap,
796 1.1 dbj buf,buflen,NULL,BUS_DMA_NOWAIT);
797 1.1 dbj }
798 1.1 dbj #endif
799 1.1 dbj if (error) {
800 1.1 dbj printf("%s: can't load mbuf chain, error = %d\n",
801 1.1 dbj sc->sc_dev.dv_xname, error);
802 1.1 dbj m_freem(sc->sc_tx_mb_head);
803 1.1 dbj sc->sc_tx_mb_head = NULL;
804 1.1 dbj return;
805 1.1 dbj }
806 1.1 dbj
807 1.1 dbj #ifdef DIAGNOSTIC
808 1.8 dbj if (sc->sc_tx_loaded != 0) {
809 1.1 dbj panic("%s: sc->sc_tx_loaded is %d",sc->sc_dev.dv_xname,
810 1.1 dbj sc->sc_tx_loaded);
811 1.1 dbj }
812 1.1 dbj #endif
813 1.1 dbj
814 1.1 dbj ifp->if_flags |= IFF_OACTIVE;
815 1.1 dbj
816 1.1 dbj bus_dmamap_sync(sc->sc_tx_dmat, sc->sc_tx_dmamap, 0,
817 1.1 dbj sc->sc_tx_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE);
818 1.1 dbj
819 1.16 dbj nextdma_start(sc->sc_tx_nd, DMACSR_SETWRITE);
820 1.1 dbj
821 1.1 dbj #if NBPFILTER > 0
822 1.1 dbj /*
823 1.1 dbj * Pass packet to bpf if there is a listener.
824 1.1 dbj */
825 1.1 dbj if (ifp->if_bpf)
826 1.1 dbj bpf_mtap(ifp->if_bpf, sc->sc_tx_mb_head);
827 1.1 dbj #endif
828 1.1 dbj
829 1.1 dbj }
830 1.1 dbj
831 1.1 dbj /****************************************************************/
832 1.1 dbj
833 1.1 dbj void
834 1.1 dbj mb8795_txdma_completed(map, arg)
835 1.1 dbj bus_dmamap_t map;
836 1.1 dbj void *arg;
837 1.1 dbj {
838 1.1 dbj struct mb8795_softc *sc = arg;
839 1.1 dbj
840 1.1 dbj DPRINTF(("%s: mb8795_txdma_completed()\n",sc->sc_dev.dv_xname));
841 1.1 dbj
842 1.1 dbj #ifdef DIAGNOSTIC
843 1.1 dbj if (!sc->sc_tx_loaded) {
844 1.1 dbj panic("%s: tx completed never loaded ",sc->sc_dev.dv_xname);
845 1.1 dbj }
846 1.1 dbj if (map != sc->sc_tx_dmamap) {
847 1.1 dbj panic("%s: unexpected tx completed map",sc->sc_dev.dv_xname);
848 1.1 dbj }
849 1.1 dbj
850 1.1 dbj #endif
851 1.1 dbj }
852 1.1 dbj
853 1.1 dbj void
854 1.1 dbj mb8795_txdma_shutdown(arg)
855 1.1 dbj void *arg;
856 1.1 dbj {
857 1.1 dbj struct mb8795_softc *sc = arg;
858 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
859 1.1 dbj
860 1.1 dbj DPRINTF(("%s: mb8795_txdma_shutdown()\n",sc->sc_dev.dv_xname));
861 1.1 dbj
862 1.1 dbj #ifdef DIAGNOSTIC
863 1.1 dbj if (!sc->sc_tx_loaded) {
864 1.1 dbj panic("%s: tx shutdown never loaded ",sc->sc_dev.dv_xname);
865 1.1 dbj }
866 1.1 dbj #endif
867 1.1 dbj
868 1.1 dbj {
869 1.1 dbj
870 1.1 dbj if (sc->sc_tx_loaded) {
871 1.1 dbj bus_dmamap_sync(sc->sc_tx_dmat, sc->sc_tx_dmamap,
872 1.1 dbj 0, sc->sc_tx_dmamap->dm_mapsize,
873 1.1 dbj BUS_DMASYNC_POSTWRITE);
874 1.1 dbj bus_dmamap_unload(sc->sc_tx_dmat, sc->sc_tx_dmamap);
875 1.1 dbj m_freem(sc->sc_tx_mb_head);
876 1.1 dbj sc->sc_tx_mb_head = NULL;
877 1.1 dbj
878 1.1 dbj sc->sc_tx_loaded--;
879 1.1 dbj }
880 1.1 dbj
881 1.1 dbj #ifdef DIAGNOSTIC
882 1.1 dbj if (sc->sc_tx_loaded != 0) {
883 1.1 dbj panic("%s: sc->sc_tx_loaded is %d",sc->sc_dev.dv_xname,
884 1.1 dbj sc->sc_tx_loaded);
885 1.1 dbj }
886 1.1 dbj #endif
887 1.1 dbj
888 1.1 dbj ifp->if_flags &= ~IFF_OACTIVE;
889 1.1 dbj
890 1.1 dbj ifp->if_timer = 0;
891 1.1 dbj
892 1.1 dbj if (ifp->if_snd.ifq_head != NULL) {
893 1.1 dbj mb8795_start(ifp);
894 1.1 dbj }
895 1.1 dbj
896 1.1 dbj }
897 1.1 dbj
898 1.1 dbj #if 0
899 1.1 dbj /* Enable ready interrupt */
900 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK,
901 1.1 dbj bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK)
902 1.1 dbj | XE_TXMASK_READYIE);
903 1.1 dbj #endif
904 1.1 dbj }
905 1.1 dbj
906 1.1 dbj
907 1.1 dbj void
908 1.1 dbj mb8795_rxdma_completed(map, arg)
909 1.1 dbj bus_dmamap_t map;
910 1.1 dbj void *arg;
911 1.1 dbj {
912 1.1 dbj struct mb8795_softc *sc = arg;
913 1.1 dbj
914 1.1 dbj sc->sc_rx_completed_idx++;
915 1.1 dbj sc->sc_rx_completed_idx %= MB8795_NRXBUFS;
916 1.1 dbj
917 1.1 dbj DPRINTF(("%s: mb8795_rxdma_completed(), sc->sc_rx_completed_idx = %d\n",
918 1.1 dbj sc->sc_dev.dv_xname, sc->sc_rx_completed_idx));
919 1.1 dbj
920 1.1 dbj #if (defined(DIAGNOSTIC))
921 1.1 dbj if (map != sc->sc_rx_dmamap[sc->sc_rx_completed_idx]) {
922 1.1 dbj panic("%s: Unexpected rx dmamap completed\n",
923 1.1 dbj sc->sc_dev.dv_xname);
924 1.1 dbj }
925 1.1 dbj #endif
926 1.1 dbj }
927 1.1 dbj
928 1.1 dbj void
929 1.1 dbj mb8795_rxdma_shutdown(arg)
930 1.1 dbj void *arg;
931 1.1 dbj {
932 1.1 dbj struct mb8795_softc *sc = arg;
933 1.1 dbj
934 1.21 dbj DPRINTF(("%s: mb8795_rxdma_shutdown(), restarting.\n",sc->sc_dev.dv_xname));
935 1.21 dbj
936 1.21 dbj #if 0
937 1.21 dbj /* Back up the dma pointers to only those that are completed */
938 1.21 dbj sc->sc_rx_loaded_idx = sc->sc_rx_completed_idx;
939 1.21 dbj #endif
940 1.21 dbj
941 1.21 dbj nextdma_start(sc->sc_rx_nd, DMACSR_SETREAD);
942 1.1 dbj }
943 1.1 dbj
944 1.1 dbj
945 1.1 dbj /*
946 1.1 dbj * load a dmamap with a freshly allocated mbuf
947 1.1 dbj */
948 1.1 dbj struct mbuf *
949 1.1 dbj mb8795_rxdmamap_load(sc,map)
950 1.1 dbj struct mb8795_softc *sc;
951 1.1 dbj bus_dmamap_t map;
952 1.1 dbj {
953 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
954 1.1 dbj struct mbuf *m;
955 1.1 dbj int error;
956 1.1 dbj
957 1.1 dbj MGETHDR(m, M_DONTWAIT, MT_DATA);
958 1.1 dbj if (m) {
959 1.1 dbj MCLGET(m, M_DONTWAIT);
960 1.1 dbj if ((m->m_flags & M_EXT) == 0) {
961 1.1 dbj m_freem(m);
962 1.1 dbj m = NULL;
963 1.1 dbj } else {
964 1.1 dbj m->m_len = MCLBYTES;
965 1.1 dbj }
966 1.1 dbj }
967 1.1 dbj if (!m) {
968 1.1 dbj /* @@@ Handle this gracefully by reusing a scratch buffer
969 1.1 dbj * or something.
970 1.1 dbj */
971 1.1 dbj panic("Unable to get memory for incoming ethernet\n");
972 1.1 dbj }
973 1.1 dbj
974 1.1 dbj /* Align buffer, @@@ next specific.
975 1.1 dbj * perhaps should be using M_ALIGN here instead?
976 1.1 dbj * First we give us a little room to align with.
977 1.1 dbj */
978 1.1 dbj {
979 1.1 dbj u_char *buf = m->m_data;
980 1.1 dbj int buflen = m->m_len;
981 1.9 dbj buflen -= DMA_ENDALIGNMENT+DMA_BEGINALIGNMENT;
982 1.1 dbj REALIGN_DMABUF(buf, buflen);
983 1.1 dbj m->m_data = buf;
984 1.1 dbj m->m_len = buflen;
985 1.1 dbj }
986 1.1 dbj
987 1.1 dbj m->m_pkthdr.rcvif = ifp;
988 1.1 dbj m->m_pkthdr.len = m->m_len;
989 1.1 dbj
990 1.1 dbj error = bus_dmamap_load_mbuf(sc->sc_rx_dmat,
991 1.1 dbj map, m, BUS_DMA_NOWAIT);
992 1.1 dbj
993 1.1 dbj bus_dmamap_sync(sc->sc_rx_dmat, map, 0,
994 1.1 dbj map->dm_mapsize, BUS_DMASYNC_PREREAD);
995 1.1 dbj
996 1.1 dbj if (error) {
997 1.1 dbj DPRINTF(("DEBUG: m->m_data = 0x%08x, m->m_len = %d\n",
998 1.1 dbj m->m_data, m->m_len));
999 1.1 dbj DPRINTF(("DEBUG: MCLBYTES = %d, map->_dm_size = %d\n",
1000 1.1 dbj MCLBYTES, map->_dm_size));
1001 1.1 dbj
1002 1.1 dbj panic("%s: can't load rx mbuf chain, error = %d\n",
1003 1.1 dbj sc->sc_dev.dv_xname, error);
1004 1.1 dbj m_freem(m);
1005 1.1 dbj m = NULL;
1006 1.1 dbj }
1007 1.1 dbj
1008 1.1 dbj return(m);
1009 1.1 dbj }
1010 1.1 dbj
1011 1.1 dbj bus_dmamap_t
1012 1.1 dbj mb8795_rxdma_continue(arg)
1013 1.1 dbj void *arg;
1014 1.1 dbj {
1015 1.1 dbj struct mb8795_softc *sc = arg;
1016 1.1 dbj bus_dmamap_t map = NULL;
1017 1.1 dbj
1018 1.1 dbj /*
1019 1.1 dbj * Currently, starts dumping new packets if the buffers
1020 1.1 dbj * fill up. This should probably reclaim unhandled
1021 1.1 dbj * buffers instead so we drop older packets instead
1022 1.1 dbj * of newer ones.
1023 1.1 dbj */
1024 1.1 dbj if (((sc->sc_rx_loaded_idx+1)%MB8795_NRXBUFS) != sc->sc_rx_handled_idx) {
1025 1.1 dbj sc->sc_rx_loaded_idx++;
1026 1.1 dbj sc->sc_rx_loaded_idx %= MB8795_NRXBUFS;
1027 1.1 dbj map = sc->sc_rx_dmamap[sc->sc_rx_loaded_idx];
1028 1.1 dbj
1029 1.1 dbj DPRINTF(("%s: mb8795_rxdma_continue() sc->sc_rx_loaded_idx = %d\nn",
1030 1.1 dbj sc->sc_dev.dv_xname,sc->sc_rx_loaded_idx));
1031 1.1 dbj }
1032 1.1 dbj #if (defined(DIAGNOSTIC))
1033 1.1 dbj else {
1034 1.17 dbj panic("%s: out of receive DMA buffers\n",sc->sc_dev.dv_xname);
1035 1.1 dbj }
1036 1.1 dbj #endif
1037 1.1 dbj
1038 1.1 dbj return(map);
1039 1.1 dbj }
1040 1.1 dbj
1041 1.1 dbj bus_dmamap_t
1042 1.1 dbj mb8795_txdma_continue(arg)
1043 1.1 dbj void *arg;
1044 1.1 dbj {
1045 1.1 dbj struct mb8795_softc *sc = arg;
1046 1.8 dbj bus_dmamap_t map;
1047 1.1 dbj
1048 1.1 dbj DPRINTF(("%s: mb8795_txdma_continue()\n",sc->sc_dev.dv_xname));
1049 1.1 dbj
1050 1.8 dbj if (sc->sc_tx_loaded) {
1051 1.8 dbj map = NULL;
1052 1.8 dbj } else {
1053 1.8 dbj map = sc->sc_tx_dmamap;
1054 1.8 dbj sc->sc_tx_loaded++;
1055 1.8 dbj }
1056 1.8 dbj
1057 1.1 dbj #ifdef DIAGNOSTIC
1058 1.1 dbj if (sc->sc_tx_loaded != 1) {
1059 1.8 dbj panic("%s: sc->sc_tx_loaded is %d",sc->sc_dev.dv_xname,
1060 1.8 dbj sc->sc_tx_loaded);
1061 1.1 dbj }
1062 1.1 dbj #endif
1063 1.1 dbj
1064 1.1 dbj return(map);
1065 1.1 dbj }
1066 1.1 dbj
1067 1.1 dbj /****************************************************************/
1068