mb8795.c revision 1.4 1 1.4 jonathan /* $NetBSD: mb8795.c,v 1.4 1998/07/05 03:14:42 jonathan Exp $ */
2 1.1 dbj /*
3 1.1 dbj * Copyright (c) 1998 Darrin B. Jewell
4 1.1 dbj * All rights reserved.
5 1.1 dbj *
6 1.1 dbj * Redistribution and use in source and binary forms, with or without
7 1.1 dbj * modification, are permitted provided that the following conditions
8 1.1 dbj * are met:
9 1.1 dbj * 1. Redistributions of source code must retain the above copyright
10 1.1 dbj * notice, this list of conditions and the following disclaimer.
11 1.1 dbj * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 dbj * notice, this list of conditions and the following disclaimer in the
13 1.1 dbj * documentation and/or other materials provided with the distribution.
14 1.1 dbj * 3. All advertising materials mentioning features or use of this software
15 1.1 dbj * must display the following acknowledgement:
16 1.1 dbj * This product includes software developed by Darrin B. Jewell
17 1.1 dbj * 4. The name of the author may not be used to endorse or promote products
18 1.1 dbj * derived from this software without specific prior written permission
19 1.1 dbj *
20 1.1 dbj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 1.1 dbj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 1.1 dbj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 1.1 dbj * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 1.1 dbj * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 1.1 dbj * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 1.1 dbj * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 1.1 dbj * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 1.1 dbj * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 1.1 dbj * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 1.1 dbj */
31 1.1 dbj
32 1.2 jonathan #include "opt_inet.h"
33 1.3 jonathan #include "opt_ccitt.h"
34 1.4 jonathan #include "opt_llc.h"
35 1.1 dbj #include "bpfilter.h"
36 1.1 dbj #include "rnd.h"
37 1.1 dbj
38 1.1 dbj #include <sys/param.h>
39 1.1 dbj #include <sys/systm.h>
40 1.1 dbj #include <sys/mbuf.h>
41 1.1 dbj #include <sys/syslog.h>
42 1.1 dbj #include <sys/socket.h>
43 1.1 dbj #include <sys/device.h>
44 1.1 dbj #include <sys/malloc.h>
45 1.1 dbj #include <sys/ioctl.h>
46 1.1 dbj #include <sys/errno.h>
47 1.1 dbj #if NRND > 0
48 1.1 dbj #include <sys/rnd.h>
49 1.1 dbj #endif
50 1.1 dbj
51 1.1 dbj #include <net/if.h>
52 1.1 dbj #include <net/if_dl.h>
53 1.1 dbj #include <net/if_ether.h>
54 1.1 dbj
55 1.1 dbj #if 0
56 1.1 dbj #include <net/if_media.h>
57 1.1 dbj #endif
58 1.1 dbj
59 1.1 dbj #ifdef INET
60 1.1 dbj #include <netinet/in.h>
61 1.1 dbj #include <netinet/if_inarp.h>
62 1.1 dbj #include <netinet/in_systm.h>
63 1.1 dbj #include <netinet/in_var.h>
64 1.1 dbj #include <netinet/ip.h>
65 1.1 dbj #endif
66 1.1 dbj
67 1.1 dbj #ifdef NS
68 1.1 dbj #include <netns/ns.h>
69 1.1 dbj #include <netns/ns_if.h>
70 1.1 dbj #endif
71 1.1 dbj
72 1.1 dbj #if defined(CCITT) && defined(LLC)
73 1.1 dbj #include <sys/socketvar.h>
74 1.1 dbj #include <netccitt/x25.h>
75 1.1 dbj #include <netccitt/pk.h>
76 1.1 dbj #include <netccitt/pk_var.h>
77 1.1 dbj #include <netccitt/pk_extern.h>
78 1.1 dbj #endif
79 1.1 dbj
80 1.1 dbj #if NBPFILTER > 0
81 1.1 dbj #include <net/bpf.h>
82 1.1 dbj #include <net/bpfdesc.h>
83 1.1 dbj #endif
84 1.1 dbj
85 1.1 dbj #include <machine/cpu.h>
86 1.1 dbj #include <machine/bus.h>
87 1.1 dbj #include <machine/intr.h>
88 1.1 dbj
89 1.1 dbj /* @@@ this is here for the REALIGN_DMABUF hack below */
90 1.1 dbj #include "nextdmareg.h"
91 1.1 dbj #include "nextdmavar.h"
92 1.1 dbj
93 1.1 dbj #include "mb8795reg.h"
94 1.1 dbj #include "mb8795var.h"
95 1.1 dbj
96 1.1 dbj #if 0
97 1.1 dbj #define XE_DEBUG
98 1.1 dbj #endif
99 1.1 dbj
100 1.1 dbj #ifdef XE_DEBUG
101 1.1 dbj #define DPRINTF(x) printf x;
102 1.1 dbj #else
103 1.1 dbj #define DPRINTF(x)
104 1.1 dbj #endif
105 1.1 dbj
106 1.1 dbj
107 1.1 dbj /*
108 1.1 dbj * Support for
109 1.1 dbj * Fujitsu Ethernet Data Link Controller (MB8795)
110 1.1 dbj * and the Fujitsu Manchester Encoder/Decoder (MB502).
111 1.1 dbj */
112 1.1 dbj
113 1.1 dbj int debugipkt = 0;
114 1.1 dbj
115 1.1 dbj
116 1.1 dbj void mb8795_shutdown __P((void *));
117 1.1 dbj
118 1.1 dbj #if 0
119 1.1 dbj int mb8795_mediachange __P((struct ifnet *));
120 1.1 dbj void mb8795_mediastatus __P((struct ifnet *, struct ifmediareq *));
121 1.1 dbj #endif
122 1.1 dbj
123 1.1 dbj struct mbuf * mb8795_rxdmamap_load __P((struct mb8795_softc *,
124 1.1 dbj bus_dmamap_t map));
125 1.1 dbj
126 1.1 dbj bus_dmamap_t mb8795_rxdma_continue __P((void *));
127 1.1 dbj void mb8795_rxdma_completed __P((bus_dmamap_t,void *));
128 1.1 dbj bus_dmamap_t mb8795_txdma_continue __P((void *));
129 1.1 dbj void mb8795_txdma_completed __P((bus_dmamap_t,void *));
130 1.1 dbj void mb8795_rxdma_shutdown __P((void *));
131 1.1 dbj void mb8795_txdma_shutdown __P((void *));
132 1.1 dbj bus_dmamap_t mb8795_txdma_restart __P((bus_dmamap_t,void *));
133 1.1 dbj
134 1.1 dbj void
135 1.1 dbj mb8795_config(sc)
136 1.1 dbj struct mb8795_softc *sc;
137 1.1 dbj {
138 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
139 1.1 dbj
140 1.1 dbj DPRINTF(("%s: mb8795_config()\n",sc->sc_dev.dv_xname));
141 1.1 dbj
142 1.1 dbj /* Initialize ifnet structure. */
143 1.1 dbj bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
144 1.1 dbj ifp->if_softc = sc;
145 1.1 dbj ifp->if_start = mb8795_start;
146 1.1 dbj ifp->if_ioctl = mb8795_ioctl;
147 1.1 dbj ifp->if_watchdog = mb8795_watchdog;
148 1.1 dbj ifp->if_flags =
149 1.1 dbj IFF_BROADCAST | IFF_NOTRAILERS;
150 1.1 dbj
151 1.1 dbj #if 0
152 1.1 dbj /* Initialize ifmedia structures. */
153 1.1 dbj ifmedia_init(&sc->sc_media, 0, mb8795_mediachange, mb8795_mediastatus);
154 1.1 dbj if (sc->sc_supmedia != NULL) {
155 1.1 dbj int i;
156 1.1 dbj for (i = 0; i < sc->sc_nsupmedia; i++)
157 1.1 dbj ifmedia_add(&sc->sc_media, sc->sc_supmedia[i],
158 1.1 dbj 0, NULL);
159 1.1 dbj ifmedia_set(&sc->sc_media, sc->sc_defaultmedia);
160 1.1 dbj } else {
161 1.1 dbj ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
162 1.1 dbj ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
163 1.1 dbj }
164 1.1 dbj #endif
165 1.1 dbj
166 1.1 dbj /* Attach the interface. */
167 1.1 dbj if_attach(ifp);
168 1.1 dbj ether_ifattach(ifp, sc->sc_enaddr);
169 1.1 dbj
170 1.1 dbj /* decrease the mtu on this interface to deal with
171 1.1 dbj * alignment problems
172 1.1 dbj */
173 1.1 dbj ifp->if_mtu -= 16;
174 1.1 dbj
175 1.1 dbj #if NBPFILTER > 0
176 1.1 dbj bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header));
177 1.1 dbj #endif
178 1.1 dbj
179 1.1 dbj sc->sc_sh = shutdownhook_establish(mb8795_shutdown, sc);
180 1.1 dbj if (sc->sc_sh == NULL)
181 1.1 dbj panic("mb8795_config: can't establish shutdownhook");
182 1.1 dbj
183 1.1 dbj #if NRND > 0
184 1.1 dbj rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname,
185 1.1 dbj RND_TYPE_NET);
186 1.1 dbj #endif
187 1.1 dbj
188 1.1 dbj /* Initialize the dma maps */
189 1.1 dbj {
190 1.1 dbj int error;
191 1.1 dbj if ((error = bus_dmamap_create(sc->sc_tx_dmat, MCLBYTES,
192 1.1 dbj (MCLBYTES/MSIZE), MCLBYTES, 0, BUS_DMA_ALLOCNOW,
193 1.1 dbj &sc->sc_tx_dmamap)) != 0) {
194 1.1 dbj panic("%s: can't create tx DMA map, error = %d\n",
195 1.1 dbj sc->sc_dev.dv_xname, error);
196 1.1 dbj }
197 1.1 dbj {
198 1.1 dbj int i;
199 1.1 dbj for(i=0;i<MB8795_NRXBUFS;i++) {
200 1.1 dbj if ((error = bus_dmamap_create(sc->sc_rx_dmat, MCLBYTES,
201 1.1 dbj (MCLBYTES/MSIZE), MCLBYTES, 0, BUS_DMA_ALLOCNOW,
202 1.1 dbj &sc->sc_rx_dmamap[i])) != 0) {
203 1.1 dbj panic("%s: can't create rx DMA map, error = %d\n",
204 1.1 dbj sc->sc_dev.dv_xname, error);
205 1.1 dbj }
206 1.1 dbj sc->sc_rx_mb_head[i] = NULL;
207 1.1 dbj }
208 1.1 dbj sc->sc_rx_loaded_idx = 0;
209 1.1 dbj sc->sc_rx_completed_idx = 0;
210 1.1 dbj sc->sc_rx_handled_idx = 0;
211 1.1 dbj }
212 1.1 dbj }
213 1.1 dbj
214 1.1 dbj /* @@@ more next hacks
215 1.1 dbj * the 2000 covers at least a 1500 mtu + headers
216 1.1 dbj * + DMA_BEGINALIGNMENT+ ENDMA_ENDALIGNMENT
217 1.1 dbj */
218 1.1 dbj sc->sc_txbuf = malloc(2000, M_DEVBUF, M_NOWAIT);
219 1.1 dbj if (!sc->sc_txbuf) panic("%s: can't malloc tx DMA buffer",
220 1.1 dbj sc->sc_dev.dv_xname);
221 1.1 dbj
222 1.1 dbj sc->sc_tx_mb_head = NULL;
223 1.1 dbj sc->sc_tx_loaded = 0;
224 1.1 dbj
225 1.1 dbj sc->sc_tx_nd->nd_chaining_flag = 0;
226 1.1 dbj sc->sc_tx_nd->nd_shutdown_cb = mb8795_txdma_shutdown;
227 1.1 dbj sc->sc_tx_nd->nd_continue_cb = mb8795_txdma_continue;
228 1.1 dbj sc->sc_tx_nd->nd_completed_cb = mb8795_txdma_completed;
229 1.1 dbj sc->sc_tx_nd->nd_cb_arg = sc;
230 1.1 dbj
231 1.1 dbj sc->sc_rx_nd->nd_chaining_flag = 1;
232 1.1 dbj sc->sc_rx_nd->nd_shutdown_cb = mb8795_rxdma_shutdown;
233 1.1 dbj sc->sc_rx_nd->nd_continue_cb = mb8795_rxdma_continue;
234 1.1 dbj sc->sc_rx_nd->nd_completed_cb = mb8795_rxdma_completed;
235 1.1 dbj sc->sc_rx_nd->nd_cb_arg = sc;
236 1.1 dbj
237 1.1 dbj DPRINTF(("%s: leaving mb8795_config()\n",sc->sc_dev.dv_xname));
238 1.1 dbj }
239 1.1 dbj
240 1.1 dbj
241 1.1 dbj /****************************************************************/
242 1.1 dbj
243 1.1 dbj #define XCHR(x) "0123456789abcdef"[(x) & 0xf]
244 1.1 dbj static void
245 1.1 dbj hex_dump(unsigned char *pkt, size_t len)
246 1.1 dbj {
247 1.1 dbj size_t i, j;
248 1.1 dbj
249 1.1 dbj printf("0000: ");
250 1.1 dbj for(i=0; i<len; i++) {
251 1.1 dbj printf("%c%c ", XCHR(pkt[i]>>4), XCHR(pkt[i]));
252 1.1 dbj if ((i+1) % 16 == 0) {
253 1.1 dbj printf(" %c", '"');
254 1.1 dbj for(j=0; j<16; j++)
255 1.1 dbj printf("%c", pkt[i-15+j]>=32 && pkt[i-15+j]<127?pkt[i-15+j]:'.');
256 1.1 dbj printf("%c\n%c%c%c%c: ", '"', XCHR((i+1)>>12),
257 1.1 dbj XCHR((i+1)>>8), XCHR((i+1)>>4), XCHR(i+1));
258 1.1 dbj }
259 1.1 dbj }
260 1.1 dbj printf("\n");
261 1.1 dbj }
262 1.1 dbj
263 1.1 dbj
264 1.1 dbj /*
265 1.1 dbj * Controller receive interrupt.
266 1.1 dbj */
267 1.1 dbj void
268 1.1 dbj mb8795_rint(sc)
269 1.1 dbj struct mb8795_softc *sc;
270 1.1 dbj {
271 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
272 1.1 dbj int error = 0;
273 1.1 dbj u_char rxstat;
274 1.1 dbj u_char rxmask;
275 1.1 dbj
276 1.1 dbj rxstat = bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_RXSTAT);
277 1.1 dbj rxmask = bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_RXMASK);
278 1.1 dbj
279 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RXSTAT, XE_RXSTAT_CLEAR);
280 1.1 dbj
281 1.1 dbj #if 0
282 1.1 dbj DPRINTF(("%s: rx interrupt, rxstat = %b\n",
283 1.1 dbj sc->sc_dev.dv_xname, rxstat, XE_RXSTAT_BITS));
284 1.1 dbj #endif
285 1.1 dbj
286 1.1 dbj if (rxstat & XE_RXSTAT_RESET) {
287 1.1 dbj DPRINTF(("%s: rx reset packet\n",
288 1.1 dbj sc->sc_dev.dv_xname));
289 1.1 dbj error++;
290 1.1 dbj }
291 1.1 dbj if (rxstat & XE_RXSTAT_SHORT) {
292 1.1 dbj DPRINTF(("%s: rx short packet\n",
293 1.1 dbj sc->sc_dev.dv_xname));
294 1.1 dbj error++;
295 1.1 dbj }
296 1.1 dbj if (rxstat & XE_RXSTAT_ALIGNERR) {
297 1.1 dbj DPRINTF(("%s: rx alignment error\n",
298 1.1 dbj sc->sc_dev.dv_xname));
299 1.1 dbj error++;
300 1.1 dbj }
301 1.1 dbj if (rxstat & XE_RXSTAT_CRCERR) {
302 1.1 dbj DPRINTF(("%s: rx CRC error\n",
303 1.1 dbj sc->sc_dev.dv_xname));
304 1.1 dbj error++;
305 1.1 dbj }
306 1.1 dbj if (rxstat & XE_RXSTAT_OVERFLOW) {
307 1.1 dbj DPRINTF(("%s: rx overflow error\n",
308 1.1 dbj sc->sc_dev.dv_xname));
309 1.1 dbj error++;
310 1.1 dbj }
311 1.1 dbj
312 1.1 dbj if (error) {
313 1.1 dbj ifp->if_ierrors++;
314 1.1 dbj /* @@@ handle more gracefully, free memory, etc. */
315 1.1 dbj }
316 1.1 dbj
317 1.1 dbj if (rxstat & XE_RXSTAT_OK) {
318 1.1 dbj int s;
319 1.1 dbj s = spldma();
320 1.1 dbj
321 1.1 dbj while(sc->sc_rx_handled_idx != sc->sc_rx_completed_idx) {
322 1.1 dbj struct mbuf *m;
323 1.1 dbj bus_dmamap_t map;
324 1.1 dbj
325 1.1 dbj sc->sc_rx_handled_idx++;
326 1.1 dbj sc->sc_rx_handled_idx %= MB8795_NRXBUFS;
327 1.1 dbj
328 1.1 dbj /* Should probably not do this much while interrupts
329 1.1 dbj * are disabled, but for now we will.
330 1.1 dbj */
331 1.1 dbj
332 1.1 dbj map = sc->sc_rx_dmamap[sc->sc_rx_handled_idx];
333 1.1 dbj m = sc->sc_rx_mb_head[sc->sc_rx_handled_idx];
334 1.1 dbj
335 1.1 dbj bus_dmamap_sync(sc->sc_rx_dmat, map,
336 1.1 dbj 0, map->dm_mapsize, BUS_DMASYNC_POSTREAD);
337 1.1 dbj
338 1.1 dbj
339 1.1 dbj /* Find receive length and chop off CRC */
340 1.1 dbj /* @@@ assumes packet is all in first segment
341 1.1 dbj * also assumes segment length is length of packet.
342 1.1 dbj * see comment in nextdma.c nextdma_intr();
343 1.1 dbj */
344 1.1 dbj m->m_pkthdr.len = map->dm_segs[0].ds_len-4;
345 1.1 dbj m->m_len = map->dm_segs[0].ds_len-4;
346 1.1 dbj m->m_pkthdr.rcvif = ifp;
347 1.1 dbj
348 1.1 dbj bus_dmamap_unload(sc->sc_rx_dmat, map);
349 1.1 dbj
350 1.1 dbj /* Install a fresh mbuf for next packet */
351 1.1 dbj
352 1.1 dbj sc->sc_rx_mb_head[sc->sc_rx_handled_idx] =
353 1.1 dbj mb8795_rxdmamap_load(sc,map);
354 1.1 dbj
355 1.1 dbj /* enable interrupts while we process the packet */
356 1.1 dbj splx(s);
357 1.1 dbj
358 1.1 dbj #if defined(XE_DEBUG)
359 1.1 dbj /* Peek at the packet */
360 1.1 dbj DPRINTF(("%s: received packet, at VA 0x%08x-0x%08x,len %d\n",
361 1.1 dbj sc->sc_dev.dv_xname,mtod(m,u_char *),mtod(m,u_char *)+m->m_len,m->m_len));
362 1.1 dbj #if 0
363 1.1 dbj hex_dump(mtod(m,u_char *), m->m_pkthdr.len < 255 ? m->m_pkthdr.len : 128 );
364 1.1 dbj #endif
365 1.1 dbj #endif
366 1.1 dbj
367 1.1 dbj {
368 1.1 dbj struct ether_header *eh;
369 1.1 dbj
370 1.1 dbj ifp->if_ipackets++;
371 1.1 dbj debugipkt++;
372 1.1 dbj
373 1.1 dbj /* We assume that the header fit entirely in one mbuf. */
374 1.1 dbj eh = mtod(m, struct ether_header *);
375 1.1 dbj
376 1.1 dbj /* Pass the packet up, with the ether header sort-of removed. */
377 1.1 dbj m_adj(m, sizeof(struct ether_header));
378 1.1 dbj ether_input(ifp, eh, m);
379 1.1 dbj }
380 1.1 dbj
381 1.1 dbj s = spldma();
382 1.1 dbj
383 1.1 dbj }
384 1.1 dbj
385 1.1 dbj splx(s);
386 1.1 dbj
387 1.1 dbj }
388 1.1 dbj
389 1.1 dbj DPRINTF(("%s: rx interrupt, rxstat = %b\n",
390 1.1 dbj sc->sc_dev.dv_xname, rxstat, XE_RXSTAT_BITS));
391 1.1 dbj
392 1.1 dbj #if 0 && defined(XE_DEBUG)
393 1.1 dbj {
394 1.1 dbj DPRINTF(("rxstat = 0x%b\n",
395 1.1 dbj bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_RXSTAT), XE_RXSTAT_BITS));
396 1.1 dbj DPRINTF(("rxmask = 0x%b\n",
397 1.1 dbj bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_RXMASK), XE_RXMASK_BITS));
398 1.1 dbj DPRINTF(("rxmode = 0x%b\n",
399 1.1 dbj bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_RXMODE), XE_RXMODE_BITS));
400 1.1 dbj }
401 1.1 dbj #endif
402 1.1 dbj
403 1.1 dbj return;
404 1.1 dbj }
405 1.1 dbj
406 1.1 dbj /*
407 1.1 dbj * Controller transmit interrupt.
408 1.1 dbj */
409 1.1 dbj void
410 1.1 dbj mb8795_tint(sc)
411 1.1 dbj struct mb8795_softc *sc;
412 1.1 dbj
413 1.1 dbj {
414 1.1 dbj int reset = 0;
415 1.1 dbj u_char txstat;
416 1.1 dbj u_char txmask;
417 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
418 1.1 dbj
419 1.1 dbj txstat = bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_TXSTAT);
420 1.1 dbj txmask = bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK);
421 1.1 dbj
422 1.1 dbj #if 0
423 1.1 dbj DPRINTF(("%s: tx interrupt, txstat = %b\n",
424 1.1 dbj sc->sc_dev.dv_xname, txstat, XE_TXSTAT_BITS));
425 1.1 dbj #endif
426 1.1 dbj
427 1.1 dbj if (txstat & XE_TXSTAT_SHORTED) {
428 1.1 dbj printf("%s: tx cable shorted\n", sc->sc_dev.dv_xname);
429 1.1 dbj ifp->if_oerrors++;
430 1.1 dbj }
431 1.1 dbj if (txstat & XE_TXSTAT_UNDERFLOW) {
432 1.1 dbj printf("%s: tx underflow\n", sc->sc_dev.dv_xname);
433 1.1 dbj ifp->if_oerrors++;
434 1.1 dbj }
435 1.1 dbj if (txstat & XE_TXSTAT_COLLERR) {
436 1.1 dbj DPRINTF(("%s: tx collision\n", sc->sc_dev.dv_xname));
437 1.1 dbj ifp->if_collisions++;
438 1.1 dbj }
439 1.1 dbj if (txstat & XE_TXSTAT_COLLERR16) {
440 1.1 dbj printf("%s: tx 16th collision\n", sc->sc_dev.dv_xname);
441 1.1 dbj ifp->if_oerrors++;
442 1.1 dbj ifp->if_collisions += 16;
443 1.1 dbj }
444 1.1 dbj
445 1.1 dbj if (reset) {
446 1.1 dbj mb8795_reset(sc);
447 1.1 dbj return;
448 1.1 dbj }
449 1.1 dbj
450 1.1 dbj #if 0
451 1.1 dbj if (txstat & XE_TXSTAT_READY) {
452 1.1 dbj
453 1.1 dbj panic("%s: unexpected tx interrupt %b",
454 1.1 dbj sc->sc_dev.dv_xname,txstat,XE_TXSTAT_BITS);
455 1.1 dbj
456 1.1 dbj /* turn interrupt off */
457 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK,
458 1.1 dbj txmask & ~XE_TXMASK_READYIE);
459 1.1 dbj }
460 1.1 dbj #endif
461 1.1 dbj
462 1.1 dbj return;
463 1.1 dbj }
464 1.1 dbj
465 1.1 dbj /****************************************************************/
466 1.1 dbj
467 1.1 dbj void
468 1.1 dbj mb8795_reset(sc)
469 1.1 dbj struct mb8795_softc *sc;
470 1.1 dbj {
471 1.1 dbj int s;
472 1.1 dbj
473 1.1 dbj s = splimp();
474 1.1 dbj mb8795_init(sc);
475 1.1 dbj splx(s);
476 1.1 dbj }
477 1.1 dbj
478 1.1 dbj void
479 1.1 dbj mb8795_watchdog(ifp)
480 1.1 dbj struct ifnet *ifp;
481 1.1 dbj {
482 1.1 dbj struct mb8795_softc *sc = ifp->if_softc;
483 1.1 dbj
484 1.1 dbj log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
485 1.1 dbj ++ifp->if_oerrors;
486 1.1 dbj
487 1.1 dbj DPRINTF(("%s: %d input errors, %d input packets\n",
488 1.1 dbj sc->sc_dev.dv_xname, ifp->if_ierrors, ifp->if_ipackets));
489 1.1 dbj
490 1.1 dbj mb8795_reset(sc);
491 1.1 dbj }
492 1.1 dbj
493 1.1 dbj /*
494 1.1 dbj * Initialization of interface; set up initialization block
495 1.1 dbj * and transmit/receive descriptor rings.
496 1.1 dbj * @@@ error handling is bogus in here. memory leaks
497 1.1 dbj */
498 1.1 dbj void
499 1.1 dbj mb8795_init(sc)
500 1.1 dbj struct mb8795_softc *sc;
501 1.1 dbj {
502 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
503 1.1 dbj
504 1.1 dbj m_freem(sc->sc_tx_mb_head);
505 1.1 dbj sc->sc_tx_mb_head = NULL;
506 1.1 dbj sc->sc_tx_loaded = 0;
507 1.1 dbj
508 1.1 dbj {
509 1.1 dbj int i;
510 1.1 dbj for(i=0;i<MB8795_NRXBUFS;i++) {
511 1.1 dbj if (sc->sc_rx_mb_head[i]) {
512 1.1 dbj bus_dmamap_unload(sc->sc_rx_dmat, sc->sc_rx_dmamap[i]);
513 1.1 dbj m_freem(sc->sc_rx_mb_head[i]);
514 1.1 dbj }
515 1.1 dbj sc->sc_rx_mb_head[i] =
516 1.1 dbj mb8795_rxdmamap_load(sc, sc->sc_rx_dmamap[i]);
517 1.1 dbj }
518 1.1 dbj sc->sc_rx_loaded_idx = 0;
519 1.1 dbj sc->sc_rx_completed_idx = 0;
520 1.1 dbj sc->sc_rx_handled_idx = 0;
521 1.1 dbj }
522 1.1 dbj
523 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RESET, XE_RESET_MODE);
524 1.1 dbj
525 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXMODE, XE_TXMODE_LB_DISABLE);
526 1.1 dbj #if 0 /* This interrupt was sometimes failing to ack correctly
527 1.1 dbj * causing a loop @@@
528 1.1 dbj */
529 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK,
530 1.1 dbj XE_TXMASK_UNDERFLOWIE | XE_TXMASK_COLLIE | XE_TXMASK_COLL16IE
531 1.1 dbj | XE_TXMASK_PARERRIE);
532 1.1 dbj #else
533 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK, 0);
534 1.1 dbj #endif
535 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXSTAT, XE_TXSTAT_CLEAR);
536 1.1 dbj
537 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RXMODE, XE_RXMODE_NORMAL);
538 1.1 dbj
539 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RXMASK,
540 1.1 dbj XE_RXMASK_OKIE | XE_RXMASK_RESETIE | XE_RXMASK_SHORTIE |
541 1.1 dbj XE_RXMASK_ALIGNERRIE | XE_RXMASK_CRCERRIE | XE_RXMASK_OVERFLOWIE);
542 1.1 dbj
543 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RXSTAT, XE_RXSTAT_CLEAR);
544 1.1 dbj
545 1.1 dbj {
546 1.1 dbj int i;
547 1.1 dbj for(i=0;i<sizeof(sc->sc_enaddr);i++) {
548 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh,XE_ENADDR+i,sc->sc_enaddr[i]);
549 1.1 dbj }
550 1.1 dbj }
551 1.1 dbj
552 1.1 dbj DPRINTF(("%s: initializing ethernet %02x:%02x:%02x:%02x:%02x:%02x, size=%d\n",
553 1.1 dbj sc->sc_dev.dv_xname,
554 1.1 dbj sc->sc_enaddr[0],sc->sc_enaddr[1],sc->sc_enaddr[2],
555 1.1 dbj sc->sc_enaddr[3],sc->sc_enaddr[4],sc->sc_enaddr[5],
556 1.1 dbj sizeof(sc->sc_enaddr)));
557 1.1 dbj
558 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RESET, 0);
559 1.1 dbj
560 1.1 dbj ifp->if_flags |= IFF_RUNNING;
561 1.1 dbj ifp->if_flags &= ~IFF_OACTIVE;
562 1.1 dbj ifp->if_timer = 0;
563 1.1 dbj
564 1.1 dbj nextdma_init(sc->sc_tx_nd);
565 1.1 dbj nextdma_init(sc->sc_rx_nd);
566 1.1 dbj
567 1.1 dbj nextdma_start(sc->sc_rx_nd, DMACSR_READ);
568 1.1 dbj
569 1.1 dbj if (ifp->if_snd.ifq_head != NULL) {
570 1.1 dbj mb8795_start(ifp);
571 1.1 dbj }
572 1.1 dbj }
573 1.1 dbj
574 1.1 dbj void
575 1.1 dbj mb8795_stop(sc)
576 1.1 dbj struct mb8795_softc *sc;
577 1.1 dbj {
578 1.1 dbj printf("%s: stop not implemented\n", sc->sc_dev.dv_xname);
579 1.1 dbj }
580 1.1 dbj
581 1.1 dbj
582 1.1 dbj void
583 1.1 dbj mb8795_shutdown(arg)
584 1.1 dbj void *arg;
585 1.1 dbj {
586 1.1 dbj struct mb8795_softc *sc = (struct mb8795_softc *)arg;
587 1.1 dbj mb8795_stop(sc);
588 1.1 dbj }
589 1.1 dbj
590 1.1 dbj /****************************************************************/
591 1.1 dbj int
592 1.1 dbj mb8795_ioctl(ifp, cmd, data)
593 1.1 dbj register struct ifnet *ifp;
594 1.1 dbj u_long cmd;
595 1.1 dbj caddr_t data;
596 1.1 dbj {
597 1.1 dbj register struct mb8795_softc *sc = ifp->if_softc;
598 1.1 dbj struct ifaddr *ifa = (struct ifaddr *)data;
599 1.1 dbj struct ifreq *ifr = (struct ifreq *)data;
600 1.1 dbj int s, error = 0;
601 1.1 dbj
602 1.1 dbj s = splimp();
603 1.1 dbj
604 1.1 dbj switch (cmd) {
605 1.1 dbj
606 1.1 dbj case SIOCSIFADDR:
607 1.1 dbj ifp->if_flags |= IFF_UP;
608 1.1 dbj
609 1.1 dbj switch (ifa->ifa_addr->sa_family) {
610 1.1 dbj #ifdef INET
611 1.1 dbj case AF_INET:
612 1.1 dbj mb8795_init(sc);
613 1.1 dbj arp_ifinit(ifp, ifa);
614 1.1 dbj break;
615 1.1 dbj #endif
616 1.1 dbj #ifdef NS
617 1.1 dbj case AF_NS:
618 1.1 dbj {
619 1.1 dbj register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
620 1.1 dbj
621 1.1 dbj if (ns_nullhost(*ina))
622 1.1 dbj ina->x_host =
623 1.1 dbj *(union ns_host *)LLADDR(ifp->if_sadl);
624 1.1 dbj else {
625 1.1 dbj bcopy(ina->x_host.c_host,
626 1.1 dbj LLADDR(ifp->if_sadl),
627 1.1 dbj sizeof(sc->sc_enaddr));
628 1.1 dbj }
629 1.1 dbj /* Set new address. */
630 1.1 dbj mb8795_init(sc);
631 1.1 dbj break;
632 1.1 dbj }
633 1.1 dbj #endif
634 1.1 dbj default:
635 1.1 dbj mb8795_init(sc);
636 1.1 dbj break;
637 1.1 dbj }
638 1.1 dbj break;
639 1.1 dbj
640 1.1 dbj #if defined(CCITT) && defined(LLC)
641 1.1 dbj case SIOCSIFCONF_X25:
642 1.1 dbj ifp->if_flags |= IFF_UP;
643 1.1 dbj ifa->ifa_rtrequest = cons_rtrequest; /* XXX */
644 1.1 dbj error = x25_llcglue(PRC_IFUP, ifa->ifa_addr);
645 1.1 dbj if (error == 0)
646 1.1 dbj mb8795_init(sc);
647 1.1 dbj break;
648 1.1 dbj #endif /* CCITT && LLC */
649 1.1 dbj
650 1.1 dbj case SIOCSIFFLAGS:
651 1.1 dbj if ((ifp->if_flags & IFF_UP) == 0 &&
652 1.1 dbj (ifp->if_flags & IFF_RUNNING) != 0) {
653 1.1 dbj /*
654 1.1 dbj * If interface is marked down and it is running, then
655 1.1 dbj * stop it.
656 1.1 dbj */
657 1.1 dbj mb8795_stop(sc);
658 1.1 dbj ifp->if_flags &= ~IFF_RUNNING;
659 1.1 dbj } else if ((ifp->if_flags & IFF_UP) != 0 &&
660 1.1 dbj (ifp->if_flags & IFF_RUNNING) == 0) {
661 1.1 dbj /*
662 1.1 dbj * If interface is marked up and it is stopped, then
663 1.1 dbj * start it.
664 1.1 dbj */
665 1.1 dbj mb8795_init(sc);
666 1.1 dbj } else {
667 1.1 dbj /*
668 1.1 dbj * Reset the interface to pick up changes in any other
669 1.1 dbj * flags that affect hardware registers.
670 1.1 dbj */
671 1.1 dbj /*mb8795_stop(sc);*/
672 1.1 dbj mb8795_init(sc);
673 1.1 dbj }
674 1.1 dbj #ifdef XE_DEBUG
675 1.1 dbj if (ifp->if_flags & IFF_DEBUG)
676 1.1 dbj sc->sc_debug = 1;
677 1.1 dbj else
678 1.1 dbj sc->sc_debug = 0;
679 1.1 dbj #endif
680 1.1 dbj break;
681 1.1 dbj
682 1.1 dbj case SIOCADDMULTI:
683 1.1 dbj case SIOCDELMULTI:
684 1.1 dbj error = (cmd == SIOCADDMULTI) ?
685 1.1 dbj ether_addmulti(ifr, &sc->sc_ethercom) :
686 1.1 dbj ether_delmulti(ifr, &sc->sc_ethercom);
687 1.1 dbj
688 1.1 dbj if (error == ENETRESET) {
689 1.1 dbj /*
690 1.1 dbj * Multicast list has changed; set the hardware filter
691 1.1 dbj * accordingly.
692 1.1 dbj */
693 1.1 dbj mb8795_reset(sc);
694 1.1 dbj error = 0;
695 1.1 dbj }
696 1.1 dbj break;
697 1.1 dbj
698 1.1 dbj #if 0
699 1.1 dbj case SIOCGIFMEDIA:
700 1.1 dbj case SIOCSIFMEDIA:
701 1.1 dbj error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
702 1.1 dbj break;
703 1.1 dbj #endif
704 1.1 dbj
705 1.1 dbj default:
706 1.1 dbj error = EINVAL;
707 1.1 dbj break;
708 1.1 dbj }
709 1.1 dbj
710 1.1 dbj splx(s);
711 1.1 dbj
712 1.1 dbj #if 0
713 1.1 dbj DPRINTF(("DEBUG: mb8795_ioctl(0x%lx) returning %d\n",
714 1.1 dbj cmd,error));
715 1.1 dbj #endif
716 1.1 dbj
717 1.1 dbj return (error);
718 1.1 dbj }
719 1.1 dbj
720 1.1 dbj /*
721 1.1 dbj * Setup output on interface.
722 1.1 dbj * Get another datagram to send off of the interface queue, and map it to the
723 1.1 dbj * interface before starting the output.
724 1.1 dbj * Called only at splimp or interrupt level.
725 1.1 dbj */
726 1.1 dbj void
727 1.1 dbj mb8795_start(ifp)
728 1.1 dbj struct ifnet *ifp;
729 1.1 dbj {
730 1.1 dbj int error;
731 1.1 dbj struct mb8795_softc *sc = ifp->if_softc;
732 1.1 dbj
733 1.1 dbj if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
734 1.1 dbj return;
735 1.1 dbj
736 1.1 dbj DPRINTF(("%s: mb8795_start()\n",sc->sc_dev.dv_xname));
737 1.1 dbj
738 1.1 dbj #if (defined(DIAGNOSTIC))
739 1.1 dbj {
740 1.1 dbj u_char txstat;
741 1.1 dbj txstat = bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_TXSTAT);
742 1.1 dbj if (!(txstat & XE_TXSTAT_READY)) {
743 1.1 dbj panic("%s: transmitter not ready\n", sc->sc_dev.dv_xname);
744 1.1 dbj }
745 1.1 dbj }
746 1.1 dbj #endif
747 1.1 dbj
748 1.1 dbj #if 0
749 1.1 dbj return; /* @@@ Turn off xmit for debugging */
750 1.1 dbj #endif
751 1.1 dbj
752 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXSTAT, XE_TXSTAT_CLEAR);
753 1.1 dbj
754 1.1 dbj IF_DEQUEUE(&ifp->if_snd, sc->sc_tx_mb_head);
755 1.1 dbj if (sc->sc_tx_mb_head == 0) {
756 1.1 dbj printf("%s: No packet to start\n",
757 1.1 dbj sc->sc_dev.dv_xname);
758 1.1 dbj return;
759 1.1 dbj }
760 1.1 dbj
761 1.1 dbj ifp->if_timer = 5;
762 1.1 dbj
763 1.1 dbj /* The following is a next specific hack that should
764 1.1 dbj * probably be moved out of MI code.
765 1.1 dbj * This macro assumes it can move forward as needed
766 1.1 dbj * in the buffer. Perhaps it should zero the extra buffer.
767 1.1 dbj */
768 1.1 dbj #define REALIGN_DMABUF(s,l) \
769 1.1 dbj { (s) = ((u_char *)(((unsigned)(s)+DMA_BEGINALIGNMENT-1) \
770 1.1 dbj &~(DMA_BEGINALIGNMENT-1))); \
771 1.1 dbj (l) = ((u_char *)(((unsigned)((s)+(l))+ENDMA_ENDALIGNMENT-1) \
772 1.1 dbj &~(ENDMA_ENDALIGNMENT-1)))-(s);}
773 1.1 dbj
774 1.1 dbj #if 0
775 1.1 dbj error = bus_dmamap_load_mbuf(sc->sc_tx_dmat,
776 1.1 dbj sc->sc_tx_dmamap,
777 1.1 dbj sc->sc_tx_mb_head,
778 1.1 dbj BUS_DMA_NOWAIT);
779 1.1 dbj #else
780 1.1 dbj {
781 1.1 dbj u_char *buf = sc->sc_txbuf;
782 1.1 dbj int buflen = 0;
783 1.1 dbj struct mbuf *m = sc->sc_tx_mb_head;
784 1.1 dbj buflen = m->m_pkthdr.len;
785 1.1 dbj
786 1.1 dbj /* Fix runt packets, @@@ memory overrun */
787 1.1 dbj if (buflen < ETHERMIN+sizeof(struct ether_header)) {
788 1.1 dbj buflen = ETHERMIN+sizeof(struct ether_header);
789 1.1 dbj }
790 1.1 dbj
791 1.1 dbj buflen += 15;
792 1.1 dbj REALIGN_DMABUF(buf,buflen);
793 1.1 dbj if (buflen > 1520) {
794 1.1 dbj panic("%s: packet too long\n",sc->sc_dev.dv_xname);
795 1.1 dbj }
796 1.1 dbj
797 1.1 dbj {
798 1.1 dbj u_char *p = buf;
799 1.1 dbj for (m=sc->sc_tx_mb_head; m; m = m->m_next) {
800 1.1 dbj if (m->m_len == 0) continue;
801 1.1 dbj bcopy(mtod(m, u_char *), p, m->m_len);
802 1.1 dbj p += m->m_len;
803 1.1 dbj }
804 1.1 dbj }
805 1.1 dbj
806 1.1 dbj error = bus_dmamap_load(sc->sc_tx_dmat, sc->sc_tx_dmamap,
807 1.1 dbj buf,buflen,NULL,BUS_DMA_NOWAIT);
808 1.1 dbj }
809 1.1 dbj #endif
810 1.1 dbj if (error) {
811 1.1 dbj printf("%s: can't load mbuf chain, error = %d\n",
812 1.1 dbj sc->sc_dev.dv_xname, error);
813 1.1 dbj m_freem(sc->sc_tx_mb_head);
814 1.1 dbj sc->sc_tx_mb_head = NULL;
815 1.1 dbj return;
816 1.1 dbj }
817 1.1 dbj sc->sc_tx_loaded++;
818 1.1 dbj
819 1.1 dbj #ifdef DIAGNOSTIC
820 1.1 dbj if (sc->sc_tx_loaded != 1) {
821 1.1 dbj panic("%s: sc->sc_tx_loaded is %d",sc->sc_dev.dv_xname,
822 1.1 dbj sc->sc_tx_loaded);
823 1.1 dbj }
824 1.1 dbj #endif
825 1.1 dbj
826 1.1 dbj ifp->if_flags |= IFF_OACTIVE;
827 1.1 dbj
828 1.1 dbj bus_dmamap_sync(sc->sc_tx_dmat, sc->sc_tx_dmamap, 0,
829 1.1 dbj sc->sc_tx_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE);
830 1.1 dbj
831 1.1 dbj nextdma_start(sc->sc_tx_nd, DMACSR_WRITE);
832 1.1 dbj
833 1.1 dbj #if NBPFILTER > 0
834 1.1 dbj /*
835 1.1 dbj * Pass packet to bpf if there is a listener.
836 1.1 dbj */
837 1.1 dbj if (ifp->if_bpf)
838 1.1 dbj bpf_mtap(ifp->if_bpf, sc->sc_tx_mb_head);
839 1.1 dbj #endif
840 1.1 dbj
841 1.1 dbj }
842 1.1 dbj
843 1.1 dbj /****************************************************************/
844 1.1 dbj
845 1.1 dbj void
846 1.1 dbj mb8795_txdma_completed(map, arg)
847 1.1 dbj bus_dmamap_t map;
848 1.1 dbj void *arg;
849 1.1 dbj {
850 1.1 dbj struct mb8795_softc *sc = arg;
851 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
852 1.1 dbj
853 1.1 dbj DPRINTF(("%s: mb8795_txdma_completed()\n",sc->sc_dev.dv_xname));
854 1.1 dbj
855 1.1 dbj #ifdef DIAGNOSTIC
856 1.1 dbj if (!sc->sc_tx_loaded) {
857 1.1 dbj panic("%s: tx completed never loaded ",sc->sc_dev.dv_xname);
858 1.1 dbj }
859 1.1 dbj if (map != sc->sc_tx_dmamap) {
860 1.1 dbj panic("%s: unexpected tx completed map",sc->sc_dev.dv_xname);
861 1.1 dbj }
862 1.1 dbj
863 1.1 dbj #endif
864 1.1 dbj }
865 1.1 dbj
866 1.1 dbj void
867 1.1 dbj mb8795_txdma_shutdown(arg)
868 1.1 dbj void *arg;
869 1.1 dbj {
870 1.1 dbj struct mb8795_softc *sc = arg;
871 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
872 1.1 dbj
873 1.1 dbj DPRINTF(("%s: mb8795_txdma_shutdown()\n",sc->sc_dev.dv_xname));
874 1.1 dbj
875 1.1 dbj #ifdef DIAGNOSTIC
876 1.1 dbj if (!sc->sc_tx_loaded) {
877 1.1 dbj panic("%s: tx shutdown never loaded ",sc->sc_dev.dv_xname);
878 1.1 dbj }
879 1.1 dbj #endif
880 1.1 dbj
881 1.1 dbj {
882 1.1 dbj
883 1.1 dbj if (sc->sc_tx_loaded) {
884 1.1 dbj bus_dmamap_sync(sc->sc_tx_dmat, sc->sc_tx_dmamap,
885 1.1 dbj 0, sc->sc_tx_dmamap->dm_mapsize,
886 1.1 dbj BUS_DMASYNC_POSTWRITE);
887 1.1 dbj bus_dmamap_unload(sc->sc_tx_dmat, sc->sc_tx_dmamap);
888 1.1 dbj m_freem(sc->sc_tx_mb_head);
889 1.1 dbj sc->sc_tx_mb_head = NULL;
890 1.1 dbj
891 1.1 dbj sc->sc_tx_loaded--;
892 1.1 dbj }
893 1.1 dbj
894 1.1 dbj #ifdef DIAGNOSTIC
895 1.1 dbj if (sc->sc_tx_loaded != 0) {
896 1.1 dbj panic("%s: sc->sc_tx_loaded is %d",sc->sc_dev.dv_xname,
897 1.1 dbj sc->sc_tx_loaded);
898 1.1 dbj }
899 1.1 dbj #endif
900 1.1 dbj
901 1.1 dbj ifp->if_flags &= ~IFF_OACTIVE;
902 1.1 dbj
903 1.1 dbj ifp->if_timer = 0;
904 1.1 dbj
905 1.1 dbj if (ifp->if_snd.ifq_head != NULL) {
906 1.1 dbj mb8795_start(ifp);
907 1.1 dbj }
908 1.1 dbj
909 1.1 dbj }
910 1.1 dbj
911 1.1 dbj #if 0
912 1.1 dbj /* Enable ready interrupt */
913 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK,
914 1.1 dbj bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK)
915 1.1 dbj | XE_TXMASK_READYIE);
916 1.1 dbj #endif
917 1.1 dbj }
918 1.1 dbj
919 1.1 dbj
920 1.1 dbj void
921 1.1 dbj mb8795_rxdma_completed(map, arg)
922 1.1 dbj bus_dmamap_t map;
923 1.1 dbj void *arg;
924 1.1 dbj {
925 1.1 dbj struct mb8795_softc *sc = arg;
926 1.1 dbj
927 1.1 dbj sc->sc_rx_completed_idx++;
928 1.1 dbj sc->sc_rx_completed_idx %= MB8795_NRXBUFS;
929 1.1 dbj
930 1.1 dbj DPRINTF(("%s: mb8795_rxdma_completed(), sc->sc_rx_completed_idx = %d\n",
931 1.1 dbj sc->sc_dev.dv_xname, sc->sc_rx_completed_idx));
932 1.1 dbj
933 1.1 dbj #if (defined(DIAGNOSTIC))
934 1.1 dbj if (map != sc->sc_rx_dmamap[sc->sc_rx_completed_idx]) {
935 1.1 dbj panic("%s: Unexpected rx dmamap completed\n",
936 1.1 dbj sc->sc_dev.dv_xname);
937 1.1 dbj }
938 1.1 dbj #endif
939 1.1 dbj }
940 1.1 dbj
941 1.1 dbj void
942 1.1 dbj mb8795_rxdma_shutdown(arg)
943 1.1 dbj void *arg;
944 1.1 dbj {
945 1.1 dbj struct mb8795_softc *sc = arg;
946 1.1 dbj
947 1.1 dbj printf("%s: mb8795_rxdma_shutdown(), resetting the interface\n",
948 1.1 dbj sc->sc_dev.dv_xname);
949 1.1 dbj
950 1.1 dbj /* we might want to just reset the DMA here instead,
951 1.1 dbj * but this will do.
952 1.1 dbj */
953 1.1 dbj mb8795_init(sc);
954 1.1 dbj }
955 1.1 dbj
956 1.1 dbj
957 1.1 dbj /*
958 1.1 dbj * load a dmamap with a freshly allocated mbuf
959 1.1 dbj */
960 1.1 dbj struct mbuf *
961 1.1 dbj mb8795_rxdmamap_load(sc,map)
962 1.1 dbj struct mb8795_softc *sc;
963 1.1 dbj bus_dmamap_t map;
964 1.1 dbj {
965 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
966 1.1 dbj struct mbuf *m;
967 1.1 dbj int error;
968 1.1 dbj
969 1.1 dbj MGETHDR(m, M_DONTWAIT, MT_DATA);
970 1.1 dbj if (m) {
971 1.1 dbj MCLGET(m, M_DONTWAIT);
972 1.1 dbj if ((m->m_flags & M_EXT) == 0) {
973 1.1 dbj m_freem(m);
974 1.1 dbj m = NULL;
975 1.1 dbj } else {
976 1.1 dbj m->m_len = MCLBYTES;
977 1.1 dbj }
978 1.1 dbj }
979 1.1 dbj if (!m) {
980 1.1 dbj /* @@@ Handle this gracefully by reusing a scratch buffer
981 1.1 dbj * or something.
982 1.1 dbj */
983 1.1 dbj panic("Unable to get memory for incoming ethernet\n");
984 1.1 dbj }
985 1.1 dbj
986 1.1 dbj /* Align buffer, @@@ next specific.
987 1.1 dbj * perhaps should be using M_ALIGN here instead?
988 1.1 dbj * First we give us a little room to align with.
989 1.1 dbj */
990 1.1 dbj {
991 1.1 dbj u_char *buf = m->m_data;
992 1.1 dbj int buflen = m->m_len;
993 1.1 dbj buflen -= ENDMA_ENDALIGNMENT+DMA_BEGINALIGNMENT;
994 1.1 dbj REALIGN_DMABUF(buf, buflen);
995 1.1 dbj m->m_data = buf;
996 1.1 dbj m->m_len = buflen;
997 1.1 dbj }
998 1.1 dbj
999 1.1 dbj m->m_pkthdr.rcvif = ifp;
1000 1.1 dbj m->m_pkthdr.len = m->m_len;
1001 1.1 dbj
1002 1.1 dbj error = bus_dmamap_load_mbuf(sc->sc_rx_dmat,
1003 1.1 dbj map, m, BUS_DMA_NOWAIT);
1004 1.1 dbj
1005 1.1 dbj bus_dmamap_sync(sc->sc_rx_dmat, map, 0,
1006 1.1 dbj map->dm_mapsize, BUS_DMASYNC_PREREAD);
1007 1.1 dbj
1008 1.1 dbj if (error) {
1009 1.1 dbj DPRINTF(("DEBUG: m->m_data = 0x%08x, m->m_len = %d\n",
1010 1.1 dbj m->m_data, m->m_len));
1011 1.1 dbj DPRINTF(("DEBUG: MCLBYTES = %d, map->_dm_size = %d\n",
1012 1.1 dbj MCLBYTES, map->_dm_size));
1013 1.1 dbj
1014 1.1 dbj panic("%s: can't load rx mbuf chain, error = %d\n",
1015 1.1 dbj sc->sc_dev.dv_xname, error);
1016 1.1 dbj m_freem(m);
1017 1.1 dbj m = NULL;
1018 1.1 dbj }
1019 1.1 dbj
1020 1.1 dbj return(m);
1021 1.1 dbj }
1022 1.1 dbj
1023 1.1 dbj bus_dmamap_t
1024 1.1 dbj mb8795_rxdma_continue(arg)
1025 1.1 dbj void *arg;
1026 1.1 dbj {
1027 1.1 dbj struct mb8795_softc *sc = arg;
1028 1.1 dbj bus_dmamap_t map = NULL;
1029 1.1 dbj
1030 1.1 dbj /*
1031 1.1 dbj * Currently, starts dumping new packets if the buffers
1032 1.1 dbj * fill up. This should probably reclaim unhandled
1033 1.1 dbj * buffers instead so we drop older packets instead
1034 1.1 dbj * of newer ones.
1035 1.1 dbj */
1036 1.1 dbj if (((sc->sc_rx_loaded_idx+1)%MB8795_NRXBUFS) != sc->sc_rx_handled_idx) {
1037 1.1 dbj sc->sc_rx_loaded_idx++;
1038 1.1 dbj sc->sc_rx_loaded_idx %= MB8795_NRXBUFS;
1039 1.1 dbj map = sc->sc_rx_dmamap[sc->sc_rx_loaded_idx];
1040 1.1 dbj
1041 1.1 dbj DPRINTF(("%s: mb8795_rxdma_continue() sc->sc_rx_loaded_idx = %d\nn",
1042 1.1 dbj sc->sc_dev.dv_xname,sc->sc_rx_loaded_idx));
1043 1.1 dbj }
1044 1.1 dbj #if (defined(DIAGNOSTIC))
1045 1.1 dbj else {
1046 1.1 dbj panic("%s: out of receive DMA buffers\n",sc->sc_dev.dv_xname);
1047 1.1 dbj }
1048 1.1 dbj #endif
1049 1.1 dbj
1050 1.1 dbj return(map);
1051 1.1 dbj }
1052 1.1 dbj
1053 1.1 dbj bus_dmamap_t
1054 1.1 dbj mb8795_txdma_continue(arg)
1055 1.1 dbj void *arg;
1056 1.1 dbj {
1057 1.1 dbj struct mb8795_softc *sc = arg;
1058 1.1 dbj bus_dmamap_t map = sc->sc_tx_dmamap;
1059 1.1 dbj
1060 1.1 dbj DPRINTF(("%s: mb8795_txdma_continue()\n",sc->sc_dev.dv_xname));
1061 1.1 dbj
1062 1.1 dbj #ifdef DIAGNOSTIC
1063 1.1 dbj if (sc->sc_tx_loaded != 1) {
1064 1.1 dbj panic("%s: sc->sc_tx_loaded is %d",sc->sc_dev.dv_xname,
1065 1.1 dbj sc->sc_tx_loaded);
1066 1.1 dbj }
1067 1.1 dbj #endif
1068 1.1 dbj
1069 1.1 dbj return(map);
1070 1.1 dbj }
1071 1.1 dbj
1072 1.1 dbj
1073 1.1 dbj /****************************************************************/
1074 1.1 dbj #if 0
1075 1.1 dbj int
1076 1.1 dbj mb8795_mediachange(ifp)
1077 1.1 dbj struct ifnet *ifp;
1078 1.1 dbj {
1079 1.1 dbj struct mb8795_softc *sc = ifp->if_softc;
1080 1.1 dbj
1081 1.1 dbj if (sc->sc_mediachange)
1082 1.1 dbj return ((*sc->sc_mediachange)(sc));
1083 1.1 dbj return (EINVAL);
1084 1.1 dbj }
1085 1.1 dbj
1086 1.1 dbj void
1087 1.1 dbj mb8795_mediastatus(ifp, ifmr)
1088 1.1 dbj struct ifnet *ifp;
1089 1.1 dbj struct ifmediareq *ifmr;
1090 1.1 dbj {
1091 1.1 dbj struct mb8795_softc *sc = ifp->if_softc;
1092 1.1 dbj
1093 1.1 dbj if ((ifp->if_flags & IFF_UP) == 0)
1094 1.1 dbj return;
1095 1.1 dbj
1096 1.1 dbj ifmr->ifm_status = IFM_AVALID;
1097 1.1 dbj if (sc->sc_havecarrier)
1098 1.1 dbj ifmr->ifm_status |= IFM_ACTIVE;
1099 1.1 dbj
1100 1.1 dbj if (sc->sc_mediastatus)
1101 1.1 dbj (*sc->sc_mediastatus)(sc, ifmr);
1102 1.1 dbj }
1103 1.1 dbj #endif
1104 1.1 dbj /****************************************************************/
1105